clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz

clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz

[ Upstream commit dafebd0f9a4f56b10d7fbda0bff1f540d16a2ea4 ]

PLL rate on RK356x is calculated through the simple formula:
((24000000 / _refdiv) * _fbdiv) / (_postdiv1 * _postdiv2)

The PLL rate setting for 78.75MHz seems to be copied from 96MHz
so this patch fixes it and configures it properly.

Signed-off-by: Alibek Omarov <a1ba.omarov@gmail.com>
Fixes: 842f4cb72639 ("clk: rockchip: Add more PLL rates for rk3568")
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20230614134750.1056293-1-a1ba.omarov@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>