[ARM] Ensure we preserve other CPSR bits when switching to SVC mode.

diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index c300acd5a38595b641982fe9ceda497960109550..0268780931bd02b224f99e74831e7f3889e2d5ee 100644 (file)
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -1028,8 +1028,10 @@ vector_IRQ:      @
                @
                @ now branch to the relevant MODE handling routine
                @
-               mov     r13, #PSR_I_BIT | MODE_SVC
-               msr     spsr_c, r13                     @ switch to SVC_32 mode
+               mrs     r13, cpsr
+               bic     r13, r13, #MODE_MASK
+               orr     r13, r13, #MODE_SVC
+               msr     spsr, r13                       @ switch to SVC_32 mode
 
                and     lr, lr, #15
                ldr     lr, [pc, lr, lsl #2]