drm/xe/xe_gt_idle: Add CCS to the powergating info print

[ Upstream commit 369ba0d1efe91cccabe98ae53c53b7425f327edf ]

While reading the main GT powergating info from debugfs, include both
RCS and CCS engine masks.

Fixes: 0914c1e45d3a1 ("drm/xe/xe_gt_idle: add debugfs entry for powergating info")
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patch.msgid.link/20260819073457.1812722-2-balasubramani.vivekanandan@intel.com
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
(cherry picked from commit 8899e413c5ab85443ec9bbc50cffe924c6b596de)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/xe/xe_gt_idle.c b/drivers/gpu/drm/xe/xe_gt_idle.c
index 3e3d1d52f6302621e72b7dca4b19b8d9ab324528..81e3ec7ff4fdd95ad2bb9ec80ff9d60e8759f84d 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt_idle.c
+++ b/drivers/gpu/drm/xe/xe_gt_idle.c
@@ -236,7 +236,8 @@ int xe_gt_idle_pg_print(struct xe_gt *gt, struct drm_printer *p)
                xe_force_wake_put(gt_to_fw(gt), fw_ref);
        }
 
-       if (gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK) {
+       if (gt->info.engine_mask &
+           (XE_HW_ENGINE_RCS_MASK | XE_HW_ENGINE_CCS_MASK)) {
                drm_printf(p, "Render Power Gating Enabled: %s\n",
                           str_yes_no(pg_enabled & RENDER_POWERGATE_ENABLE));