drm/xe/xe3: Apply Wa_16029380221 to media

Apply Wa_16029380221 to Xe3p_LPM.

The Xe3p_LPM media page walker is hard-wired NonCoherent and cannot
observe CPU:WB cached page table data. Force page tables to CPU:WC
by clearing has_cached_pt when MEDIA_VERSION(3500) is detected.

v2: Simplify code comment to avoid duplicating information
    already present in xe_wa_oob.rules. (Gustavo)

Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
Link: https://patch.msgid.link/20260611162828.3879694-2-nitin.r.gote@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index d224861b6f6fd954d506ad6e82c7943666688bbf..f73d407e1e7f3a7c8fce2713071bbe1d8ea59779 100644 (file)
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -948,6 +948,15 @@ int xe_device_probe(struct xe_device *xe)
                        return err;
        }
 
+       /*
+        * Wa_16029380221: The affected GT will always use non-coherent
+        * access to page tables, so we must do uncached writes from the
+        * CPU.
+        */
+       for_each_gt(gt, xe, id)
+               if (XE_GT_WA(gt, 16029380221))
+                       xe->info.has_cached_pt = false;
+
        for_each_tile(tile, xe, id) {
                err = xe_ggtt_init_early(tile->mem.ggtt);
                if (err)

diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index f8a185103b80576e5da739731820e8393c484662..9027365f0043428c0b31432664c4991ee58f6f6d 100644 (file)
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -65,3 +65,4 @@
 
 14025883347    MEDIA_VERSION_RANGE(1301, 3503)
                GRAPHICS_VERSION_RANGE(2004, 3005)
+16029380221    MEDIA_VERSION(3500)