[PATCH] ATI Mach64 build fix

From: Geert Uytterhoeven <geert@linux-m68k.org>

Atyfb: Add missing parts of reversal of Mobility changes, allowing ATI Mach64
GX support to compile again.

diff --git a/drivers/video/aty/mach64_gx.c b/drivers/video/aty/mach64_gx.c
index a27b9bcd885916fa9dcc46dfdcf509fe9f0167f6..85168a32eea87aecbaa161aea3d06c5e1bf722cd 100644 (file)
--- a/drivers/video/aty/mach64_gx.c
+++ b/drivers/video/aty/mach64_gx.c
@@ -119,7 +119,7 @@ static int aty_set_dac_514(const struct fb_info *info,
 }
 
 static int aty_var_to_pll_514(const struct fb_info *info, u32 vclk_per,
-                             u32 bpp, u32 width, union aty_pll *pll)
+                             u8 bpp, union aty_pll *pll)
 {
        /*
         *  FIXME: use real calculations instead of using fixed values from the old
@@ -338,7 +338,7 @@ const struct aty_dac_ops aty_dac_att21c498 = {
      */
 
 static int aty_var_to_pll_18818(const struct fb_info *info, u32 vclk_per,
-                               u32 bpp, u32 width, union aty_pll *pll)
+                               u8 bpp, union aty_pll *pll)
 {
        u32 MHz100;             /* in 0.01 MHz */
        u32 program_bits;
@@ -494,7 +494,7 @@ const struct aty_pll_ops aty_pll_ati18818_1 = {
      */
 
 static int aty_var_to_pll_1703(const struct fb_info *info, u32 vclk_per,
-                              u32 bpp, u32 width, union aty_pll *pll)
+                              u32 vclk_per, u8 bpp, union aty_pll *pll)
 {
        u32 mhz100;             /* in 0.01 MHz */
        u32 program_bits;
@@ -610,7 +610,7 @@ const struct aty_pll_ops aty_pll_stg1703 = {
      */
 
 static int aty_var_to_pll_8398(const struct fb_info *info, u32 vclk_per,
-                              u32 bpp, u32 width, union aty_pll *pll)
+                              u32 vclk_per, u8 bpp, union aty_pll *pll)
 {
        u32 tempA, tempB, fOut, longMHz100, diff, preDiff;
 
@@ -734,7 +734,7 @@ const struct aty_pll_ops aty_pll_ch8398 = {
      */
 
 static int aty_var_to_pll_408(const struct fb_info *info, u32 vclk_per,
-                             u32 bpp, u32 width, union aty_pll *pll)
+                             u8 bpp, union aty_pll *pll)
 {
        u32 mhz100;             /* in 0.01 MHz */
        u32 program_bits;