net: xilinx: axienet: Schedule NAPI in two steps

[ Upstream commit ba0da2dc934ec5ac32bbeecbd0670da16ba03565 ]

As advised by Documentation/networking/napi.rst, masking IRQs after
calling napi_schedule can be racy. Avoid this by only masking/scheduling
if napi_schedule_prep returns true.

Fixes: 9e2bc267e780 ("net: axienet: Use NAPI for TX completion path")
Fixes: cc37610caaf8 ("net: axienet: implement NAPI and GRO receive")
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Reviewed-by: Shannon Nelson <shannon.nelson@amd.com>
Reviewed-by: Eric Dumazet <edumazet@google.com>
Link: https://patch.msgid.link/20240913145711.2284295-1-sean.anderson@linux.dev
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index 88d7bc2ea7132602a3cffd59414ead7c5955c21a..00b1a4cf7c4be617c90cfd092b165373e08eff57 100644 (file)
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -1222,9 +1222,10 @@ static irqreturn_t axienet_tx_irq(int irq, void *_ndev)
                u32 cr = lp->tx_dma_cr;
 
                cr &= ~(XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK);
-               axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
-
-               napi_schedule(&lp->napi_tx);
+               if (napi_schedule_prep(&lp->napi_tx)) {
+                       axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
+                       __napi_schedule(&lp->napi_tx);
+               }
        }
 
        return IRQ_HANDLED;
@@ -1266,9 +1267,10 @@ static irqreturn_t axienet_rx_irq(int irq, void *_ndev)
                u32 cr = lp->rx_dma_cr;
 
                cr &= ~(XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK);
-               axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
-
-               napi_schedule(&lp->napi_rx);
+               if (napi_schedule_prep(&lp->napi_rx)) {
+                       axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
+                       __napi_schedule(&lp->napi_rx);
+               }
        }
 
        return IRQ_HANDLED;