dmaengine: fsl-qdma: fix SoC may hang on 16 byte unaligned read

commit 9d739bccf261dd93ec1babf82f5c5d71dd4caa3e upstream.

There is chip (ls1028a) errata:

The SoC may hang on 16 byte unaligned read transactions by QDMA.

Unaligned read transactions initiated by QDMA may stall in the NOC
(Network On-Chip), causing a deadlock condition. Stalled transactions will
trigger completion timeouts in PCIe controller.

Workaround:
Enable prefetch by setting the source descriptor prefetchable bit
( SD[PF] = 1 ).

Implement this workaround.

Cc: stable@vger.kernel.org
Fixes: b092529e0aa0 ("dmaengine: fsl-qdma: Add qDMA controller driver for Layerscape SoCs")
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20240201215007.439503-1-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c
index f383f219ed008d9440794ab1361f9a1df2104168..915fa0cbb55390ff049e9c2b944748e99ac33aaa 100644 (file)
--- a/drivers/dma/fsl-qdma.c
+++ b/drivers/dma/fsl-qdma.c
@@ -109,6 +109,7 @@
 #define FSL_QDMA_CMD_WTHROTL_OFFSET    20
 #define FSL_QDMA_CMD_DSEN_OFFSET       19
 #define FSL_QDMA_CMD_LWC_OFFSET                16
+#define FSL_QDMA_CMD_PF                        BIT(17)
 
 /* Field definition for Descriptor status */
 #define QDMA_CCDF_STATUS_RTE           BIT(5)
@@ -384,7 +385,8 @@ static void fsl_qdma_comp_fill_memcpy(struct fsl_qdma_comp *fsl_comp,
        qdma_csgf_set_f(csgf_dest, len);
        /* Descriptor Buffer */
        cmd = cpu_to_le32(FSL_QDMA_CMD_RWTTYPE <<
-                         FSL_QDMA_CMD_RWTTYPE_OFFSET);
+                         FSL_QDMA_CMD_RWTTYPE_OFFSET) |
+                         FSL_QDMA_CMD_PF;
        sdf->data = QDMA_SDDF_CMD(cmd);
 
        cmd = cpu_to_le32(FSL_QDMA_CMD_RWTTYPE <<