clk: qcom: gcc-sc8180x: Add GPLL9 support

commit 818a2f8d5e4ad2c1e39a4290158fe8e39a744c70 upstream.

Add the missing GPLL9 pll and fix the gcc_parents_7 data to use
the correct pll hw.

Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x")
Cc: stable@vger.kernel.org
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20240812-gcc-sc8180x-fixes-v2-3-8b3eaa5fb856@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c
index 9b2e53a0582542498d8dd3c8a32f5bc4e9bf43b9..e7523908f56da6b1970e7ef4423b05affa8a5c90 100644 (file)
--- a/drivers/clk/qcom/gcc-sc8180x.c
+++ b/drivers/clk/qcom/gcc-sc8180x.c
@@ -142,6 +142,23 @@ static struct clk_alpha_pll gpll7 = {
        },
 };
 
+static struct clk_alpha_pll gpll9 = {
+       .offset = 0x1c000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
+       .clkr = {
+               .enable_reg = 0x52000,
+               .enable_mask = BIT(9),
+               .hw.init = &(const struct clk_init_data) {
+                       .name = "gpll9",
+                       .parent_data = &(const struct clk_parent_data) {
+                               .fw_name = "bi_tcxo",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_alpha_pll_fixed_trion_ops,
+               },
+       },
+};
+
 static const struct parent_map gcc_parent_map_0[] = {
        { P_BI_TCXO, 0 },
        { P_GPLL0_OUT_MAIN, 1 },
@@ -241,7 +258,7 @@ static const struct parent_map gcc_parent_map_7[] = {
 static const struct clk_parent_data gcc_parents_7[] = {
        { .fw_name = "bi_tcxo", },
        { .hw = &gpll0.clkr.hw },
-       { .name = "gppl9" },
+       { .hw = &gpll9.clkr.hw },
        { .hw = &gpll4.clkr.hw },
        { .hw = &gpll0_out_even.clkr.hw },
 };
@@ -4448,6 +4465,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = {
        [GPLL1] = &gpll1.clkr,
        [GPLL4] = &gpll4.clkr,
        [GPLL7] = &gpll7.clkr,
+       [GPLL9] = &gpll9.clkr,
 };
 
 static const struct qcom_reset_map gcc_sc8180x_resets[] = {