#include "clock.h"
+/* clock information */
+
+unsigned long s3c24xx_xtal = 12*1000*1000; /* default 12MHz */
+unsigned long s3c24xx_fclk;
+unsigned long s3c24xx_hclk;
+unsigned long s3c24xx_pclk;
static LIST_HEAD(clocks);
static DECLARE_MUTEX(clocks_sem);
/* initialise the main system clocks */
- clk_h.rate = s3c2410_hclk;
- clk_p.rate = s3c2410_pclk;
- clk_f.rate = s3c2410_fclk;
+ clk_h.rate = s3c24xx_hclk;
+ clk_p.rate = s3c24xx_pclk;
+ clk_f.rate = s3c24xx_fclk;
/* set the enabled clocks to a minimal (known) state */
__raw_writel(S3C2410_CLKCON_PWMT | S3C2410_CLKCON_UART0 | S3C2410_CLKCON_UART1 | S3C2410_CLKCON_UART2 | S3C2410_CLKCON_GPIO | S3C2410_CLKCON_RTC, S3C2410_CLKCON);
unsigned long rate;
unsigned long ctrlbit;
};
+
+/* processor clock settings, in Hz */
+
+extern unsigned long s3c24xx_xtal;
+extern unsigned long s3c24xx_pclk;
+extern unsigned long s3c24xx_hclk;
+extern unsigned long s3c24xx_fclk;
int count;
tab = cpu_ids;
- for (count = 0; count < ARRAY_SIZE(cpu_ids); count++) {
+ for (count = 0; count < ARRAY_SIZE(cpu_ids); count++, tab++) {
if ((idcode & tab->idmask) == tab->idcode)
return tab;
}
#endif
extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
-
#include <asm/arch/regs-serial.h>
#include "s3c2410.h"
+#include "clock.h"
#include "devs.h"
#include "cpu.h"
[0] = {
.hwport = 0,
.flags = 0,
- .clock = &s3c2410_pclk,
+ .clock = &s3c24xx_pclk,
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
[1] = {
.hwport = 1,
.flags = 0,
- .clock = &s3c2410_pclk,
+ .clock = &s3c24xx_pclk,
.ucon = 0x245,
.ulcon = 0x03,
.ufcon = 0x00,
[2] = {
.hwport = 2,
.flags = 0,
- .clock = &s3c2410_pclk,
+ .clock = &s3c24xx_pclk,
.ucon = 0x3c5,
.ulcon = 0x43,
.ufcon = 0x51,
* 05-Sep-2003 BJD Moved to kernel v2.6
* 18-Jan-2004 BJD Added serial port configuration
* 21-Aug-2004 BJD Added new struct s3c2410_board handler
+ * 28-Sep-2004 BJD Updates for new serial port bits
*/
#include <linux/kernel.h>
#include "s3c2410.h"
#include "cpu.h"
+#include "clock.h"
int s3c2410_clock_tick_rate = 12*1000*1000; /* current timers at 12MHz */
struct s3c2410_uartcfg *s3c2410_uartcfgs;
-/* clock info */
-
-unsigned long s3c2410_fclk;
-unsigned long s3c2410_hclk;
-unsigned long s3c2410_pclk;
+/* Initial IO mappings */
static struct map_desc s3c2410_iodesc[] __initdata = {
IODESC_ENT(USBHOST),
&s3c_uart2
};
+/* store our uart devices for the serial driver console */
+struct platform_device *s3c2410_uart_devices[3];
+
+static int s3c2410_uart_count = 0;
+
+/* uart registration process */
+
+void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+ struct platform_device *platdev;
+ int uart;
+
+ s3c2410_uartcfgs = cfg; /* compatibility */
+
+ for (uart = 0; uart < no; uart++, cfg++) {
+ platdev = uart_devices[cfg->hwport];
+
+ s3c2410_uart_devices[uart] = platdev;
+ platdev->dev.platform_data = cfg;
+ }
+
+ s3c2410_uart_count = uart;
+}
+
+/* s3c2410_map_io
+ *
+ * register the standard cpu IO areas, and any passed in from the
+ * machine specific initialisation.
+ *
+ * this function also sets the initial clock frequencies from the
+ * settings passed in
+*/
+
void __init s3c2410_map_io(struct map_desc *mach_desc, int mach_size)
{
unsigned long tmp;
iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
iotable_init(mach_desc, mach_size);
- printk("machine_initted %p,%d\n", mach_desc, mach_size);
-
/* now we've got our machine bits initialised, work out what
* clocks we've got */
- s3c2410_fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), 12*MHZ);
+ s3c24xx_fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON),
+ s3c24xx_xtal);
tmp = __raw_readl(S3C2410_CLKDIVN);
- //printk("tmp=%08x, fclk=%d\n", tmp, s3c2410_fclk);
/* work out clock scalings */
- s3c2410_hclk = s3c2410_fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1);
- s3c2410_pclk = s3c2410_hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1);
+ s3c24xx_hclk = s3c24xx_fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1);
+ s3c24xx_pclk = s3c24xx_hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1);
/* print brieft summary of clocks, etc */
printk("S3C2410: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
- print_mhz(s3c2410_fclk), print_mhz(s3c2410_hclk),
- print_mhz(s3c2410_pclk));
+ print_mhz(s3c24xx_fclk), print_mhz(s3c24xx_hclk),
+ print_mhz(s3c24xx_pclk));
}
static struct s3c2410_board *board;
board = b;
}
-void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no)
-{
- s3c2410_uartcfgs = cfg;
-}
-
int __init s3c2410_init(void)
{
int ret;
* 04-Sep-2004 BJD Added s3c2410_init_uarts() call
*/
+struct s3c2410_uartcfg;
+
extern void s3c2410_map_io(struct map_desc *, int count);
+extern void s3c2410_init_uarts(struct s3c2410_uartcfg *, int no);
+
extern void s3c2410_init_irq(void);
extern void s3c2410_init_time(void);
* published by the Free Software Foundation.
*
* Modifications:
- * 24-Aug-2004 BJD Start of s3c2440 support
+ * 24-Aug-2004 BJD Start of s3c2440 support
+ * 12-Oct-2004 BJD Moved clock info out to clock.c
*/
#include <linux/kernel.h>
#include <asm/arch/regs-serial.h>
#include "s3c2440.h"
+#include "clock.h"
#include "cpu.h"
int s3c2440_clock_tick_rate = 12*1000*1000; /* current timers at 12MHz */
/* clock info */
-
-unsigned long s3c2440_baseclk = 12*1000*1000; /* assume base is 12MHz */
unsigned long s3c2440_hdiv;
-unsigned long s3c2440_fclk;
-unsigned long s3c2440_hclk;
-unsigned long s3c2440_pclk;
-
static struct map_desc s3c2440_iodesc[] __initdata = {
IODESC_ENT(USBHOST),
IODESC_ENT(CLKPWR),
void __init s3c2440_map_io(struct map_desc *mach_desc, int size)
{
- unsigned long tmp;
+ unsigned long clkdiv;
unsigned long camdiv;
/* register our io-tables */
/* now we've got our machine bits initialised, work out what
* clocks we've got */
- s3c2440_fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON),
- s3c2440_baseclk);
+ s3c24xx_fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON),
+ s3c24xx_xtal) * 2;
- tmp = __raw_readl(S3C2410_CLKDIVN);
+ clkdiv = __raw_readl(S3C2410_CLKDIVN);
camdiv = __raw_readl(S3C2440_CAMDIVN);
/* work out clock scalings */
- switch (tmp & S3C2440_CLKDIVN_HDIVN_MASK) {
+ switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
case S3C2440_CLKDIVN_HDIVN_1:
s3c2440_hdiv = 1;
break;
break;
case S3C2440_CLKDIVN_HDIVN_3_6:
- s3c2440_hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 6 : 3;
+ s3c2440_hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
break;
}
- s3c2440_hclk = s3c2440_fclk / s3c2440_hdiv;
- s3c2440_pclk = s3c2440_hclk / ((tmp & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);
+ s3c24xx_hclk = s3c24xx_fclk / s3c2440_hdiv;
+ s3c24xx_pclk = s3c24xx_hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1);
/* print brieft summary of clocks, etc */
printk("S3C2440: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
- print_mhz(s3c2440_fclk), print_mhz(s3c2440_hclk),
- print_mhz(s3c2440_pclk));
+ print_mhz(s3c24xx_fclk), print_mhz(s3c24xx_hclk),
+ print_mhz(s3c24xx_pclk));
}
#include <asm/arch/regs-irq.h>
#include <asm/mach/time.h>
+#include "clock.h"
+
static unsigned long timer_startval;
static unsigned long timer_ticks_usec;
-
/* with an 12MHz clock, we get 12 ticks per-usec
*/
*/
if (machine_is_h1940() || machine_is_smdk2410() ) {
- timer_ticks_usec = s3c2410_pclk / (1000*1000);
+ timer_ticks_usec = s3c24xx_pclk / (1000*1000);
timer_ticks_usec /= 6;
tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
tcfg0 |= ((6 - 1) / 2) << S3C2410_TCFG_PRESCALER1_SHIFT;
- tcnt = (s3c2410_pclk / 6) / HZ;
+ tcnt = (s3c24xx_pclk / 6) / HZ;
}
* 12-Mar-2004 BJD Fixed include protection, fixed type of clock vars
* 14-Sep-2004 BJD Added misccr and getpin to gpio
* 01-Oct-2004 BJD Added the new gpio functions
+ * 16-Oct-2004 BJD Removed the clock variables
*/
#ifndef __ASM_ARCH_HARDWARE_H
#ifndef __ASSEMBLY__
-/* processor clock settings, in Hz */
-extern unsigned long s3c2410_pclk;
-extern unsigned long s3c2410_hclk;
-extern unsigned long s3c2410_fclk;
-
/* external functions for GPIO support
*
* These allow various different clients to access the same GPIO
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