#include <asm/irq.h>
#include <asm/mpspec.h>
-#ifdef CONFIG_X86_LOCAL_APIC
+#ifdef CONFIG_X86_64
+
+static inline void acpi_madt_oem_check(char *oem_id, char *oem_table_id) { }
+static inline void clustered_apic_check(void) { }
+static inline int ioapic_setup_disabled(void) { return 0; }
+#include <asm/proto.h>
+
+#else /* X86 */
+
+#ifdef CONFIG_X86_LOCAL_APIC
#include <mach_apic.h>
#include <mach_mpparse.h>
-#include <asm/io_apic.h>
-#endif
+#endif /* CONFIG_X86_LOCAL_APIC */
+
+#endif /* X86 */
#define PREFIX "ACPI: "
*/
enum acpi_irq_model_id acpi_irq_model = ACPI_IRQ_MODEL_PIC;
+#ifdef CONFIG_X86_64
+
+/* rely on all ACPI tables being in the direct mapping */
+char *__acpi_map_table(unsigned long phys_addr, unsigned long size)
+{
+ if (!phys_addr || !size)
+ return NULL;
+
+ if (phys_addr < (end_pfn_map << PAGE_SHIFT))
+ return __va(phys_addr);
+
+ return NULL;
+}
+
+#else
+
/*
* Temporarily use the virtual area starting from FIX_IO_APIC_BASE_END,
* to map the target physical address. The problem is that set_fixmap()
return ((unsigned char *) base + offset);
}
-
+#endif
#ifdef CONFIG_PCI_MMCONFIG
static int __init acpi_parse_mcfg(unsigned long phys_addr, unsigned long size)
#ifdef CONFIG_HPET_TIMER
-extern unsigned long hpet_address;
static int __init acpi_parse_hpet(unsigned long phys, unsigned long size)
{
return -1;
}
- hpet_address = hpet_tbl->addr.addrl;
- printk(KERN_INFO PREFIX "HPET id: %#x base: %#lx\n", hpet_tbl->id,
- hpet_address);
+#ifdef CONFIG_X86_64
+ vxtime.hpet_address = hpet_tbl->addr.addrl |
+ ((long) hpet_tbl->addr.addrh << 32);
+
+ printk(KERN_INFO PREFIX "HPET id: %#x base: %#lx\n",
+ hpet_tbl->id, vxtime.hpet_address);
+#else /* X86 */
+ {
+ extern unsigned long hpet_address;
+
+ hpet_address = hpet_tbl->addr.addrl;
+ printk(KERN_INFO PREFIX "HPET id: %#x base: %#lx\n",
+ hpet_tbl->id, hpet_address);
+ }
+#endif /* X86 */
+
return 0;
}
#else
#define acpi_parse_hpet NULL
#endif
+#ifdef CONFIG_X86_PM_TIMER
extern u32 pmtmr_ioport;
+#endif
static int __init acpi_parse_fadt(unsigned long phys, unsigned long size)
{
/*
* if "noapic" boot option, don't look for IO-APICs
*/
- if (ioapic_setup_disabled()) {
+ if (skip_ioapic_setup) {
printk(KERN_INFO PREFIX "Skipping IOAPIC probe "
"due to 'noapic' option.\n");
return -ENODEV;
obj-y += mce.o
obj-$(CONFIG_MTRR) += ../../i386/kernel/cpu/mtrr/
-obj-$(CONFIG_ACPI) += acpi/
+obj-$(CONFIG_ACPI_BOOT) += acpi/
obj-$(CONFIG_X86_MSR) += msr.o
obj-$(CONFIG_MICROCODE) += microcode.o
obj-$(CONFIG_X86_CPUID) += cpuid.o
obj-$(CONFIG_ACPI_BOOT) := boot.o
+boot-$(CONFIG_ACPI_BOOT) := ../../../i386/kernel/acpi/boot.o
obj-$(CONFIG_ACPI_SLEEP) += sleep.o wakeup.o
-
extern FADT_DESCRIPTOR acpi_fadt;
-void __init mp_config_ioapic_for_sci(int irq)
-{
- int ioapic;
- int ioapic_pin;
- struct acpi_table_madt *madt;
- struct acpi_table_int_src_ovr *entry = NULL;
- acpi_interrupt_flags flags;
- void *madt_end;
- acpi_status status;
-
- /*
- * Ensure that if there is an interrupt source override entry
- * for the ACPI SCI, we leave it as is. Unfortunately this involves
- * walking the MADT again.
- */
- status = acpi_get_firmware_table("APIC", 1, ACPI_LOGICAL_ADDRESSING,
- (struct acpi_table_header **) &madt);
- if (ACPI_SUCCESS(status)) {
- madt_end = (void *) (unsigned long)madt + madt->header.length;
-
- entry = (struct acpi_table_int_src_ovr *)
- ((unsigned long) madt + sizeof(struct acpi_table_madt));
-
- while ((void *) entry < madt_end) {
- if (entry->header.type == ACPI_MADT_INT_SRC_OVR &&
- acpi_fadt.sci_int == entry->bus_irq)
- goto found;
-
- entry = (struct acpi_table_int_src_ovr *)
- ((unsigned long) entry + entry->header.length);
- }
- }
- /*
- * Although the ACPI spec says that the SCI should be level/low
- * don't reprogram it unless there is an explicit MADT OVR entry
- * instructing us to do so -- otherwise we break Tyan boards which
- * have the SCI wired edge/high but no MADT OVR.
- */
- return;
-
-found:
- /*
- * See the note at the end of ACPI 2.0b section
- * 5.2.10.8 for what this is about.
- */
- flags = entry->flags;
- acpi_fadt.sci_int = entry->global_irq;
- irq = entry->global_irq;
-
- ioapic = mp_find_ioapic(irq);
-
- ioapic_pin = irq - mp_ioapic_routing[ioapic].irq_start;
-
- /*
- * MPS INTI flags:
- * trigger: 0=default, 1=edge, 3=level
- * polarity: 0=default, 1=high, 3=low
- * Per ACPI spec, default for SCI means level/low.
- */
- io_apic_set_pci_routing(ioapic, ioapic_pin, irq,
- (flags.trigger == 1 ? 0 : 1), (flags.polarity == 1 ? 0 : 1));
-}
-
#ifdef CONFIG_ACPI_PCI
void __init mp_parse_prt (void)
#ifdef CONFIG_ACPI_BOOT
extern int __initdata acpi_ht;
+extern acpi_interrupt_flags acpi_sci_flags;
/* int __initdata acpi_force = 0; */
#endif
if (!memcmp(from, "acpi=ht", 7)) {
acpi_ht = 1;
}
+ else if (!memcmp(from, "pci=noacpi", 10))
+ acpi_noirq_set();
+
+ else if (!memcmp(from, "acpi_sci=edge", 13))
+ acpi_sci_flags.trigger = 1;
+ else if (!memcmp(from, "acpi_sci=level", 14))
+ acpi_sci_flags.trigger = 3;
+ else if (!memcmp(from, "acpi_sci=high", 13))
+ acpi_sci_flags.polarity = 1;
+ else if (!memcmp(from, "acpi_sci=low", 12))
+ acpi_sci_flags.polarity = 3;
#endif
if (!memcmp(from, "nolapic", 7) ||
bool "Power Management Timer Support"
depends on X86 && ACPI
depends on ACPI_BOOT && EXPERIMENTAL
+ depends on !X86_64
default n
help
The Power Management Timer is available on all ACPI-capable,
#define _COMPONENT ACPI_BUS_COMPONENT
ACPI_MODULE_NAME ("acpi_bus")
-#ifdef CONFIG_X86_64
-extern void __init acpi_pic_sci_set_trigger(unsigned int irq);
-#elif defined(CONFIG_X86)
+#ifdef CONFIG_X86
extern void __init acpi_pic_sci_set_trigger(unsigned int irq, u16 trigger);
#endif
printk(KERN_ERR PREFIX "Unable to get the FADT\n");
goto error1;
}
-#ifdef CONFIG_X86_64
- /* Ensure the SCI is set to level-triggered, active-low */
- if (acpi_ioapic)
- mp_config_ioapic_for_sci(acpi_fadt.sci_int);
- else
- acpi_pic_sci_set_trigger(acpi_fadt.sci_int);
-#elif defined(CONFIG_X86)
+
+#ifdef CONFIG_X86
if (!acpi_ioapic) {
extern acpi_interrupt_flags acpi_sci_flags;
/* Set PIC-mode SCI trigger type */
#endif /*CONFIG_X86_IO_APIC*/
#endif
-extern void mp_config_ioapic_for_sci(int irq);
-
extern int using_apic_timer;
#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS)
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