arch/arm/vmlinux.lds
MRPROPER_FILES += \
+ arch/arm/tools/constants.h* \
include/asm-arm/arch \
include/asm-arm/proc \
include/asm-arm/constants.h* \
.endm
#elif defined(CONFIG_ARCH_SA1100)
+
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #0x80000000 @ physical base address
movne \rx, #0xf8000000 @ virtual address
- @add \rx, \rx, #0x00050000 @ Ser3
- add \rx, \rx, #0x00010000 @ Ser1
+
+ @ We probe for the active serial port here, coherently with
+ @ the comment in include/asm-arm/arch-sa1100/uncompress.h.
+ @ We assume r1 can be clobbered.
+
+ @ see if Ser3 is active
+ add \rx, \rx, #0x00050000
+ ldr r1, [\rx, #UTCR3]
+ tst r1, #UTCR3_TXE
+
+ @ if Ser3 is inactive, then try Ser1
+ addeq \rx, \rx, #(0x00010000 - 0x00050000)
+ ldreq r1, [\rx, #UTCR3]
+ tsteq r1, #UTCR3_TXE
+
+ @ if Ser1 is inactive, then try Ser2
+ addeq \rx, \rx, #(0x00030000 - 0x00010000)
+ ldreq r1, [\rx, #UTCR3]
+ tsteq r1, #UTCR3_TXE
+
+ @ if all ports are inactive, then there is nothing we can do
+ moveq pc, lr
.endm
.macro senduart,rd,rx
- str \rd, [\rx, #0x14] @ UTDR
+ str \rd, [\rx, #UTDR]
.endm
.macro waituart,rd,rx
-1001: ldr \rd, [\rx, #0x20] @ UTSR1
- tst \rd, #1 << 2 @ UTSR1_TNF
+1001: ldr \rd, [\rx, #UTSR1]
+ tst \rd, #UTSR1_TNF
beq 1001b
.endm
.macro busyuart,rd,rx
-1001: ldr \rd, [\rx, #0x20] @ UTSR1
- tst \rd, #1 << 0 @ UTSR1_TBY
+1001: ldr \rd, [\rx, #UTSR1]
+ tst \rd, #UTSR1_TBY
bne 1001b
.endm
/*
* Breakpoint SWI instruction: SWI &9F0001
*/
-#define BREAKINST 0xef9f0001
+#define BREAKINST_ARM 0xef9f0001
/*
* Get the address of the live pt_regs for the specified task.
return val;
}
+#define OP_MASK 0x01e00000
+#define OP_AND 0x00000000
+#define OP_EOR 0x00200000
+#define OP_SUB 0x00400000
+#define OP_RSB 0x00600000
+#define OP_ADD 0x00800000
+#define OP_ADC 0x00a00000
+#define OP_SBC 0x00c00000
+#define OP_RSC 0x00e00000
+#define OP_ORR 0x01800000
+#define OP_MOV 0x01a00000
+#define OP_BIC 0x01c00000
+#define OP_MVN 0x01e00000
+
static unsigned long
get_branch_address(struct task_struct *child, unsigned long pc, unsigned long insn)
{
aluop1 = ptrace_getrn(child, insn);
aluop2 = ptrace_getaluop2(child, insn);
- ccbit = get_stack_long(child, REG_PSR) & CC_C_BIT ? 1 : 0;
-
- switch (insn & 0x01e00000) {
- case 0x00000000: alt = aluop1 & aluop2; break;
- case 0x00200000: alt = aluop1 ^ aluop2; break;
- case 0x00400000: alt = aluop1 - aluop2; break;
- case 0x00600000: alt = aluop2 - aluop1; break;
- case 0x00800000: alt = aluop1 + aluop2; break;
- case 0x00a00000: alt = aluop1 + aluop2 + ccbit; break;
- case 0x00c00000: alt = aluop1 - aluop2 + ccbit; break;
- case 0x00e00000: alt = aluop2 - aluop1 + ccbit; break;
- case 0x01800000: alt = aluop1 | aluop2; break;
- case 0x01a00000: alt = aluop2; break;
- case 0x01c00000: alt = aluop1 & ~aluop2; break;
- case 0x01e00000: alt = ~aluop2; break;
+ ccbit = get_stack_long(child, REG_PSR) & PSR_C_BIT ? 1 : 0;
+
+ switch (insn & OP_MASK) {
+ case OP_AND: alt = aluop1 & aluop2; break;
+ case OP_EOR: alt = aluop1 ^ aluop2; break;
+ case OP_SUB: alt = aluop1 - aluop2; break;
+ case OP_RSB: alt = aluop2 - aluop1; break;
+ case OP_ADD: alt = aluop1 + aluop2; break;
+ case OP_ADC: alt = aluop1 + aluop2 + ccbit; break;
+ case OP_SBC: alt = aluop1 - aluop2 + ccbit; break;
+ case OP_RSC: alt = aluop2 - aluop1 + ccbit; break;
+ case OP_ORR: alt = aluop1 | aluop2; break;
+ case OP_MOV: alt = aluop2; break;
+ case OP_BIC: alt = aluop1 & ~aluop2; break;
+ case OP_MVN: alt = ~aluop2; break;
}
break;
}
base = ptrace_getrn(child, insn);
if (read_tsk_long(child, base + nr_regs, &alt) == 0)
- alt = pc_pointer (alt);
+ alt = pc_pointer(alt);
break;
}
break;
if (nr < 2) {
res = read_tsk_long(child, addr, &dbg->bp[nr].insn);
if (res == 0)
- res = write_tsk_long(child, addr, BREAKINST);
+ res = write_tsk_long(child, addr, BREAKINST_ARM);
if (res == 0) {
dbg->bp[nr].address = addr;
read_tsk_long(child, dbg->bp[i].address, &tmp);
write_tsk_long(child, dbg->bp[i].address, dbg->bp[i].insn);
- if (tmp != BREAKINST)
+ if (tmp != BREAKINST_ARM)
printk(KERN_ERR "ptrace_cancel_bpt: weirdness\n");
}
}
static inline void dump_cache(const char *prefix, unsigned int cache)
{
- unsigned int mult = 2 + CACHE_M(cache) ? 1 : 0;
+ unsigned int mult = 2 + (CACHE_M(cache) ? 1 : 0);
printk("%s size %dK associativity %d line length %d sets %d\n",
prefix,
static void
c_show_cache(struct seq_file *m, const char *type, unsigned int cache)
{
- unsigned int mult = 2 + CACHE_M(cache) ? 1 : 0;
+ unsigned int mult = 2 + (CACHE_M(cache) ? 1 : 0);
seq_printf(m, "%s size\t\t: %d\n"
"%s assoc\t\t: %d\n"
cache_types[CACHE_TYPE(cache_info)],
cache_clean[CACHE_TYPE(cache_info)],
cache_lockdown[CACHE_TYPE(cache_info)],
- CACHE_S(cache_info) ? "separate I,D" : "unified");
+ CACHE_S(cache_info) ? "Harvard" : "Unified");
if (CACHE_S(cache_info)) {
c_show_cache(m, "I", CACHE_ISIZE(cache_info));
if (__put_user(retcodes[idx], rc))
return 1;
- flush_icache_range((unsigned long)rc,
- (unsigned long)(rc + 1));
+ /*
+ * Ensure that the instruction cache sees
+ * the return code written onto the stack.
+ */
+ cpu_icache_invalidate_range((unsigned long)rc,
+ (unsigned long)(rc + 1));
retcode = ((unsigned long)rc) + thumb;
}
int i;
printk("Code: ");
- for (i = -2; i < 3; i++) {
+ for (i = -4; i < 1; i++) {
unsigned int val, bad;
if (thumb)
#include <asm/assembler.h>
#include <asm/hardware.h>
-#if defined(CONFIG_CPU_26)
+#ifdef CONFIG_CPU_26
#define CPSR2SPSR(rt)
#else
#define CPSR2SPSR(rt) \
@ Proto : void memc_write(int register, int value);
@ Returns: nothing
-#if defined(CONFIG_CPU_26)
+#ifdef CONFIG_CPU_26
ENTRY(memc_write)
cmp r0, #7
RETINSTR(movgt,pc,lr)
static void arc_floppy_data_enable_dma(dmach_t channel, dma_t *dma)
{
DPRINTK("arc_floppy_data_enable_dma\n");
+
+ if (dma->using_sg)
+ BUG();
+
switch (dma->dma_mode) {
case DMA_MODE_READ: { /* read */
extern unsigned char fdc1772_dma_read, fdc1772_dma_read_end;
memcpy ((void *)0x1c, (void *)&fdc1772_dma_read,
&fdc1772_dma_read_end - &fdc1772_dma_read);
- fdc1772_setupdma(dma->buf.length, dma->buf.address); /* Sets data pointer up */
+ fdc1772_setupdma(dma->buf.length, dma->buf.__address); /* Sets data pointer up */
enable_fiq(FIQ_FLOPPYDATA);
restore_flags(flags);
}
clf();
memcpy ((void *)0x1c, (void *)&fdc1772_dma_write,
&fdc1772_dma_write_end - &fdc1772_dma_write);
- fdc1772_setupdma(dma->buf.length, dma->buf.address); /* Sets data pointer up */
+ fdc1772_setupdma(dma->buf.length, dma->buf.__address); /* Sets data pointer up */
enable_fiq(FIQ_FLOPPYDATA;
restore_flags(flags);
extern void floppy_fiqsetup(unsigned long len, unsigned long addr,
unsigned long port);
+ if (dma->using_sg)
+ BUG();
+
if (dma->dma_mode == DMA_MODE_READ) {
extern unsigned char floppy_fiqin_start, floppy_fiqin_end;
fiqhandler_start = &floppy_fiqin_start;
}
memcpy((void *)0x1c, fiqhandler_start, fiqhandler_length);
regs.ARM_r9 = dma->buf.length;
- regs.ARM_r10 = (unsigned long)dma->buf.address;
+ regs.ARM_r10 = (unsigned long)dma->buf.__address;
regs.ARM_fp = FLOPPYDMA_BASE;
set_fiq_regs(®s);
enable_fiq(dma->dma_irq);
*/
spin_lock_irqsave(&gpio_lock, flags);
gpio_modify_op(-1, GPIO_RED_LED | GPIO_FAN);
- spin_unlock_irqrestore(&gpio_loc, flags);
+ spin_unlock_irqrestore(&gpio_lock, flags);
}
/*
return irq_tab[intnr];
}
-extern void pci_v3_setup_resources(struct resource **res);
extern void pci_v3_init(void *);
struct hw_pci integrator_pci __initdata = {
swizzle: integrator_swizzle,
map_irq: integrator_map_irq,
setup: pci_v3_setup,
+ nr_controllers: 1,
scan: pci_v3_scan_bus,
preinit: pci_v3_preinit,
postinit: pci_v3_postinit,
#include <asm/hardware/pci_v3.h>
-int setup_arm_irq(int irq, struct irqaction * new);
-
/*
* The V3 PCI interface chip in Integrator provides several windows from
* local bus memory into the PCI memory areas. Unfortunately, there
flags: IORESOURCE_MEM | IORESOURCE_PREFETCH,
};
-static void __init pci_v3_setup_resources(struct resource **resource)
+static int __init pci_v3_setup_resources(struct resource **resource)
{
- if (request_resource(&iomem_resource, &non_mem))
- printk("PCI: unable to allocate non-prefetchable memory region\n");
- if (request_resource(&iomem_resource, &pre_mem))
- printk("PCI: unable to allocate prefetchable memory region\n");
+ if (request_resource(&iomem_resource, &non_mem)) {
+ printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
+ "memory region\n");
+ return -EBUSY;
+ }
+ if (request_resource(&iomem_resource, &pre_mem)) {
+ release_resource(&non_mem);
+ printk(KERN_ERR "PCI: unable to allocate prefetchable "
+ "memory region\n");
+ return -EBUSY;
+ }
/*
* bus->resource[0] is the IO resource for this bus
resource[0] = &ioport_resource;
resource[1] = &non_mem;
resource[2] = &pre_mem;
+
+ return 0;
}
/*
{
unsigned long pc = instruction_pointer(regs);
unsigned long instr = *(unsigned long *)pc;
-// char buf[128];
+#if 0
+ char buf[128];
-// sprintf(buf, "V3 fault: address=0x%08lx, pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n",
-// addr, pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255,
-// v3_readb(V3_LB_ISTAT));
-// printk("%s", buf);
-// printascii(buf);
+ sprintf(buf, "V3 fault: address=0x%08lx, pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n",
+ addr, pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255,
+ v3_readb(V3_LB_ISTAT));
+ printk(KERN_DEBUG "%s", buf);
+ printascii(buf);
+#endif
v3_writeb(V3_LB_ISTAT, 0);
__raw_writel(3, SC_PCI);
#endif
}
-static struct irqaction v3_int = {
- name: "V3",
- handler: v3_irq,
-};
-
-static struct irqaction v3_int2 = {
- name: "V3TM",
- handler: v3_irq,
-};
-
extern int (*external_fault)(unsigned long addr, struct pt_regs *regs);
-int pci_v3_setup(int nr, struct pci_sys_data *sys)
+int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
{
- if (nr)
- pci_v3_setup_resources(sys->resource);
- return nr ? 0 : 1;
+ int ret = 0;
+
+ if (nr == 0)
+ ret = pci_v3_setup_resources(sys->resource);
+
+ return ret;
}
struct pci_bus *pci_v3_scan_bus(int nr, struct pci_sys_data *sys)
{
- return pci_scan_bus(sys->busnr, &pci_v3_ops, sys);
+ return pci_scan_bus(sys->busnr, &pci_v3_ops, sys);
}
/*
{
unsigned long flags;
unsigned int temp;
+ int ret;
/*
* Hook in our fault handler for PCI errors
temp |= V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS;
v3_writew(V3_PCI_CFG, temp);
- printk("FIFO_CFG: %04x FIFO_PRIO: %04x\n",
+ printk(KERN_DEBUG "FIFO_CFG: %04x FIFO_PRIO: %04x\n",
v3_readw(V3_FIFO_CFG), v3_readw(V3_FIFO_PRIORITY));
/*
/*
* Grab the PCI error interrupt.
*/
- setup_arm_irq(IRQ_V3INT, &v3_int);
+ ret = request_irq(IRQ_V3INT, v3_irq, 0, "V3", NULL);
+ if (ret)
+ printk(KERN_ERR "PCI: unable to grab PCI error "
+ "interrupt: %d\n", ret);
spin_unlock_irqrestore(&v3_lock, flags);
}
void __init pci_v3_postinit(void)
{
unsigned int pci_cmd;
+ int ret;
pci_cmd = PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
v3_writeb(V3_LB_ISTAT, ~0x40);
v3_writeb(V3_LB_IMASK, 0x68);
-// setup_arm_irq(IRQ_LBUSTIMEOUT, &v3_int2);
+#if 0
+ ret = request_irq(IRQ_LBUSTIMEOUT, lb_timeout, 0, "bus timeout", NULL);
+ if (ret)
+ printk(KERN_ERR "PCI: unable to grab local bus timeout "
+ "interrupt: %d\n", ret);
+#endif
}
#ifdef DEBUG
#define DBG(x...) printk(x)
#else
-#define DBG(x...)
+#define DBG(x...) do { } while (0)
#endif
extern int (*external_fault)(unsigned long, struct pt_regs *);
*IOP310_SATUISR = uisr & 0x0000069f;
ret = 1;
}
-//if (ret) printk("ERROR (%08lx %08lx)", usr, uisr);
+ if (ret)
+ DBG("ERROR (%08lx %08lx)", usr, uisr);
return ret;
}
{
int ret;
u8 val;
-//printk("rdb: %d:%02x.%x %02x ", dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where);
+
+ DBG("rdb: %d:%02x.%x %02x ", dev->bus->number, PCI_SLOT(dev->devfn),
+ PCI_FUNC(dev->devfn), where);
*IOP310_SOCCAR = iop310_cfg_address(dev, where);
val = (*IOP310_SOCCDR) >> ((where & 3) * 8);
__asm__ __volatile__("nop; nop; nop; nop");
-//printk(">= %08lx ", val);
+
+ DBG(">= %08lx ", val);
ret = iop310_sec_pci_status();
if (ret)
val = 0xff;
-//printk("\n");
+ DBG("\n");
*p = val;
return PCIBIOS_SUCCESSFUL;
{
int ret;
u16 val;
-//printk("rdw: %d:%02x.%x %02x ", dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where);
+
+ DBG("rdw: %d:%02x.%x %02x ", dev->bus->number, PCI_SLOT(dev->devfn),
+ PCI_FUNC(dev->devfn), where);
*IOP310_SOCCAR = iop310_cfg_address(dev, where);
val = (*IOP310_SOCCDR) >> ((where & 3) * 8);
__asm__ __volatile__("nop; nop; nop; nop");
-//printk(">= %08lx ", val);
+
+ DBG(">= %08lx ", val);
ret = iop310_sec_pci_status();
if (ret)
val = 0xffff;
-//printk("\n");
+ DBG("\n");
*p = val;
return PCIBIOS_SUCCESSFUL;
{
int ret;
u32 val;
-//printk("rdl: %d:%02x.%x %02x ", dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where);
+
+ DBG("rdl: %d:%02x.%x %02x ", dev->bus->number, PCI_SLOT(dev->devfn),
+ PCI_FUNC(dev->devfn), where);
*IOP310_SOCCAR = iop310_cfg_address(dev, where);
val = *IOP310_SOCCDR;
__asm__ __volatile__("nop; nop; nop; nop");
-//printk(">= %08lx ", val);
+
+ DBG(">= %08lx ", val);
ret = iop310_sec_pci_status();
if (ret)
val = 0xffffffff;
-//printk("\n");
+ DBG("\n");
*p = val;
return PCIBIOS_SUCCESSFUL;
{
int ret;
u32 val;
-//printk("wrb: %d:%02x.%x %02x ", dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where);
+
+ DBG("wrb: %d:%02x.%x %02x ", dev->bus->number, PCI_SLOT(dev->devfn),
+ PCI_FUNC(dev->devfn), where);
*IOP310_SOCCAR = iop310_cfg_address(dev, where);
val = *IOP310_SOCCDR;
__asm__ __volatile__("nop; nop; nop; nop");
-//printk("<= %08lx", v);
+
+ DBG("<= %08lx", v);
ret = iop310_sec_pci_status();
if (ret == 0) {
where = (where & 3) * 8;
val |= v << where;
*IOP310_SOCCDR = val;
}
-//printk("\n");
+ DBG("\n");
return PCIBIOS_SUCCESSFUL;
}
{
int ret;
u32 val;
-//printk("wrw: %d:%02x.%x %02x ", dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where);
+
+ DBG("wrw: %d:%02x.%x %02x ", dev->bus->number, PCI_SLOT(dev->devfn),
+ PCI_FUNC(dev->devfn), where);
*IOP310_SOCCAR = iop310_cfg_address(dev, where);
val = *IOP310_SOCCDR;
__asm__ __volatile__("nop; nop; nop; nop");
-//printk("<= %08lx", v);
+
+ DBG("<= %08lx", v);
ret = iop310_sec_pci_status();
if (ret == 0) {
where = (where & 2) * 8;
val |= v << where;
*IOP310_SOCCDR = val;
}
-//printk("\n");
+ DBG("\n");
return PCIBIOS_SUCCESSFUL;
}
static int
iop310_sec_wr_cfg_dword(struct pci_dev *dev, int where, u32 v)
{
-//printk("wrl: %d:%02x.%x %02x ", dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where);
+ DBG("wrl: %d:%02x.%x %02x ", dev->bus->number, PCI_SLOT(dev->devfn),
+ PCI_FUNC(dev->devfn), where);
*IOP310_SOCCAR = iop310_cfg_address(dev, where);
*IOP310_SOCCDR = v;
__asm__ __volatile__("nop; nop; nop; nop");
-//printk("<= %08lx\n", v);
+
+ DBG("<= %08lx\n", v);
return PCIBIOS_SUCCESSFUL;
}
*/
int iop310_pci_abort_handler(unsigned long addr, struct pt_regs *regs)
{
-// printk("PCI abort: address = %08x PC = %08x LR = %08lx\n",
-// addr, regs->ARM_pc, regs->ARM_lr);
+ DBG("PCI abort: address = %08x PC = %08x LR = %08lx\n",
+ addr, regs->ARM_pc, regs->ARM_lr);
return 0;
}
case 1:
res[0].start = IOP310_PCISEC_LOWER_IO + 0x6e000000;
res[0].end = IOP310_PCISEC_LOWER_IO + 0x6e00ffff;
- res[0].name = "PCI IO Primary";
+ res[0].name = "PCI IO Secondary";
res[1].start = IOP310_PCISEC_LOWER_MEM;
res[1].end = IOP310_PCISEC_LOWER_MEM + IOP310_PCI_WINDOW_SIZE;
- res[1].name = "PCI Memory Primary";
+ res[1].name = "PCI Memory Secondary";
break;
}
void iop310_init(void)
{
DBG("PCI: Intel 80312 PCI-to-PCI init code.\n");
- DBG(" ATU secondary: IOP310_SOMWVR=0x%04x, IOP310_SOIOWVR=0x%04x\n",
- *IOP310_SOMWVR,
- *IOP310_SOIOWVR);
- DBG(" ATU secondary: IOP310_ATUCR=0x%08x\n", *IOP310_ATUCR);
- DBG(" ATU secondary: IOP310_SIABAR=0x%08x IOP310_SIALR=0x%08x IOP310_SIATVR=%08x\n", *IOP310_SIABAR, *IOP310_SIALR, *IOP310_SIATVR);
-
- DBG(" ATU primary: IOP310_POMWVR=0x%04x, IOP310_POIOWVR=0x%04x\n",
- *IOP310_POMWVR,
- *IOP310_POIOWVR);
- DBG(" ATU secondary: IOP310_PIABAR=0x%08x IOP310_PIALR=0x%08x IOP310_PIATVR=%08x\n", *IOP310_PIABAR, *IOP310_PIALR, *IOP310_PIATVR);
-
- DBG(" P2P: IOP310_PCR=0x%04x IOP310_BCR=0x%04x IOP310_EBCR=0x%04x\n", *IOP310_PCR, *IOP310_BCR, *IOP310_EBCR);
+ DBG(" ATU secondary: ATUCR =0x%08x\n", *IOP310_ATUCR);
+ DBG(" ATU secondary: SOMWVR=0x%08x SOIOWVR=0x%08x\n",
+ *IOP310_SOMWVR, *IOP310_SOIOWVR);
+ DBG(" ATU secondary: SIABAR=0x%08x SIALR =0x%08x SIATVR=%08x\n",
+ *IOP310_SIABAR, *IOP310_SIALR, *IOP310_SIATVR);
+ DBG(" ATU primary: POMWVR=0x%08x POIOWVR=0x%08x\n",
+ *IOP310_POMWVR, *IOP310_POIOWVR);
+ DBG(" ATU primary: PIABAR=0x%08x PIALR =0x%08x PIATVR=%08x\n",
+ *IOP310_PIABAR, *IOP310_PIALR, *IOP310_PIATVR);
+ DBG(" P2P: PCR=0x%04x BCR=0x%04x EBCR=0x%04x\n",
+ *IOP310_PCR, *IOP310_BCR, *IOP310_EBCR);
/*
* Windows have to be carefully opened via a nice set of calls
*IOP310_PCR &= 0xfff8;
external_fault = iop310_pci_abort_handler;
-
}
*/
if (!dma->using_sg) {
dma->buf.dma_address = pci_map_single(NULL,
- dma->buf.address, dma->buf.length,
+ dma->buf.__address, dma->buf.length,
dma->dma_mode == DMA_MODE_READ ?
PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE);
}
unsigned int fiqhandler_length;
struct pt_regs regs;
+ if (dma->using_sg)
+ BUG();
+
if (dma->dma_mode == DMA_MODE_READ) {
extern unsigned char floppy_fiqin_start, floppy_fiqin_end;
fiqhandler_start = &floppy_fiqin_start;
}
regs.ARM_r9 = dma->buf.length;
- regs.ARM_r10 = (unsigned long)dma->buf.address;
+ regs.ARM_r10 = (unsigned long)dma->buf.__address;
regs.ARM_fp = FLOPPYDMA_BASE;
if (claim_fiq(&fh)) {
| GPIO_H3100_IR_ON \
| GPIO_H3100_IR_FSEL)
-void h3100_init_egpio( void )
+static void h3100_init_egpio( void )
{
GPDR |= H3100_DIRECT_EGPIO;
GPCR = H3100_DIRECT_EGPIO; /* Initially all off */
H3600_EGPIO = h3600_egpio;
}
-void h3100_control_egpio( enum ipaq_egpio_type x, int setp )
+static void h3100_control_egpio( enum ipaq_egpio_type x, int setp )
{
unsigned int egpio = 0;
long gpio = 0;
*/
}
-unsigned long h3100_read_egpio( void )
+static unsigned long h3100_read_egpio( void )
{
return h3600_egpio;
}
/************************* H3600 *************************/
-void h3600_init_egpio( void )
+static void h3600_init_egpio( void )
{
h3600_egpio = EGPIO_H3600_RS232_ON;
H3600_EGPIO = h3600_egpio;
}
-void h3600_control_egpio( enum ipaq_egpio_type x, int setp )
+static void h3600_control_egpio( enum ipaq_egpio_type x, int setp )
{
unsigned int egpio = 0;
unsigned long flags;
local_irq_restore(flags);
}
-unsigned long h3600_read_egpio( void )
+static unsigned long h3600_read_egpio( void )
{
return h3600_egpio;
}
static unsigned int h3800_asic1_gpio;
static unsigned int h3800_asic2_gpio;
-void h3800_init_egpio(void)
+static void h3800_init_egpio(void)
{
/* Set up ASIC #1 */
H3800_ASIC1_GPIO_Direction = ASIC1_OUTPUTS; /* All outputs */
H3800_ASIC1_FlashWP_VPP_ON = 0;
}
-void h3800_control_egpio( enum ipaq_egpio_type x, int setp )
+static void h3800_control_egpio( enum ipaq_egpio_type x, int setp )
{
unsigned int set_asic1_egpio = 0;
unsigned int clear_asic1_egpio = 0;
local_irq_restore(flags);
}
-unsigned long h3800_read_egpio( void )
+static unsigned long h3800_read_egpio( void )
{
return h3800_asic1_gpio | (h3800_asic2_gpio << 16);
}
/* initialize extra IRQs */
set_GPIO_IRQ_edge(GPIO_GPIO1, GPIO_RISING_EDGE);
- sa1111_init_irq(IRQ_GPIO1)); /* chained on GPIO 1 */
+ sa1111_init_irq(IRQ_GPIO1); /* chained on GPIO 1 */
return 0;
}
int pm_do_suspend(void)
{
- int retval;
-
/* set up pointer to sleep parameters */
sleep_save = kmalloc(SLEEP_SAVE_SIZE*sizeof(long), GFP_ATOMIC);
if (!sleep_save)
PSPR = 0;
#ifdef DEBUG
- printk("*** made it back from resume\n");
+ printk(KERN_DEBUG "*** made it back from resume\n");
#endif
/* restore registers */
#define ACPI_S1_SLP_TYP 19
/*
- * Send us to sleep. We must not be called from IRQ context.
+ * Send us to sleep.
*/
static int sysctl_pm_do_suspend(void)
{
int retval;
- if (in_interrupt()) {
- printk(KERN_CRIT "pm_do_suspend() called from IRQ\n");
- return -EINVAL;
- }
-
retval = pm_send_all(PM_SUSPEND, (void *)3);
if (retval == 0) {
- retval = __pm_do_suspend();
+ retval = pm_do_suspend();
pm_send_all(PM_RESUME, (void *)0);
}
return retval;
}
-
static struct ctl_table pm_table[] =
{
{ACPI_S1_SLP_TYP, "suspend", NULL, 0, 0600, NULL, (proc_handler *)&sysctl_pm_do_suspend},
if (!inf->fn(addr, fsr, regs))
return;
- printk(KERN_ALERT "Unhandled fault: %s (%X) at 0x%08lx\n",
+ printk(KERN_ALERT "Unhandled fault: %s (0x%03x) at 0x%08lx\n",
inf->name, fsr, addr);
force_sig(inf->sig, current);
show_pte(current->mm, addr);
return;
}
-/*
- * Take care of architecture specific things when placing a new PTE into
- * a page table, or changing an existing PTE. Basically, there are two
- * things that we need to take care of:
- *
- * 1. If PG_dcache_dirty is set for the page, we need to ensure
- * that any cache entries for the kernels virtual memory
- * range are written back to the page.
- * 2. If we have multiple shared mappings of the same space in
- * an object, we need to deal with the cache aliasing issues.
- *
- * Note that the page_table_lock will be held.
- */
-void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
+static void
+make_coherent(struct vm_area_struct *vma, unsigned long addr, struct page *page)
{
- struct page *page = pte_page(pte);
struct vm_area_struct *mpnt;
- struct mm_struct *mm;
- unsigned long pgoff;
- int aliases;
-
- if (!VALID_PAGE(page) || !page->mapping)
- return;
-
- if (test_and_clear_bit(PG_dcache_dirty, &page->flags)) {
- unsigned long kvirt = (unsigned long)page_address(page);
- cpu_cache_clean_invalidate_range(kvirt, kvirt + PAGE_SIZE, 0);
- }
-
- mm = vma->vm_mm;
- pgoff = (addr - vma->vm_start) >> PAGE_SHIFT;
- aliases = 0;
+ struct mm_struct *mm = vma->vm_mm;
+ unsigned long pgoff = (addr - vma->vm_start) >> PAGE_SHIFT;
+ int aliases = 0;
/*
* If we have any shared mappings that are in the same mm
if (aliases)
adjust_pte(vma, addr);
}
+
+/*
+ * Take care of architecture specific things when placing a new PTE into
+ * a page table, or changing an existing PTE. Basically, there are two
+ * things that we need to take care of:
+ *
+ * 1. If PG_dcache_dirty is set for the page, we need to ensure
+ * that any cache entries for the kernels virtual memory
+ * range are written back to the page.
+ * 2. If we have multiple shared mappings of the same space in
+ * an object, we need to deal with the cache aliasing issues.
+ *
+ * Note that the page_table_lock will be held.
+ */
+void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
+{
+ struct page *page = pte_page(pte);
+
+ if (VALID_PAGE(page) && page->mapping) {
+ if (test_and_clear_bit(PG_dcache_dirty, &page->flags)) {
+ unsigned long kvirt = (unsigned long)page_address(page);
+ cpu_cache_clean_invalidate_range(kvirt, kvirt + PAGE_SIZE, 0);
+ }
+
+ make_coherent(vma, addr, page);
+ }
+}
struct siginfo si;
#ifdef CONFIG_DEBUG_USER
- printk(KERN_DEBUG "%s: unhandled page fault at pc=0x%08lx, "
- "lr=0x%08lx (bad address=0x%08lx, code %d)\n",
- tsk->comm, regs->ARM_pc, regs->ARM_lr, addr, error_code);
+ printk(KERN_DEBUG "%s: unhandled page fault at 0x%08lx, code 0x%03x\n",
+ tsk->comm, addr, error_code);
+ show_pte(tsk->mm, addr);
+ show_regs(regs);
#endif
tsk->thread.address = addr;
* If we are out of memory for pid1,
* sleep for a while and retry
*/
- tsk->policy |= SCHED_YIELD;
- schedule();
+ yield();
goto survive;
check_stack:
# To add an entry into this database, please see Documentation/arm/README,
# or contact rmk@arm.linux.org.uk
#
-# Last update: Fri Jan 4 10:27:21 2002
+# Last update: Sun Feb 24 17:43:42 2002
#
# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
#
cdb89712 ARCH_CDB89712 CDB89712 107
graphicsmaster SA1100_GRAPHICSMASTER GRAPHICSMASTER 108
adsbitsy SA1100_ADSBITSY ADSBITSY 109
-cotulla_idp ARCH_COTULLA_IDP COTULLA_IDP 110
+pxa_idp ARCH_PXA_IDP PXA_IDP 110
plce ARCH_PLCE PLCE 111
pt_system3 SA1100_PT_SYSTEM3 PT_SYSTEM3 112
-medalb ARCH_MEDALB MEDALB 113
+murphy ARCH_MEDALB MEDALB 113
eagle ARCH_EAGLE EAGLE 114
dsc21 ARCH_DSC21 DSC21 115
dsc24 ARCH_DSC24 DSC24 116
cep SA1100_CEP CEP 151
fortunet ARCH_FORTUNET FORTUNET 152
vc547x ARCH_VC547X VC547X 153
+filewalker SA1100_FILEWALKER FILEWALKER 154
+netgateway SA1100_NETGATEWAY NETGATEWAY 155
+symbol2800 SA1100_SYMBOL2800 SYMBOL2800 156
+suns SA1100_SUNS SUNS 157
+frodo SA1100_FRODO FRODO 158
+ms301 SA1100_MACH_TYTE_MS301 MACH_TYTE_MS301 159
+mx1ads ARCH_MX1ADS MX1ADS 160
+h7201 ARCH_H7201 H7201 161
+h7202 ARCH_H7202 H7202 162
+amico ARCH_AMICO AMICO 163
+iam SA1100_IAM IAM 164
+tt530 SA1100_TT530 TT530 165
#ifdef CONFIG_SA1100_ASSABET
extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set);
#else
-#define ASSABET_BCR_frob(x) do { } while (0)
+#define ASSABET_BCR_frob(x,y) do { } while (0)
#endif
#define ASSABET_BCR_set(x) ASSABET_BCR_frob((x), (x))
* Generic IO read/write. These perform native-endian accesses. Note
* that some architectures will want to re-define __raw_{read,write}w.
*/
-extern void __raw_writesb(unsigned int addr, void *data, int bytelen);
-extern void __raw_writesw(unsigned int addr, void *data, int wordlen);
-extern void __raw_writesl(unsigned int addr, void *data, int longlen);
+extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
+extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
+extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
#ifndef __ARM_MMU_H
#define __ARM_MMU_H
-/* The ARM doesn't have a mmu context */
+/*
+ * The ARM doesn't have a mmu context
+ */
typedef struct { } mm_context_t;
#endif
#define ASMARM_PCI_H
#ifdef __KERNEL__
-
+#include <linux/config.h>
#include <linux/mm.h> /* bah! */
#include <asm/arch/hardware.h>
for (i = 0; i < nents; i++, sg++) {
char *virt;
- if (sg->address && sg->page)
- BUG();
- else if (!sg->address && !sg->page)
- BUG();
-
- if (sg->address) {
- sg->dma_address = virt_to_bus(sg->address);
- virt = sg->address;
- } else {
- sg->dma_address = page_to_bus(sg->page) + sg->offset;
- virt = page_address(sg->page) + sg->offset;
- }
+
+ sg->dma_address = page_to_bus(sg->page) + sg->offset;
+ virt = page_address(sg->page) + sg->offset;
consistent_sync(virt, sg->length, direction);
}
int i;
for (i = 0; i < nelems; i++, sg++) {
- char *virt;
-
- if (sg->address)
- virt = sg->address;
- else
- virt = page_address(sg->page) + sg->offset;
+ char *virt = page_address(sg->page) + sg->offset;
consistent_sync(virt, sg->length, direction);
}
}
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