[PATCH] sh: ST40 updates

This includes some ST40 updates from the ST tree.  The most notable change is
the ST40GX1 fixes for INTC2-based interrupts.

Signed-off-by: Alex Bennee <kernel-hacker@bennee.com>
Signed-off-by: Paul Mundt <paul.mundt@nokia.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

diff --git a/arch/sh/boards/harp/setup.c b/arch/sh/boards/harp/setup.c
index 0d64b28b0c36759793a37692e18024ea2ae60a1d..05b01b8f40aa39068cf8a9df5865d5d17be793a5 100644 (file)
--- a/arch/sh/boards/harp/setup.c
+++ b/arch/sh/boards/harp/setup.c
@@ -54,3 +54,38 @@ int __init platform_setup(void)
 
        return 0;
 }
+
+/*
+ * pcibios_map_platform_irq
+ *
+ * This is board specific and returns the IRQ for a given PCI device.
+ * It is used by the PCI code (arch/sh/kernel/st40_pci*)
+ *
+ */
+
+#define HARP_PCI_IRQ    1
+#define HARP_BRIDGE_IRQ 2
+#define OVERDRIVE_SLOT0_IRQ 0
+
+
+int __init pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+       switch (slot) {
+#ifdef CONFIG_SH_STB1_HARP
+       case 2:         /*This is the PCI slot on the */
+               return HARP_PCI_IRQ;
+       case 1:         /* this is the bridge */
+               return HARP_BRIDGE_IRQ;
+#elif defined(CONFIG_SH_STB1_OVERDRIVE)
+       case 1:
+       case 2:
+       case 3:
+               return slot - 1;
+#else
+#error Unknown board
+#endif
+       default:
+               return -1;
+       }
+}
+

diff --git a/arch/sh/kernel/cpu/irq_ipr.c b/arch/sh/kernel/cpu/irq_ipr.c
index daae02e6b56d4c435e710629020894396de995b4..7ea3d2d030e5581e847b5d2f9484e5bd41e9a739 100644 (file)
--- a/arch/sh/kernel/cpu/irq_ipr.c
+++ b/arch/sh/kernel/cpu/irq_ipr.c
@@ -19,6 +19,7 @@
 #include <linux/config.h>
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/module.h>
 
 #include <asm/system.h>
 #include <asm/io.h>
@@ -41,7 +42,7 @@ static void mask_and_ack_ipr(unsigned int);
 static void end_ipr_irq(unsigned int irq);
 
 static unsigned int startup_ipr_irq(unsigned int irq)
-{ 
+{
        enable_ipr_irq(irq);
        return 0; /* never anything pending */
 }
@@ -281,6 +282,10 @@ void __init init_IRQ(void)
 #endif /* !CONFIG_CPU_SUBTYPE_SH7300 */
 #endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709  || CONFIG_CPU_SUBTYPE_SH7300*/
 
+#ifdef CONFIG_CPU_SUBTYPE_ST40
+       init_IRQ_intc2();
+#endif
+
        /* Perform the machine specific initialisation */
        if (sh_mv.mv_init_irq != NULL) {
                sh_mv.mv_init_irq();
@@ -329,3 +334,6 @@ int ipr_irq_demux(int irq)
        return irq;
 }
 #endif
+
+EXPORT_SYMBOL(make_ipr_irq);
+

diff --git a/arch/sh/kernel/cpu/sh4/irq_intc2.c b/arch/sh/kernel/cpu/sh4/irq_intc2.c
index ec99f4cc47e4ccc8b6f8315adcb9fcf64cf14744..099ebbf897457a5b606c9f3acae891d0d717a6b8 100644 (file)
--- a/arch/sh/kernel/cpu/sh4/irq_intc2.c
+++ b/arch/sh/kernel/cpu/sh4/irq_intc2.c
@@ -22,8 +22,11 @@
 
 
 struct intc2_data {
-       unsigned int addr;      /* Address of Interrupt Priority Register */
-       int mask; /*Mask to apply */
+       unsigned char msk_offset;
+       unsigned char msk_shift;
+#ifdef CONFIG_CPU_SUBTYPE_ST40
+       int (*clear_irq) (int);
+#endif
 };
 
 
@@ -56,33 +59,34 @@ static struct hw_interrupt_type intc2_irq_type = {
 
 static void disable_intc2_irq(unsigned int irq)
 {
-       unsigned addr;
-       int offset=irq-INTC2_FIRST_IRQ;
-       unsigned val,flags;
+       int irq_offset = irq - INTC2_FIRST_IRQ;
+       int msk_shift, msk_offset;
 
        // Sanity check
-       if(offset<0 || offset>=NR_INTC2_IRQS) return;
-
-       addr=intc2_data[offset].addr+INTC2_INTMSK_OFFSET;
+       if((irq_offset<0) || (irq_offset>=NR_INTC2_IRQS))
+               return;
 
-       local_irq_save(flags);
-       val=ctrl_inl(addr);
-       val|=intc2_data[offset].mask;
-       ctrl_outl(val,addr);
+       msk_shift = intc2_data[irq_offset].msk_shift;
+       msk_offset = intc2_data[irq_offset].msk_offset;
 
-       local_irq_restore(flags);
+       ctrl_outl(1<<msk_shift,
+                 INTC2_BASE+INTC2_INTMSK_OFFSET+msk_offset);
 }
 
 static void enable_intc2_irq(unsigned int irq)
 {
-       int offset=irq-INTC2_FIRST_IRQ;
+       int irq_offset = irq - INTC2_FIRST_IRQ;
+       int msk_shift, msk_offset;
 
-       // Sanity check
-       if(offset<0 || offset>=NR_INTC2_IRQS) return;
+       /* Sanity check */
+       if((irq_offset<0) || (irq_offset>=NR_INTC2_IRQS))
+               return;
 
-       ctrl_outl(intc2_data[offset].mask,
-                 intc2_data[offset].addr+INTC2_INTMSKCLR_OFFSET);
+       msk_shift = intc2_data[irq_offset].msk_shift;
+       msk_offset = intc2_data[irq_offset].msk_offset;
 
+       ctrl_outl(1<<msk_shift,
+                 INTC2_BASE+INTC2_INTMSKCLR_OFFSET+msk_offset);
 }
 
 static void mask_and_ack_intc2(unsigned int irq)
@@ -94,28 +98,52 @@ static void end_intc2_irq(unsigned int irq)
 {
        if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
                enable_intc2_irq(irq);
+
+#ifdef CONFIG_CPU_SUBTYPE_ST40
+       if (intc2_data[irq - INTC2_FIRST_IRQ].clear_irq)
+               intc2_data[irq - INTC2_FIRST_IRQ].clear_irq (irq);
+#endif
 }
 
-void make_intc2_irq(unsigned int irq, unsigned int addr, 
-                   unsigned int group,int pos, int priority)
+/*
+ * Setup an INTC2 style interrupt.
+ * NOTE: Unlike IPR interrupts, parameters are not shifted by this code,
+ * allowing the use of the numbers straight out of the datasheet.
+ * For example:
+ *    PIO1 which is INTPRI00[19,16] and INTMSK00[13]
+ * would be:               ^     ^             ^  ^
+ *                         |     |             |  |
+ *    make_intc2_irq(84,   0,   16,            0, 13);
+ */
+void make_intc2_irq(unsigned int irq,
+                   unsigned int ipr_offset, unsigned int ipr_shift,
+                   unsigned int msk_offset, unsigned int msk_shift,
+                   unsigned int priority)
 {
-       int offset=irq-INTC2_FIRST_IRQ;
-       unsigned flags,val;
+       int irq_offset = irq - INTC2_FIRST_IRQ;
+       unsigned int flags;
+       unsigned long ipr;
 
-       if(offset<0 || offset>=NR_INTC2_IRQS) {
+       if((irq_offset<0) || (irq_offset>=NR_INTC2_IRQS))
                return;
-       }
 
        disable_irq_nosync(irq);
+
        /* Fill the data we need */
-       intc2_data[offset].addr=addr;
-       intc2_data[offset].mask=1<<pos;
+       intc2_data[irq_offset].msk_offset = msk_offset;
+       intc2_data[irq_offset].msk_shift  = msk_shift;
+#ifdef CONFIG_CPU_SUBTYPE_ST40
+       intc2_data[irq_offset].clear_irq = NULL;
+#endif
                
        /* Set the priority level */
        local_irq_save(flags);
-       val=ctrl_inl(addr+INTC2_INTPRI_OFFSET);
-       val|=(priority)<< (group<<4);
-       ctrl_outl(val,addr+INTC2_INTPRI_OFFSET);
+
+       ipr=ctrl_inl(INTC2_BASE+INTC2_INTPRI_OFFSET+ipr_offset);
+       ipr&=~(0xf<<ipr_shift);
+       ipr|=(priority)<<ipr_shift;
+       ctrl_outl(ipr, INTC2_BASE+INTC2_INTPRI_OFFSET+ipr_offset);
+
        local_irq_restore(flags);
 
        irq_desc[irq].handler=&intc2_irq_type;
@@ -123,5 +151,72 @@ void make_intc2_irq(unsigned int irq, unsigned int addr,
        disable_intc2_irq(irq);
 }
 
+#ifdef CONFIG_CPU_SUBTYPE_ST40
 
+struct intc2_init {
+       unsigned short irq;
+       unsigned char ipr_offset, ipr_shift;
+       unsigned char msk_offset, msk_shift;
+};
+
+static struct intc2_init intc2_init_data[]  __initdata = {
+       {64,  0,  0, 0,  0},    /* PCI serr */
+       {65,  0,  4, 0,  1},    /* PCI err */
+       {66,  0,  4, 0,  2},    /* PCI ad */
+       {67,  0,  4, 0,  3},    /* PCI pwd down */
+       {72,  0,  8, 0,  5},    /* DMAC INT0 */
+       {73,  0,  8, 0,  6},    /* DMAC INT1 */
+       {74,  0,  8, 0,  7},    /* DMAC INT2 */
+       {75,  0,  8, 0,  8},    /* DMAC INT3 */
+       {76,  0,  8, 0,  9},    /* DMAC INT4 */
+       {78,  0,  8, 0, 11},    /* DMAC ERR */
+       {80,  0, 12, 0, 12},    /* PIO0 */
+       {84,  0, 16, 0, 13},    /* PIO1 */
+       {88,  0, 20, 0, 14},    /* PIO2 */
+       {112, 4,  0, 4,  0},    /* Mailbox */
+#ifdef CONFIG_CPU_SUBTYPE_ST40GX1
+       {116, 4,  4, 4,  4},    /* SSC0 */
+       {120, 4,  8, 4,  8},    /* IR Blaster */
+       {124, 4, 12, 4, 12},    /* USB host */
+       {128, 4, 16, 4, 16},    /* Video processor BLITTER */
+       {132, 4, 20, 4, 20},    /* UART0 */
+       {134, 4, 20, 4, 22},    /* UART2 */
+       {136, 4, 24, 4, 24},    /* IO_PIO0 */
+       {140, 4, 28, 4, 28},    /* EMPI */
+       {144, 8,  0, 8,  0},    /* MAFE */
+       {148, 8,  4, 8,  4},    /* PWM */
+       {152, 8,  8, 8,  8},    /* SSC1 */
+       {156, 8, 12, 8, 12},    /* IO_PIO1 */
+       {160, 8, 16, 8, 16},    /* USB target */
+       {164, 8, 20, 8, 20},    /* UART1 */
+       {168, 8, 24, 8, 24},    /* Teletext */
+       {172, 8, 28, 8, 28},    /* VideoSync VTG */
+       {173, 8, 28, 8, 29},    /* VideoSync DVP0 */
+       {174, 8, 28, 8, 30},    /* VideoSync DVP1 */
+#endif
+};
+
+void __init init_IRQ_intc2(void)
+{
+       struct intc2_init *p;
+
+       printk(KERN_ALERT "init_IRQ_intc2\n");
+
+       for (p = intc2_init_data;
+            p<intc2_init_data+ARRAY_SIZE(intc2_init_data);
+            p++) {
+               make_intc2_irq(p->irq, p->ipr_offset, p->ipr_shift,
+                              p-> msk_offset, p->msk_shift, 13);
+       }
+}
+
+/* Adds a termination callback to the interrupt */
+void intc2_add_clear_irq(int irq, int (*fn)(int))
+{
+       if (irq < INTC2_FIRST_IRQ)
+               return;
+
+       intc2_data[irq - INTC2_FIRST_IRQ].clear_irq = fn;
+}
 
+#endif /* CONFIG_CPU_SUBTYPE_ST40 */