drm/gfx12: Program DB_RING_CONTROL

This is needed to allocate occlusion counters across
both gfx pipes. GFX 12 only has one gfx pipe, so no functional
change since the default value is 1.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 8221a77b6b75bbfdaab50ade23b956ebb400b612..6fedb6df8db94459d83b8abe2b2363fe438c879c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -1827,6 +1827,15 @@ static void gfx_v12_0_constants_init(struct amdgpu_device *adev)
        gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info);
        gfx_v12_0_get_tcc_info(adev);
        adev->gfx.config.pa_sc_tile_steering_override = 0;
+       /* Program DB_RING_CONTROL for multiple GFX pipes
+        * Default power up value is 1.
+        * Possible values:
+        * 0 - split occlusion counters between gfx pipes
+        * 1 - all occlusion counters to pipe 0
+        * 2 - all occlusion counters to pipe 1
+        */
+       WREG32_FIELD15_PREREG(GC, 0, DB_RING_CONTROL, COUNTER_CONTROL,
+                             (adev->gfx.me.num_pipe_per_me > 1) ? 0 : 1);
 
        /* XXX SH_MEM regs */
        /* where to put LDS, scratch, GPUVM in FSA64 space */