[ARM] Move ARMv4 wbi functions to separate file

This allows the ARMv4 write buffer + icache entry handling
instructions to be left out of a kernel which doesn't have separate
icache entry handling instructions.

diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 88ca1a91ef0ab7785f9ffaf4f741815ec01a420f..8d4045d105eea468ab579f0fcc26f958474b282d 100644 (file)
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -22,24 +22,21 @@ obj-$(CONFIG_DISCONTIGMEM) += discontig.o
 p-$(CONFIG_CPU_26)     += proc-arm2_3.o
 
 # ARMv3
-p-$(CONFIG_CPU_ARM610) += proc-arm6_7.o  tlb-v3.o   copypage-v3.o
-p-$(CONFIG_CPU_ARM710) += proc-arm6_7.o  tlb-v3.o   copypage-v3.o
+p-$(CONFIG_CPU_ARM610) += proc-arm6_7.o  tlb-v3.o    copypage-v3.o
+p-$(CONFIG_CPU_ARM710) += proc-arm6_7.o  tlb-v3.o    copypage-v3.o
 
 # ARMv4
-p-$(CONFIG_CPU_ARM720T)        += proc-arm720.o  tlb-v4.o   copypage-v4wt.o abort-lv4t.o
-p-$(CONFIG_CPU_ARM920T)        += proc-arm920.o  tlb-v4wb.o copypage-v4wb.o abort-ev4t.o
-p-$(CONFIG_CPU_ARM922T)        += proc-arm922.o  tlb-v4wb.o copypage-v4wb.o abort-ev4t.o
-p-$(CONFIG_CPU_ARM1020)        += proc-arm1020.o tlb-v4wb.o copypage-v4wb.o abort-ev4t.o
-p-$(CONFIG_CPU_SA110)  += proc-sa110.o   tlb-v4wb.o copypage-v4wb.o abort-ev4.o   minicache.o
-p-$(CONFIG_CPU_SA1100) += proc-sa110.o   tlb-v4wb.o copypage-v4mc.o abort-ev4.o   minicache.o
+p-$(CONFIG_CPU_ARM720T)        += proc-arm720.o  tlb-v4.o    copypage-v4wt.o abort-lv4t.o
+p-$(CONFIG_CPU_ARM920T)        += proc-arm920.o  tlb-v4wbi.o copypage-v4wb.o abort-ev4t.o
+p-$(CONFIG_CPU_ARM922T)        += proc-arm922.o  tlb-v4wbi.o copypage-v4wb.o abort-ev4t.o
+p-$(CONFIG_CPU_ARM1020)        += proc-arm1020.o tlb-v4wbi.o copypage-v4wb.o abort-ev4t.o
+p-$(CONFIG_CPU_SA110)  += proc-sa110.o   tlb-v4wb.o  copypage-v4wb.o abort-ev4.o   minicache.o
+p-$(CONFIG_CPU_SA1100) += proc-sa110.o   tlb-v4wb.o  copypage-v4mc.o abort-ev4.o   minicache.o
 
 # ARMv5
-p-$(CONFIG_CPU_ARM926T)        += proc-arm926.o  tlb-v4wb.o copypage-v4wb.o abort-ev5tej.o
-p-$(CONFIG_CPU_XSCALE) += proc-xscale.o  tlb-v4wb.o copypage-xscale.o abort-xscale.o minicache.o
+p-$(CONFIG_CPU_ARM926T)        += proc-arm926.o  tlb-v4wbi.o copypage-v4wb.o abort-ev5tej.o
+p-$(CONFIG_CPU_XSCALE) += proc-xscale.o  tlb-v4wbi.o copypage-xscale.o abort-xscale.o minicache.o
 
 obj-y          += $(sort $(p-y))
 
 include $(TOPDIR)/Rules.make
-
-# Special dependencies
-$(obj)/$(p-y): include/asm-arm/constants.h

diff --git a/arch/arm/mm/tlb-v4wb.S b/arch/arm/mm/tlb-v4wb.S
index 90ca6c7597a3e111315161f42f6651fa8a7b796e..3444855fb646bb3b1b249b6d8eab07516396350e 100644 (file)
--- a/arch/arm/mm/tlb-v4wb.S
+++ b/arch/arm/mm/tlb-v4wb.S
@@ -7,10 +7,10 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
- *  ARM architecture version 4 and version 5 TLB handling functions.
- *  These assume a split I/D TLBs, with a write buffer.
+ *  ARM architecture version 4 TLB handling functions.
+ *  These assume a split I/D TLBs w/o I TLB entry, with a write buffer.
  *
- *  Processors: ARM920 ARM922 ARM926 SA110 SA1100 SA1110 XScale
+ *  Processors: SA110 SA1100 SA1110
  */
 #include <linux/linkage.h>
 #include <linux/init.h>
@@ -67,50 +67,6 @@ ENTRY(v4wb_flush_kern_tlb_range)
        blo     1b
        mov     pc, lr
 
-/*
- * These two are optimised for ARM920, ARM922, ARM926, Xscale
- */
-
-/*
- *     v4wb_flush_user_tlb_range(start, end, mm)
- *
- *     Invalidate a range of TLB entries in the specified address space.
- *
- *     - start - range start address
- *     - end   - range end address
- *     - mm    - mm_struct describing address space
- */
-       .align  5
-ENTRY(v4wbi_flush_user_tlb_range)
-       vma_vm_mm ip, r2
-       act_mm  r3                              @ get current->active_mm
-       eors    r3, ip, r3                      @ == mm ?
-       movne   pc, lr                          @ no, we dont do anything
-       mov     r3, #0
-       mcr     p15, 0, r3, c7, c10, 4          @ drain WB
-       vma_vm_flags r2, r2
-       bic     r0, r0, #0x0ff
-       bic     r0, r0, #0xf00
-1:     tst     r2, #VM_EXEC
-       mcrne   p15, 0, r0, c8, c5, 1           @ invalidate I TLB entry
-       mcr     p15, 0, r0, c8, c6, 1           @ invalidate D TLB entry
-       add     r0, r0, #PAGE_SZ
-       cmp     r0, r1
-       blo     1b
-       mov     pc, lr
-
-ENTRY(v4wbi_flush_kern_tlb_range)
-       mov     r3, #0
-       mcr     p15, 0, r3, c7, c10, 4          @ drain WB
-       bic     r0, r0, #0x0ff
-       bic     r0, r0, #0xf00
-1:     mcr     p15, 0, r0, c8, c5, 1           @ invalidate I TLB entry
-       mcr     p15, 0, r0, c8, c6, 1           @ invalidate D TLB entry
-       add     r0, r0, #PAGE_SZ
-       cmp     r0, r1
-       blo     1b
-       mov     pc, lr
-
        __INIT
 
        .type   v4wb_tlb_fns, #object
@@ -119,10 +75,3 @@ ENTRY(v4wb_tlb_fns)
        .long   v4wb_flush_kern_tlb_range
        .long   v4wb_tlb_flags
        .size   v4wb_tlb_fns, . - v4wb_tlb_fns
-
-       .type   v4wbi_tlb_fns, #object
-ENTRY(v4wbi_tlb_fns)
-       .long   v4wbi_flush_user_tlb_range
-       .long   v4wbi_flush_kern_tlb_range
-       .long   v4wbi_tlb_flags
-       .size   v4wbi_tlb_fns, . - v4wbi_tlb_fns

diff --git a/arch/arm/mm/tlb-v4wbi.S b/arch/arm/mm/tlb-v4wbi.S
new file mode 100644 (file)
index 0000000..ecbdcd0
--- /dev/null
+++ b/arch/arm/mm/tlb-v4wbi.S
@@ -0,0 +1,68 @@
+/*
+ *  linux/arch/arm/mm/tlbv4wbi.S
+ *
+ *  Copyright (C) 1997-2002 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  ARM architecture version 4 and version 5 TLB handling functions.
+ *  These assume a split I/D TLBs, with a write buffer.
+ *
+ *  Processors: ARM920 ARM922 ARM926 XScale
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/constants.h>
+#include <asm/tlbflush.h>
+#include "proc-macros.S"
+
+/*
+ *     v4wb_flush_user_tlb_range(start, end, mm)
+ *
+ *     Invalidate a range of TLB entries in the specified address space.
+ *
+ *     - start - range start address
+ *     - end   - range end address
+ *     - mm    - mm_struct describing address space
+ */
+       .align  5
+ENTRY(v4wbi_flush_user_tlb_range)
+       vma_vm_mm ip, r2
+       act_mm  r3                              @ get current->active_mm
+       eors    r3, ip, r3                      @ == mm ?
+       movne   pc, lr                          @ no, we dont do anything
+       mov     r3, #0
+       mcr     p15, 0, r3, c7, c10, 4          @ drain WB
+       vma_vm_flags r2, r2
+       bic     r0, r0, #0x0ff
+       bic     r0, r0, #0xf00
+1:     tst     r2, #VM_EXEC
+       mcrne   p15, 0, r0, c8, c5, 1           @ invalidate I TLB entry
+       mcr     p15, 0, r0, c8, c6, 1           @ invalidate D TLB entry
+       add     r0, r0, #PAGE_SZ
+       cmp     r0, r1
+       blo     1b
+       mov     pc, lr
+
+ENTRY(v4wbi_flush_kern_tlb_range)
+       mov     r3, #0
+       mcr     p15, 0, r3, c7, c10, 4          @ drain WB
+       bic     r0, r0, #0x0ff
+       bic     r0, r0, #0xf00
+1:     mcr     p15, 0, r0, c8, c5, 1           @ invalidate I TLB entry
+       mcr     p15, 0, r0, c8, c6, 1           @ invalidate D TLB entry
+       add     r0, r0, #PAGE_SZ
+       cmp     r0, r1
+       blo     1b
+       mov     pc, lr
+
+       __INIT
+
+       .type   v4wbi_tlb_fns, #object
+ENTRY(v4wbi_tlb_fns)
+       .long   v4wbi_flush_user_tlb_range
+       .long   v4wbi_flush_kern_tlb_range
+       .long   v4wbi_tlb_flags
+       .size   v4wbi_tlb_fns, . - v4wbi_tlb_fns