drm/xe: Move engines' LRC programming RTP table off the stack

The 'lrc_setup' RTP table was allocated on the stack because it wasn't
truly constant and needed to calculate the proper value for BLIT_CCTL at
runtime based on other stack variables.  Using the FIELD_SET_FUNC action
allows us to make the table itself truly constant and move it off the
stack; the BLIT_CCTL value is now calculated during RTP table
processing.

v2:
 - Made table static

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patch.msgid.link/20260617-rtp_with_dynamic_vals-v2-3-3f4cb34c2ea1@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 98265293f2dce2e2a9fec5d0a7af082447445992..603bb197801afefc39859da4499e2413920290b4 100644 (file)
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -337,39 +337,41 @@ static bool xe_rtp_cfeg_wmtp_disabled(const struct xe_device *xe,
        return xe_mmio_read32(&hwe->gt->mmio, XEHP_FUSE4) & CFEG_WMTP_DISABLE;
 }
 
+static u32 blit_cctl_val(struct xe_gt *gt, struct xe_hw_engine *hwe)
+{
+       return REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, gt->mocs.uc_index) |
+               REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, gt->mocs.uc_index);
+}
+
+static const struct xe_rtp_table_sr lrc_setup = XE_RTP_TABLE_SR(
+       /*
+        * Some blitter commands do not have a field for MOCS, those
+        * commands will use MOCS index pointed by BLIT_CCTL.
+        * BLIT_CCTL registers are needed to be programmed to un-cached.
+        */
+       { XE_RTP_NAME("BLIT_CCTL_default_MOCS"),
+         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1274),
+                      ENGINE_CLASS(COPY)),
+         XE_RTP_ACTIONS(FIELD_SET_FUNC(BLIT_CCTL(0),
+                                       BLIT_CCTL_DST_MOCS_MASK |
+                                       BLIT_CCTL_SRC_MOCS_MASK,
+                                       blit_cctl_val,
+                                       XE_RTP_ACTION_FLAG(ENGINE_BASE)))
+       },
+       /* Disable WMTP if HW doesn't support it */
+       { XE_RTP_NAME("DISABLE_WMTP_ON_UNSUPPORTED_HW"),
+         XE_RTP_RULES(FUNC(xe_rtp_cfeg_wmtp_disabled)),
+         XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(0),
+                                  PREEMPT_GPGPU_LEVEL_MASK,
+                                  PREEMPT_GPGPU_THREAD_GROUP_LEVEL)),
+         XE_RTP_ENTRY_FLAG(FOREACH_ENGINE)
+       },
+);
+
 static void
 hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe)
 {
-       struct xe_gt *gt = hwe->gt;
-       const u8 mocs_write_idx = gt->mocs.uc_index;
-       const u8 mocs_read_idx = gt->mocs.uc_index;
-       u32 blit_cctl_val = REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, mocs_write_idx) |
-                           REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, mocs_read_idx);
        struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
-       const struct xe_rtp_table_sr lrc_setup = XE_RTP_TABLE_SR(
-               /*
-                * Some blitter commands do not have a field for MOCS, those
-                * commands will use MOCS index pointed by BLIT_CCTL.
-                * BLIT_CCTL registers are needed to be programmed to un-cached.
-                */
-               { XE_RTP_NAME("BLIT_CCTL_default_MOCS"),
-                 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1274),
-                              ENGINE_CLASS(COPY)),
-                 XE_RTP_ACTIONS(FIELD_SET(BLIT_CCTL(0),
-                                BLIT_CCTL_DST_MOCS_MASK |
-                                BLIT_CCTL_SRC_MOCS_MASK,
-                                blit_cctl_val,
-                                XE_RTP_ACTION_FLAG(ENGINE_BASE)))
-               },
-               /* Disable WMTP if HW doesn't support it */
-               { XE_RTP_NAME("DISABLE_WMTP_ON_UNSUPPORTED_HW"),
-                 XE_RTP_RULES(FUNC(xe_rtp_cfeg_wmtp_disabled)),
-                 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(0),
-                                          PREEMPT_GPGPU_LEVEL_MASK,
-                                          PREEMPT_GPGPU_THREAD_GROUP_LEVEL)),
-                 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE)
-               },
-       );
 
        xe_rtp_process_to_sr(&ctx, &lrc_setup, &hwe->reg_lrc, true);
 }