pinctrl: airoha: an7583: fix misprint in gpio19 pinconf

[ Upstream commit a7f3e2b7730fc1d6c7431af49e0dc1ee97589795 ]

Pin 21 (gpio19) duplicate pinconf settings of pin 20. Fix it using
a proper bit number in the configuration register.

Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c
index f10b2d1eb56bc465b33a6eca872e8d424600a813..99fee1b490d86a677845bd960f1ebd5dc39f9b71 100644 (file)
--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
@@ -2063,7 +2063,7 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
        PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
        PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
        PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
-       PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(18)),
+       PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)),
        PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
        PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
        PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
@@ -2180,7 +2180,7 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
        PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
        PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
        PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
-       PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(18)),
+       PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)),
        PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
        PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
        PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
@@ -2297,7 +2297,7 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
        PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
        PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
        PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
-       PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(18)),
+       PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)),
        PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
        PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
        PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
@@ -2414,7 +2414,7 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
        PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
        PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
        PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
-       PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(18)),
+       PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)),
        PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
        PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
        PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),