MIPS: BPF: Fix build on pre-R2 little endian CPUs

commit b259e51f2e29390518021f9b8df55a3de42f371b upstream.

The rotr, seh and wsbh instructions have been introduced with the R2
ISA. Thus the current BPF code fails to build on pre-R2 little endian
CPUs:

    CC      arch/mips/net/bpf_jit.o
    AS      arch/mips/net/bpf_jit_asm.o
  /home/aurel32/linux-4.2/arch/mips/net/bpf_jit_asm.S: Assembler messages:
  /home/aurel32/linux-4.2/arch/mips/net/bpf_jit_asm.S:67: Error: opcode not supported on this processor: mips32 (mips32) `wsbh $8,$19'
  /home/aurel32/linux-4.2/arch/mips/net/bpf_jit_asm.S:68: Error: opcode not supported on this processor: mips32 (mips32) `rotr $19,$8,16'
  /home/aurel32/linux-4.2/arch/mips/net/bpf_jit_asm.S:83: Error: opcode not supported on this processor: mips32 (mips32) `wsbh $8,$19'
  /home/aurel32/linux-4.2/arch/mips/net/bpf_jit_asm.S:84: Error: opcode not supported on this processor: mips32 (mips32) `seh $19,$8'
  /home/aurel32/linux-4.2/arch/mips/net/bpf_jit_asm.S:151: Error: opcode not supported on this processor: mips32 (mips32) `wsbh $8,$12'
  /home/aurel32/linux-4.2/arch/mips/net/bpf_jit_asm.S:153: Error: opcode not supported on this processor: mips32 (mips32) `rotr $19,$8,16'
  /home/aurel32/linux-4.2/arch/mips/net/bpf_jit_asm.S:164: Error: opcode not supported on this processor: mips32 (mips32) `wsbh $19,$12'
  /home/aurel32/linux-4.2/scripts/Makefile.build:294: recipe for target 'arch/mips/net/bpf_jit_asm.o' failed

Fix that by providing equivalent code for these CPUs.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11098/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/mips/net/bpf_jit_asm.S b/arch/mips/net/bpf_jit_asm.S
index 4f54cb18f1049b07e1dbdf8050a72c0004769de7..dabf4179cd7e373ac39dde61a6027f631a4544bc 100644 (file)
--- a/arch/mips/net/bpf_jit_asm.S
+++ b/arch/mips/net/bpf_jit_asm.S
@@ -64,8 +64,20 @@ sk_load_word_positive:
        PTR_ADDU t1, $r_skb_data, offset
        lw      $r_A, 0(t1)
 #ifdef CONFIG_CPU_LITTLE_ENDIAN
+# if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
        wsbh    t0, $r_A
        rotr    $r_A, t0, 16
+# else
+       sll     t0, $r_A, 24
+       srl     t1, $r_A, 24
+       srl     t2, $r_A, 8
+       or      t0, t0, t1
+       andi    t2, t2, 0xff00
+       andi    t1, $r_A, 0xff00
+       or      t0, t0, t2
+       sll     t1, t1, 8
+       or      $r_A, t0, t1
+# endif
 #endif
        jr      $r_ra
         move   $r_ret, zero
@@ -80,8 +92,16 @@ sk_load_half_positive:
        PTR_ADDU t1, $r_skb_data, offset
        lh      $r_A, 0(t1)
 #ifdef CONFIG_CPU_LITTLE_ENDIAN
+# if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
        wsbh    t0, $r_A
        seh     $r_A, t0
+# else
+       sll     t0, $r_A, 24
+       andi    t1, $r_A, 0xff00
+       sra     t0, t0, 16
+       srl     t1, t1, 8
+       or      $r_A, t0, t1
+# endif
 #endif
        jr      $r_ra
         move   $r_ret, zero
@@ -148,9 +168,22 @@ sk_load_byte_positive:
 NESTED(bpf_slow_path_word, (6 * SZREG), $r_sp)
        bpf_slow_path_common(4)
 #ifdef CONFIG_CPU_LITTLE_ENDIAN
+# if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
        wsbh    t0, $r_s0
        jr      $r_ra
         rotr   $r_A, t0, 16
+# else
+       sll     t0, $r_s0, 24
+       srl     t1, $r_s0, 24
+       srl     t2, $r_s0, 8
+       or      t0, t0, t1
+       andi    t2, t2, 0xff00
+       andi    t1, $r_s0, 0xff00
+       or      t0, t0, t2
+       sll     t1, t1, 8
+       jr      $r_ra
+        or     $r_A, t0, t1
+# endif
 #else
        jr      $r_ra
         move   $r_A, $r_s0
@@ -161,8 +194,17 @@ NESTED(bpf_slow_path_word, (6 * SZREG), $r_sp)
 NESTED(bpf_slow_path_half, (6 * SZREG), $r_sp)
        bpf_slow_path_common(2)
 #ifdef CONFIG_CPU_LITTLE_ENDIAN
+# if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
        jr      $r_ra
         wsbh   $r_A, $r_s0
+# else
+       sll     t0, $r_s0, 8
+       andi    t1, $r_s0, 0xff00
+       andi    t0, t0, 0xff00
+       srl     t1, t1, 8
+       jr      $r_ra
+        or     $r_A, t0, t1
+# endif
 #else
        jr      $r_ra
         move   $r_A, $r_s0