drm/xe/xe_ras: Add drm_ras feature flag

Add xe drm_ras feature flag. Enable this flag for PVC and CRI to support
exposing RAS error counters via netlink.

Reviewed-by: Raag Jadav <raag.jadav@intel.com>
Link: https://patch.msgid.link/20260618060633.2790109-14-riana.tauro@intel.com
Signed-off-by: Riana Tauro <riana.tauro@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index b687a2eeead328fbd42bab9cdb3c3054e174bb6c..d3fbcf10f8abe5c2294c8daa1b695dd606f1cb72 100644 (file)
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -742,6 +742,7 @@ static void vf_update_device_info(struct xe_device *xe)
        xe->info.has_late_bind = 0;
        xe->info.skip_guc_pc = 1;
        xe->info.skip_pcode = 1;
+       xe->info.has_drm_ras = false;
 }
 
 static int xe_device_vram_alloc(struct xe_device *xe)

diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 32dd2ffbc796397028a1fb0025f0cc0db2d399d3..4e2f115f14e2032c7c2a08fe31a562c7e21419a3 100644 (file)
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -156,6 +156,8 @@ struct xe_device {
                u8 has_cached_pt:1;
                /** @info.has_device_atomics_on_smem: Supports device atomics on SMEM */
                u8 has_device_atomics_on_smem:1;
+               /** @info.has_drm_ras: Device supports drm_ras (Reliability, Availability, Serviceability) */
+               u8 has_drm_ras:1;
                /** @info.has_fan_control: Device supports fan control */
                u8 has_fan_control:1;
                /** @info.has_flat_ccs: Whether flat CCS metadata is used */

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 3165686e3e04bc455c0a98f3c95c265de83d8c69..c9d4fb6c4ff6ab570fd4aa9484363406823bdb1f 100644 (file)
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -355,6 +355,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = {
        PLATFORM(PVC),
        .dma_mask_size = 52,
        .has_display = false,
+       .has_drm_ras = true,
        .has_gsc_nvm = 1,
        .has_heci_gscfi = 1,
        .max_gt_per_tile = 1,
@@ -457,6 +458,7 @@ static const struct xe_device_desc cri_desc = {
        PLATFORM(CRESCENTISLAND),
        .dma_mask_size = 52,
        .has_display = false,
+       .has_drm_ras = true,
        .has_flat_ccs = false,
        .has_gsc_nvm = 1,
        .has_i2c = true,
@@ -760,6 +762,7 @@ static int xe_info_init_early(struct xe_device *xe,
 
        xe->info.is_dgfx = desc->is_dgfx;
        xe->info.has_cached_pt = desc->has_cached_pt;
+       xe->info.has_drm_ras = desc->has_drm_ras;
        xe->info.has_fan_control = desc->has_fan_control;
        /* runtime fusing may force flat_ccs to disabled later */
        xe->info.has_flat_ccs = desc->has_flat_ccs;

diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index 5b85e2c24b7b2874192b9de89cbead8346688e99..24d4a3d005178a03d5995e220ee40e55dc944973 100644 (file)
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -40,6 +40,7 @@ struct xe_device_desc {
 
        u8 has_cached_pt:1;
        u8 has_display:1;
+       u8 has_drm_ras:1;
        u8 has_fan_control:1;
        u8 has_flat_ccs:1;
        u8 has_gsc_nvm:1;

diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 71ee9eeb18969415bb6db1e268015232aac85e2e..44f4e1a3455b7c77c96411268db2c9100dc21ff7 100644 (file)
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -278,7 +278,7 @@ int xe_ras_clear_counter(struct xe_device *xe, u8 severity, u8 component)
  */
 void xe_ras_init(struct xe_device *xe)
 {
-       if (xe->info.platform != XE_PVC)
+       if (!xe->info.has_drm_ras)
                return;
 
        xe_drm_ras_init(xe);