#
-# Makefile for the linux MPC4xx ppc-specific parts
+# Makefile for the linux MPC4xx ppc-specific parts
#
/* -----------------------------------------------------------------------------
- * From STB03xxx SICC UART Specification
+ * From STB03xxx SICC UART Specification
* -----------------------------------------------------------------------------
* UART Register Offsets.
*/
unsigned int fifosize;
unsigned int tiocm_support;
void (*set_mctrl)(struct SICC_port *, u_int mctrl);
-};
+};
/*
* This is the state information which is persistent across opens
/* As a last resort, if the quotient is zero, default to 9600 bps */
if (!quot)
quot = (info->port->uartclk / (16 * 9600)) - 1;
-
+
info->timeout = info->port->fifosize * HZ * bits / baud;
info->timeout += HZ/50; /* Add .02 seconds of slop */
SICC_XMIT_SIZE) > 0) &&
!info->tty->stopped && !info->tty->hw_stopped))
result &= TIOCSER_TEMT;
-
+
return put_user(result, value);
}
cep->stats.tx_bytes += skb->len;
cep->skb_cur = (cep->skb_cur+1) & TX_RING_MOD_MASK;
-
+
spin_lock_irq(&cep->lock);
/* Send it on its way. Tell CPM its ready, interrupt when done,
for (;;) {
if (bdp->cbd_sc & BD_ENET_RX_EMPTY)
break;
-
+
#ifndef final_version
/* Since we have allocated space to hold a complete frame, both
* the first and last indicators should be set.
ep = (scc_enet_t *)dev->base_addr;
if (dev->flags&IFF_PROMISC) {
-
+
/* Log any net taps. */
printk("%s: Promiscuous mode enabled.\n", dev->name);
cep->sccp->scc_pmsr |= SCC_PSMR_PRO;
dmi = dev->mc_list;
for (i=0; i<dev->mc_count; i++) {
-
+
/* Only support group multicast for now.
*/
if (!(dmi->dmi_addr[0] & 1))
(PC_ENET_RENA | PC_ENET_CLSN | PC_ENET_TXCLK | PC_ENET_RXCLK);
io->iop_pdirc &=
~(PC_ENET_RENA | PC_ENET_CLSN | PC_ENET_TXCLK | PC_ENET_RXCLK);
- io->iop_psorc &=
+ io->iop_psorc &=
~(PC_ENET_RENA | PC_ENET_TXCLK | PC_ENET_RXCLK);
io->iop_psorc |= PC_ENET_CLSN;
* down. We now issue a restart transmit. Since the
* errors close the BD and update the pointers, the restart
* _should_ pick up without having to reset any of our
- * pointers either. Also, To workaround 8260 device erratum
+ * pointers either. Also, To workaround 8260 device erratum
* CPM37, we must disable and then re-enable the transmitter
* following a Late Collision, Underrun, or Retry Limit error.
*/
for (;;) {
if (bdp->cbd_sc & BD_ENET_RX_EMPTY)
break;
-
+
#ifndef final_version
/* Since we have allocated space to hold a complete frame, both
* the first and last indicators should be set.
ep = (fcc_enet_t *)dev->base_addr;
if (dev->flags&IFF_PROMISC) {
-
+
/* Log any net taps. */
printk("%s: Promiscuous mode enabled.\n", dev->name);
cep->fccp->fcc_fpsmr |= FCC_PSMR_PRO;
dmi = dev->mc_list;
for (i=0; i<dev->mc_count; i++) {
-
+
/* Only support group multicast for now.
*/
if (!(dmi->dmi_addr[0] & 1))
cep = (struct fcc_enet_private *)(dev->priv);
ep = cep->ep;
-
+
if (netif_running(dev))
return -EBUSY;
memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
-
+
eap = (unsigned char *) &(ep->fen_paddrh);
for (i=5; i>=0; i--)
*eap++ = addr->sa_data[i];
ep->fen_genfcc.fcc_tiptr = mem_addr+32;
ep->fen_padptr = mem_addr+64;
memset((char *)(&(immap->im_dprambase[(mem_addr+64)])), 0x88, 32);
-
+
ep->fen_genfcc.fcc_rbptr = 0;
ep->fen_genfcc.fcc_tbptr = 0;
ep->fen_genfcc.fcc_rcrc = 0;
fccp->fcc_gfmr &= ~(FCC_GFMR_ENR | FCC_GFMR_ENT);
}
#endif /* CONFIG_USE_MDIO */
-
+
static void
fcc_restart(struct net_device *dev, int duplex)
{
#undef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
#define _INLINE_ inline
-
+
#define DBG_CNT(s)
/* We overload some of the items in the data structure to meet our
if (serial_paranoia_check(info, tty->name, "rs_stop"))
return;
-
+
save_flags(flags); cli();
if ((idx = info->state->smc_scc_num) < SCC_NUM_BASE) {
smcp = &immr->im_smc[idx];
if (serial_paranoia_check(info, tty->name, "rs_stop"))
return;
-
+
save_flags(flags); cli();
if ((idx = info->state->smc_scc_num) < SCC_NUM_BASE) {
smcp = &immr->im_smc[idx];
* rs_interrupt() should try to keep the interrupt handler as fast as
* possible. After you are done making modifications, it is not a bad
* idea to do:
- *
+ *
* gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c
*
* and look at the resulting assemble code in serial.s.
}
*/
status &= info->read_status_mask;
-
+
if (status & (BD_SC_BR)) {
#ifdef SERIAL_DEBUG_INTR
printk("handling break....");
break_pressed = 0;
}
#endif
-
+
if (tty->flip.count >= TTY_FLIPBUF_SIZE)
break;
static _INLINE_ void transmit_chars(ser_info_t *info, struct pt_regs *regs)
{
-
+
if (info->flags & TX_WAKEUP) {
rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
}
{
int status;
struct async_icount *icount;
-
+
status = serial_in(info, UART_MSR);
if (status & UART_MSR_ANY_DELTA) {
#if (defined(SERIAL_DEBUG_OPEN) || defined(SERIAL_DEBUG_INTR))
printk("ttys%d CD now %s...", info->line,
(status & UART_MSR_DCD) ? "on" : "off");
-#endif
+#endif
if (status & UART_MSR_DCD)
wake_up_interruptible(&info->open_wait);
else {
ser_info_t *info;
volatile smc_t *smcp;
volatile scc_t *sccp;
-
+
info = (ser_info_t *)dev_id;
if ((idx = info->state->smc_scc_num) < SCC_NUM_BASE) {
transmit_chars(info, regs);
sccp->scc_scce = events;
}
-
+
#ifdef SERIAL_DEBUG_INTR
printk("rs_interrupt_single(%d, %x)...",
info->state->smc_scc_num, events);
{
ser_info_t *info = (ser_info_t *) private_;
struct tty_struct *tty;
-
+
tty = info->tty;
if (!tty)
return;
*
* serial interrupt routine -> (scheduler tqueue) ->
* do_serial_hangup() -> tty->hangup() -> rs_hangup()
- *
+ *
*/
static void do_serial_hangup(void *private_)
{
struct async_struct *info = (struct async_struct *) private_;
struct tty_struct *tty;
-
+
tty = info->tty;
if (tty)
tty_hangup(tty);
if (info->tty->termios->c_cflag & CBAUD)
info->MCR = UART_MCR_DTR | UART_MCR_RTS;
#endif
-
+
if (info->tty)
clear_bit(TTY_IO_ERROR, &info->tty->flags);
* and set the speed of the serial port
*/
change_speed(info);
-
+
if ((idx = info->state->smc_scc_num) < SCC_NUM_BASE) {
smcp = &immr->im_smc[idx];
info->flags |= ASYNC_INITIALIZED;
restore_flags(flags);
return 0;
-
+
errout:
restore_flags(flags);
return retval;
printk("Shutting down serial port %d (irq %d)....", info->line,
state->irq);
#endif
-
+
save_flags(flags); cli(); /* Disable interrupts */
if ((idx = info->state->smc_scc_num) < SCC_NUM_BASE) {
sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
#endif
}
-
+
if (info->tty)
set_bit(TTY_IO_ERROR, &info->tty->flags);
info->read_status_mask |= BD_SC_FR | BD_SC_PR;
if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
info->read_status_mask |= BD_SC_BR;
-
+
/*
* Characters to ignore
*/
if (I_IGNBRK(info->tty)) {
info->ignore_status_mask |= BD_SC_BR;
/*
- * If we're ignore parity and break indicators, ignore
+ * If we're ignore parity and break indicators, ignore
* overruns too. (For real raw support).
*/
if (I_IGNPAR(info->tty))
if (serial_paranoia_check(info, tty->name, "rs_write"))
return 0;
- if (!tty)
+ if (!tty)
return 0;
bdp = info->tx_cur;
static int rs_8xx_chars_in_buffer(struct tty_struct *tty)
{
ser_info_t *info = (ser_info_t *)tty->driver_data;
-
+
if (serial_paranoia_check(info, tty->name, "rs_chars_in_buffer"))
return 0;
return 0;
static void rs_8xx_flush_buffer(struct tty_struct *tty)
{
ser_info_t *info = (ser_info_t *)tty->driver_data;
-
+
if (serial_paranoia_check(info, tty->name, "rs_flush_buffer"))
return;
/*
* ------------------------------------------------------------
* rs_throttle()
- *
+ *
* This routine is called by the upper-layer tty layer to signal that
* incoming characters should be throttled.
* ------------------------------------------------------------
ser_info_t *info = (ser_info_t *)tty->driver_data;
#ifdef SERIAL_DEBUG_THROTTLE
char buf[64];
-
+
printk("throttle %s: %d....\n", _tty_name(tty, buf),
tty->ldisc.chars_in_buffer(tty));
#endif
if (serial_paranoia_check(info, tty->name, "rs_throttle"))
return;
-
+
if (I_IXOFF(tty))
rs_8xx_send_xchar(tty, STOP_CHAR(tty));
ser_info_t *info = (ser_info_t *)tty->driver_data;
#ifdef SERIAL_DEBUG_THROTTLE
char buf[64];
-
+
printk("unthrottle %s: %d....\n", _tty_name(tty, buf),
tty->ldisc.chars_in_buffer(tty));
#endif
if (serial_paranoia_check(info, tty->name, "rs_unthrottle"))
return;
-
+
if (I_IXOFF(tty)) {
if (info->x_char)
info->x_char = 0;
* release the bus after transmitting. This must be done when
* the transmit shift register is empty, not be done when the
* transmit holding register is empty. This functionality
- * allows an RS485 driver to be written in user space.
+ * allows an RS485 driver to be written in user space.
*/
static int get_lsr_info(struct async_struct * info, unsigned int *value)
{
return error;
#ifdef modem_control
switch (cmd) {
- case TIOCMBIS:
+ case TIOCMBIS:
if (arg & TIOCM_RTS)
info->MCR |= UART_MCR_RTS;
if (arg & TIOCM_DTR)
if (tty->flags & (1 << TTY_IO_ERROR))
return -EIO;
}
-
+
switch (cmd) {
case TCSBRK: /* SVID version: non-zero arg --> no break */
retval = tty_check_change(tty);
cli();
cnow = info->state->icount; /* atomic copy */
sti();
- if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
+ if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
cnow.dcd == cprev.dcd && cnow.cts == cprev.cts)
return -EIO; /* no change => error */
if ( ((arg & TIOCM_RNG) && (cnow.rng != cprev.rng)) ||
return 0;
#endif
- /*
+ /*
* Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
* Return: write counters to the user passed counter struct
* NB: both 1->0 and 0->1 transitions are counted except for
ser_info_t *info = (ser_info_t *)tty->driver_data;
if ( (tty->termios->c_cflag == old_termios->c_cflag)
- && ( RELEVANT_IFLAG(tty->termios->c_iflag)
+ && ( RELEVANT_IFLAG(tty->termios->c_iflag)
== RELEVANT_IFLAG(old_termios->c_iflag)))
return;
serial_out(info, UART_MCR, info->MCR);
sti();
}
-
+
/* Handle transition away from B0 status */
if (!(old_termios->c_cflag & CBAUD) &&
(tty->termios->c_cflag & CBAUD)) {
serial_out(info, UART_MCR, info->MCR);
sti();
}
-
+
/* Handle turning off CRTSCTS */
if ((old_termios->c_cflag & CRTSCTS) &&
!(tty->termios->c_cflag & CRTSCTS)) {
/*
* ------------------------------------------------------------
* rs_close()
- *
+ *
* This routine is called when the serial port gets closed. First, we
* wait for the last remaining data to be sent. Then, we unlink its
* async structure from the interrupt chain if necessary, and we free
return;
state = info->state;
-
+
save_flags(flags); cli();
-
+
if (tty_hung_up_p(filp)) {
DBG_CNT("before DEC-hung");
MOD_DEC_USE_COUNT;
restore_flags(flags);
return;
}
-
+
#ifdef SERIAL_DEBUG_OPEN
printk("rs_close ttys%d, count = %d\n", info->line, state->count);
#endif
}
info->flags |= ASYNC_CLOSING;
/*
- * Now we wait for the transmit buffer to clear; and we notify
+ * Now we wait for the transmit buffer to clear; and we notify
* the line discipline to only process XON/XOFF characters.
*/
tty->closing = 1;
unsigned long orig_jiffies, char_time;
/*int lsr;*/
volatile cbd_t *bdp;
-
+
if (serial_paranoia_check(info, tty->name, "rs_wait_until_sent"))
return;
* Set the check interval to be 1/5 of the estimated time to
* send a single character, and make it at least 1. The check
* interval should also be less than the timeout.
- *
+ *
* Note: we have to use pretty tight timings here to satisfy
* the NIST-PCTS.
*/
{
ser_info_t *info = (ser_info_t *)tty->driver_data;
struct serial_state *state = info->state;
-
+
if (serial_paranoia_check(info, tty->name, "rs_hangup"))
return;
state = info->state;
-
+
rs_8xx_flush_buffer(tty);
shutdown(info);
info->event = 0;
state->line, state->count);
#endif
cli();
- if (!tty_hung_up_p(filp))
+ if (!tty_hung_up_p(filp))
state->count--;
sti();
info->blocked_open++;
if (info->flags & ASYNC_HUP_NOTIFY)
retval = -EAGAIN;
else
- retval = -ERESTARTSYS;
+ retval = -ERESTARTSYS;
#else
retval = -EAGAIN;
#endif
status = serial_in(info, UART_MSR);
control = info ? info->MCR : serial_in(info, UART_MCR);
sti();
-
+
stat_buf[0] = 0;
stat_buf[1] = 0;
if (control & UART_MCR_RTS)
if (state->icount.frame)
ret += sprintf(buf+ret, " fe:%d", state->icount.frame);
-
+
if (state->icount.parity)
ret += sprintf(buf+ret, " pe:%d", state->icount.parity);
-
+
if (state->icount.brk)
- ret += sprintf(buf+ret, " brk:%d", state->icount.brk);
+ ret += sprintf(buf+ret, " brk:%d", state->icount.brk);
if (state->icount.overrun)
ret += sprintf(buf+ret, " oe:%d", state->icount.overrun);
else
cp = __va(bdp->cbd_bufaddr);
*cp = *s;
-
+
bdp->cbd_datlen = 1;
bdp->cbd_sc |= BD_SC_READY;
unsigned count)
{
#if defined(CONFIG_KGDB_CONSOLE) && !defined(CONFIG_USE_SERIAL2_KGDB)
- /* Try to let stub handle output. Returns true if it did. */
+ /* Try to let stub handle output. Returns true if it did. */
if (kgdb_output_string(s, count))
return;
#endif
volatile scc_uart_t *sup;
volatile immap_t *immap;
volatile iop8260_t *io;
-
+
serial_driver = alloc_tty_driver(NR_PORTS);
if (!serial_driver)
return -ENOMEM;
show_serial_version();
/* Initialize the tty_driver structure */
-
+
serial_driver->driver_name = "serial";
serial_driver->devfs_name = "tts/";
serial_driver->name = "ttyS";
state->custom_divisor = 0;
state->close_delay = 5*HZ/10;
state->closing_wait = 30*HZ;
- state->icount.cts = state->icount.dsr =
+ state->icount.cts = state->icount.dsr =
state->icount.rng = state->icount.dcd = 0;
state->icount.rx = state->icount.tx = 0;
state->icount.frame = state->icount.parity = 0;
* Enable receive and transmit.
*/
scp->scc_gsmrh = 0;
- scp->scc_gsmrl =
+ scp->scc_gsmrl =
(SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
/* Disable all interrupts and clear all pending
* Enable receive and transmit.
*/
scp->scc_gsmrh = 0;
- scp->scc_gsmrl =
+ scp->scc_gsmrl =
(SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
/* Disable all interrupts and clear all pending
int hSpeed = sound.hard.speed, sSpeed = sound.soft.speed;
int utotal, ftotal;
int stereo = sound.soft.stereo;
-
+
frameLeft >>= 2;
if (stereo)
userCount >>= 1;
read_sq_setup(numReadBufs,readbufSize<<10, sound_read_buffers);
read_sq.open_mode = file->f_mode;
- }
+ }
/* Start up the 4218 by:
* Reset.
cep->stats.tx_bytes += skb->len;
cep->skb_cur = (cep->skb_cur+1) & TX_RING_MOD_MASK;
-
+
/* Push the data cache so the CPM does not get stale memory
* data.
*/
for (;;) {
if (bdp->cbd_sc & BD_ENET_RX_EMPTY)
break;
-
+
#ifndef final_version
/* Since we have allocated space to hold a complete frame, both
* the first and last indicators should be set.
ep = (scc_enet_t *)dev->base_addr;
if (dev->flags&IFF_PROMISC) {
-
+
/* Log any net taps. */
printk("%s: Promiscuous mode enabled.\n", dev->name);
cep->sccp->scc_pmsr |= SCC_PMSR_PRO;
dmi = dev->mc_list;
for (i=0; i<dev->mc_count; i++) {
-
+
/* Only support group multicast for now.
*/
if (!(dmi->dmi_addr[0] & 1))
#undef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
#define _INLINE_ inline
-
+
#define DBG_CNT(s)
/* We overload some of the items in the data structure to meet our
if (serial_paranoia_check(info, tty->name, "rs_stop"))
return;
-
+
save_flags(flags); cli();
idx = PORT_NUM(info->state->smc_scc_num);
if (info->state->smc_scc_num & NUM_IS_SCC) {
if (serial_paranoia_check(info, tty->name, "rs_stop"))
return;
-
+
idx = PORT_NUM(info->state->smc_scc_num);
save_flags(flags); cli();
if (info->state->smc_scc_num & NUM_IS_SCC) {
* rs_interrupt() should try to keep the interrupt handler as fast as
* possible. After you are done making modifications, it is not a bad
* idea to do:
- *
+ *
* gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c
*
* and look at the resulting assemble code in serial.s.
}
#if defined(CONFIG_SERIAL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
if (break_pressed && info->line == sercons.index) {
- if (ch != 0 && time_before(jiffies,
+ if (ch != 0 && time_before(jiffies,
break_pressed + HZ*5)) {
handle_sysrq(ch, regs, NULL);
break_pressed = 0;
}
#if defined(CONFIG_SERIAL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
- ignore_char:
+ ignore_char:
#endif
/* This BD is ready to be used again. Clear status.
* Get next BD.
static _INLINE_ void transmit_chars(ser_info_t *info, struct pt_regs *regs)
{
-
+
if ((info->flags & TX_WAKEUP) ||
(info->tty->flags & (1 << TTY_DO_WRITE_WAKEUP))) {
rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
{
int status;
struct async_icount *icount;
-
+
status = serial_in(info, UART_MSR);
if (status & UART_MSR_ANY_DELTA) {
#if (defined(SERIAL_DEBUG_OPEN) || defined(SERIAL_DEBUG_INTR))
printk("ttys%d CD now %s...", info->line,
(status & UART_MSR_DCD) ? "on" : "off");
-#endif
+#endif
if (status & UART_MSR_DCD)
wake_up_interruptible(&info->open_wait);
else {
ser_info_t *info;
volatile smc_t *smcp;
volatile scc_t *sccp;
-
+
info = (ser_info_t *)dev_id;
idx = PORT_NUM(info->state->smc_scc_num);
transmit_chars(info, regs);
smcp->smc_smce = events;
}
-
+
#ifdef SERIAL_DEBUG_INTR
printk("rs_interrupt_single(%d, %x)...",
info->state->smc_scc_num, events);
{
ser_info_t *info = (ser_info_t *) private_;
struct tty_struct *tty;
-
+
tty = info->tty;
if (!tty)
return;
*
* serial interrupt routine -> (scheduler tqueue) ->
* do_serial_hangup() -> tty->hangup() -> rs_hangup()
- *
+ *
*/
static void do_serial_hangup(void *private_)
{
struct async_struct *info = (struct async_struct *) private_;
struct tty_struct *tty;
-
+
tty = info->tty;
if (tty)
tty_hangup(tty);
if (info->tty->termios->c_cflag & CBAUD)
info->MCR = UART_MCR_DTR | UART_MCR_RTS;
#endif
-
+
if (info->tty)
clear_bit(TTY_IO_ERROR, &info->tty->flags);
* and set the speed of the serial port
*/
change_speed(info);
-
+
idx = PORT_NUM(info->state->smc_scc_num);
if (info->state->smc_scc_num & NUM_IS_SCC) {
sccp = &cpmp->cp_scc[idx];
info->flags |= ASYNC_INITIALIZED;
restore_flags(flags);
return 0;
-
+
errout:
restore_flags(flags);
return retval;
printk("Shutting down serial port %d (irq %d)....", info->line,
state->irq);
#endif
-
+
save_flags(flags); cli(); /* Disable interrupts */
idx = PORT_NUM(state->smc_scc_num);
#endif
smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
}
-
+
if (info->tty)
set_bit(TTY_IO_ERROR, &info->tty->flags);
info->read_status_mask |= BD_SC_FR | BD_SC_PR;
if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
info->read_status_mask |= BD_SC_BR;
-
+
/*
* Characters to ignore
*/
if (I_IGNBRK(info->tty)) {
info->ignore_status_mask |= BD_SC_BR;
/*
- * If we're ignore parity and break indicators, ignore
+ * If we're ignore parity and break indicators, ignore
* overruns too. (For real raw support).
*/
if (I_IGNPAR(info->tty))
sccp = &cpmp->cp_scc[idx];
new_mode = (sbits << 12) | scval;
prev_mode = sccp->scc_pmsr;
- if (!(prev_mode & SCU_PMSR_PEN))
+ if (!(prev_mode & SCU_PMSR_PEN))
/* If parity is disabled, mask out even/odd */
prev_mode &= ~(SCU_PMSR_TPM|SCU_PMSR_RPM);
if (prev_mode != new_mode)
unsigned char *cp;
#ifdef CONFIG_KGDB_CONSOLE
- /* Try to let stub handle output. Returns true if it did. */
+ /* Try to let stub handle output. Returns true if it did. */
if (kgdb_output_string(buf, count))
return ret;
#endif
if (serial_paranoia_check(info, tty->name, "rs_write"))
return 0;
- if (!tty)
+ if (!tty)
return 0;
bdp = info->tx_cur;
static int rs_8xx_chars_in_buffer(struct tty_struct *tty)
{
ser_info_t *info = (ser_info_t *)tty->driver_data;
-
+
if (serial_paranoia_check(info, tty->name, "rs_chars_in_buffer"))
return 0;
return 0;
static void rs_8xx_flush_buffer(struct tty_struct *tty)
{
ser_info_t *info = (ser_info_t *)tty->driver_data;
-
+
if (serial_paranoia_check(info, tty->name, "rs_flush_buffer"))
return;
/*
* ------------------------------------------------------------
* rs_throttle()
- *
+ *
* This routine is called by the upper-layer tty layer to signal that
* incoming characters should be throttled.
* ------------------------------------------------------------
ser_info_t *info = (ser_info_t *)tty->driver_data;
#ifdef SERIAL_DEBUG_THROTTLE
char buf[64];
-
+
printk("throttle %s: %d....\n", _tty_name(tty, buf),
tty->ldisc.chars_in_buffer(tty));
#endif
if (serial_paranoia_check(info, tty->name, "rs_throttle"))
return;
-
+
if (I_IXOFF(tty))
rs_8xx_send_xchar(tty, STOP_CHAR(tty));
ser_info_t *info = (ser_info_t *)tty->driver_data;
#ifdef SERIAL_DEBUG_THROTTLE
char buf[64];
-
+
printk("unthrottle %s: %d....\n", _tty_name(tty, buf),
tty->ldisc.chars_in_buffer(tty));
#endif
if (serial_paranoia_check(info, tty->name, "rs_unthrottle"))
return;
-
+
if (I_IXOFF(tty)) {
if (info->x_char)
info->x_char = 0;
* release the bus after transmitting. This must be done when
* the transmit shift register is empty, not be done when the
* transmit holding register is empty. This functionality
- * allows an RS485 driver to be written in user space.
+ * allows an RS485 driver to be written in user space.
*/
static int get_lsr_info(struct async_struct * info, unsigned int *value)
{
return error;
#ifdef modem_control
switch (cmd) {
- case TIOCMBIS:
+ case TIOCMBIS:
if (arg & TIOCM_RTS)
info->MCR |= UART_MCR_RTS;
if (arg & TIOCM_DTR)
if (tty->flags & (1 << TTY_IO_ERROR))
return -EIO;
}
-
+
switch (cmd) {
case TCSBRK: /* SVID version: non-zero arg --> no break */
retval = tty_check_change(tty);
cli();
cnow = info->state->icount; /* atomic copy */
sti();
- if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
+ if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
cnow.dcd == cprev.dcd && cnow.cts == cprev.cts)
return -EIO; /* no change => error */
if ( ((arg & TIOCM_RNG) && (cnow.rng != cprev.rng)) ||
return 0;
#endif
- /*
+ /*
* Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
* Return: write counters to the user passed counter struct
* NB: both 1->0 and 0->1 transitions are counted except for
ser_info_t *info = (ser_info_t *)tty->driver_data;
if ( (tty->termios->c_cflag == old_termios->c_cflag)
- && ( RELEVANT_IFLAG(tty->termios->c_iflag)
+ && ( RELEVANT_IFLAG(tty->termios->c_iflag)
== RELEVANT_IFLAG(old_termios->c_iflag)))
return;
serial_out(info, UART_MCR, info->MCR);
sti();
}
-
+
/* Handle transition away from B0 status */
if (!(old_termios->c_cflag & CBAUD) &&
(tty->termios->c_cflag & CBAUD)) {
serial_out(info, UART_MCR, info->MCR);
sti();
}
-
+
/* Handle turning off CRTSCTS */
if ((old_termios->c_cflag & CRTSCTS) &&
!(tty->termios->c_cflag & CRTSCTS)) {
/*
* ------------------------------------------------------------
* rs_close()
- *
+ *
* This routine is called when the serial port gets closed. First, we
* wait for the last remaining data to be sent. Then, we unlink its
* async structure from the interrupt chain if necessary, and we free
return;
state = info->state;
-
+
save_flags(flags); cli();
-
+
if (tty_hung_up_p(filp)) {
DBG_CNT("before DEC-hung");
MOD_DEC_USE_COUNT;
restore_flags(flags);
return;
}
-
+
#ifdef SERIAL_DEBUG_OPEN
printk("rs_close ttys%d, count = %d\n", info->line, state->count);
#endif
}
info->flags |= ASYNC_CLOSING;
/*
- * Now we wait for the transmit buffer to clear; and we notify
+ * Now we wait for the transmit buffer to clear; and we notify
* the line discipline to only process XON/XOFF characters.
*/
tty->closing = 1;
unsigned long orig_jiffies, char_time;
/*int lsr;*/
volatile cbd_t *bdp;
-
+
if (serial_paranoia_check(info, tty->name, "rs_wait_until_sent"))
return;
* Set the check interval to be 1/5 of the estimated time to
* send a single character, and make it at least 1. The check
* interval should also be less than the timeout.
- *
+ *
* Note: we have to use pretty tight timings here to satisfy
* the NIST-PCTS.
*/
{
ser_info_t *info = (ser_info_t *)tty->driver_data;
struct serial_state *state = info->state;
-
+
if (serial_paranoia_check(info, tty->name, "rs_hangup"))
return;
state = info->state;
-
+
rs_8xx_flush_buffer(tty);
shutdown(info);
info->event = 0;
state->line, state->count);
#endif
cli();
- if (!tty_hung_up_p(filp))
+ if (!tty_hung_up_p(filp))
state->count--;
sti();
info->blocked_open++;
if (info->flags & ASYNC_HUP_NOTIFY)
retval = -EAGAIN;
else
- retval = -ERESTARTSYS;
+ retval = -ERESTARTSYS;
#else
retval = -EAGAIN;
#endif
status = serial_in(info, UART_MSR);
control = info ? info->MCR : serial_in(info, UART_MCR);
sti();
-
+
stat_buf[0] = 0;
stat_buf[1] = 0;
if (control & UART_MCR_RTS)
if (state->icount.frame)
ret += sprintf(buf+ret, " fe:%d", state->icount.frame);
-
+
if (state->icount.parity)
ret += sprintf(buf+ret, " pe:%d", state->icount.parity);
-
+
if (state->icount.brk)
- ret += sprintf(buf+ret, " brk:%d", state->icount.brk);
+ ret += sprintf(buf+ret, " brk:%d", state->icount.brk);
if (state->icount.overrun)
ret += sprintf(buf+ret, " oe:%d", state->icount.overrun);
/* Get the address of the host memory buffer.
*/
bdp = bdbase = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
-
+
info = &consinfo;
}
else
cp = info->tx_va_base + ((bdp - info->tx_bd_base) * TX_BUF_SIZE);
*cp = *s;
-
+
bdp->cbd_datlen = 1;
bdp->cbd_sc |= BD_SC_READY;
unsigned count)
{
#ifdef CONFIG_KGDB_CONSOLE
- /* Try to let stub handle output. Returns true if it did. */
+ /* Try to let stub handle output. Returns true if it did. */
if (kgdb_output_string(s, count))
return;
#endif
serial_driver = alloc_tty_driver(NR_PORTS);
if (!serial_driver)
return -ENOMEM;
-
+
init_bh(SERIAL_BH, do_serial_bh);
show_serial_version();
/* Initialize the tty_driver structure */
-
+
serial_driver->driver_name = "serial";
serial_driver->devfs_name = "tts/";
serial_driver->name = "ttyS";
baud_idx | CS8 | CREAD | HUPCL | CLOCAL;
serial_driver->flags = TTY_DRIVER_REAL_RAW;
tty_set_operations(serial_driver, &rs_8xx_ops);
-
+
if (tty_register_driver(serial_driver))
panic("Couldn't register serial driver\n");
-
+
cp = cpmp; /* Get pointer to Communication Processor */
immap = (immap_t *)IMAP_ADDR; /* and to internal registers */
state->custom_divisor = 0;
state->close_delay = 5*HZ/10;
state->closing_wait = 30*HZ;
- state->icount.cts = state->icount.dsr =
+ state->icount.cts = state->icount.dsr =
state->icount.rng = state->icount.dcd = 0;
state->icount.rx = state->icount.tx = 0;
state->icount.frame = state->icount.parity = 0;
* Enable receive and transmit.
*/
scp->scc_gsmrh = 0;
- scp->scc_gsmrl =
+ scp->scc_gsmrl =
(SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
/* Disable all interrupts and clear all pending
* Enable receive and transmit.
*/
scp->scc_gsmrh = 0;
- scp->scc_gsmrl =
+ scp->scc_gsmrl =
(SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
/* Disable all interrupts and clear all pending
Embedded Planet RPX Lite. PC104 form-factor SBC based on the MPC823.
RPX-Classic:
- Embedded Planet RPX Classic Low-fat. Credit-card-size SBC based on
+ Embedded Planet RPX Classic Low-fat. Credit-card-size SBC based on
the MPC 860
- BSE-IP:
+ BSE-IP:
Bright Star Engineering ip-Engine.
TQM823L:
URL: <http://www.speech-design.de/>
IVML24:
- MPC860 based board used in the "Integrated Voice Mail System",
+ MPC860 based board used in the "Integrated Voice Mail System",
Large Version (24 voice channels)
Manufacturer: Speech Design, <http://www.speech-design.de/>
Date of Release: March 2001 (?)
End of life: -
URL: <http://www.multidata.de/english/products/hpro.htm>
- IP860:
+ IP860:
VMEBus IP (Industry Pack) carrier board with MPC860
Manufacturer: MicroSys GmbH, <http://www.microsys.de/>
Date of Release: ?
bool "Math emulation"
depends on 4xx || 8xx
---help---
- Some PowerPC chips designed for embedded applications do not have
+ Some PowerPC chips designed for embedded applications do not have
a floating-point unit and therefore do not implement the
floating-point instructions in the PowerPC instruction set. If you
say Y here, the kernel will include code to emulate a floating-point
help
This enables the /proc/cpufreq interface for controlling
CPUFreq. Please note that it is recommended to use the sysfs
- interface instead (which is built automatically).
-
- For details, take a look at linux/Documentation/cpufreq.
-
+ interface instead (which is built automatically).
+
+ For details, take a look at linux/Documentation/cpufreq.
+
If in doubt, say N.
config CPU_FREQ_24_API
help
This enables the /proc/sys/cpu/ sysctl interface for controlling
CPUFreq, as known from the 2.4.-kernel patches for CPUFreq. 2.5
- uses a sysfs interface instead. Please note that some drivers do
+ uses a sysfs interface instead. Please note that some drivers do
not work well with the 2.4. /proc/sys/cpu sysctl interface,
so if in doubt, say N here.
- For details, take a look at linux/Documentation/cpufreq.
+ For details, take a look at linux/Documentation/cpufreq.
If in doubt, say N.
depends on DEBUG_KERNEL
help
If you say Y here, various routines which may sleep will become very
- noisy if they are called with a spinlock held.
+ noisy if they are called with a spinlock held.
config KGDB
bool "Include kgdb kernel debugger"
bool
depends on IBM_OCP
default y
-
+
endmenu
source "security/Kconfig"
arch/$(ARCH)/kernel/asm-offsets.s: include/asm include/linux/version.h \
include/config/MARKER
-include/asm-$(ARCH)/offsets.h: arch/$(ARCH)/kernel/asm-offsets.s
+include/asm-$(ARCH)/offsets.h: arch/$(ARCH)/kernel/asm-offsets.s
$(call filechk,gen-asm-offsets)
ifdef CONFIG_6xx
case AMI_DRACO:
panic("No support for Draco yet");
-
+
default:
panic("Unknown Amiga Model");
}
volatile struct tod2000 *tod = TOD_2000;
tod->cntrl1 = TOD2000_CNTRL1_HOLD;
-
+
while (tod->cntrl1 & TOD2000_CNTRL1_BUSY)
;
tod->second2 = real_seconds % 10;
tod->minute1 = real_minutes / 10;
tod->minute2 = real_minutes % 10;
-
+
tod->cntrl1 = TOD3000_CNTRL1_FREE;
} else /* if (AMIGAHW_PRESENT(A2000_CLK)) */ {
volatile struct tod2000 *tod = TOD_2000;
tod->cntrl1 = TOD2000_CNTRL1_HOLD;
-
+
while (tod->cntrl1 & TOD2000_CNTRL1_BUSY)
;
mach_get_model(model);
else
strcpy(model, "Unknown PowerPC");
-
+
len += sprintf(buffer+len, "Model:\t\t%s\n", model);
len += get_cpuinfo(buffer+len);
for (mem = 0, i = 0; i < m68k_realnum_memory; i++)
return NULL;
}
-int sys_request_irq(unsigned int irq,
- void (*handler)(int, void *, struct pt_regs *),
+int sys_request_irq(unsigned int irq,
+ void (*handler)(int, void *, struct pt_regs *),
unsigned long flags, const char *devname, void *dev_id)
{
if (irq < IRQ1 || irq > IRQ7) {
## Flush and invalidate the caches for the range in memory covering
## the .text section of the boot loader
-
+
lis r9,_start@h # r9 = &_start
- lis r8,_etext@ha #
+ lis r8,_etext@ha #
addi r8,r8,_etext@l # r8 = &_etext
3: dcbf r0,r9 # Flush the data cache
icbi r0,r9 # Invalidate the instruction cache
lis r7,_end@ha
addi r7,r7,_end@l # r7 = &_end
- lis r8,__bss_start@ha #
+ lis r8,__bss_start@ha #
addi r8,r8,__bss_start@l # r8 = &_bss_start
## Determine how large an area, in number of words, to clear
-
- subf r7,r8,r7 # r7 = &_end - &_bss_start + 1
+
+ subf r7,r8,r7 # r7 = &_end - &_bss_start + 1
addi r7,r7,3 # r7 += 3
srwi. r7,r7,2 # r7 = size in words.
beq 2f # If the size is zero, do not bother
/*
* arch/ppc/boot/common/misc-common.c
- *
+ *
* Misc. bootloader code (almost) all platforms can use
*
* Author: Johnnie Peters <jpeters@mvista.com>
void exit(void)
{
puts("exit\n");
- while(1);
+ while(1);
}
int tstc(void)
}
}
-void
+void
putc(const char c)
{
int x,y;
x--;
}
} else {
- vidmem [ ( x + cols * y ) * 2 ] = c;
+ vidmem [ ( x + cols * y ) * 2 ] = c;
if ( ++x >= cols ) {
x = 0;
if ( ++y >= lines ) {
x--;
}
} else {
- vidmem [ ( x + cols * y ) * 2 ] = c;
+ vidmem [ ( x + cols * y ) * 2 ] = c;
if ( ++x >= cols ) {
x = 0;
if ( ++y >= lines ) {
void *zalloc(void *x, unsigned items, unsigned size)
{
void *p = avail_ram;
-
+
size *= items;
size = (size + 7) & -8;
avail_ram += size;
{
z_stream s;
int r, i, flags;
-
+
/* skip header */
i = 10;
flags = src[3];
puts("gunzip: ran out of data in header\n");
exit();
}
-
+
s.zalloc = zalloc;
s.zfree = zfree;
r = inflateInit2(&s, -MAX_WBITS);
/*
* arch/ppc/boot/common/mpc10x_common.c
- *
+ *
* A routine to find out how much memory the machine has.
*
* Based on:
/********************** AOUT "OPTIONAL HEADER" **********************/
-typedef struct
+typedef struct
{
unsigned char magic[2]; /* type of file */
unsigned char vstamp[2]; /* version stamp */
#define E_FILNMLEN 14 /* # characters in a file name */
#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */
-struct external_syment
+struct external_syment
{
union {
char e_name[E_SYMNMLEN];
#define N_TMASK (060)
#define N_BTSHFT (4)
#define N_TSHIFT (2)
-
+
union external_auxent {
struct {
};
#define SYMENT struct external_syment
-#define SYMESZ 18
+#define SYMESZ 18
#define AUXENT union external_auxent
#define AUXESZ 18
#define DBXMASK 0x80 /* for dbx storage mask */
/* zconf.h -- configuration of the zlib compression library
* Copyright (C) 1995 Jean-loup Gailly.
- * For conditions of distribution and use, see copyright notice in zlib.h
+ * For conditions of distribution and use, see copyright notice in zlib.h
*/
/* From: zconf.h,v 1.12 1995/05/03 17:27:12 jloup Exp */
#define ZLIB_VERSION "0.95P"
-/*
+/*
The 'zlib' compression library provides in-memory compression and
decompression functions, including integrity checks of the uncompressed
data. This version of the library supports only one compression method
/* basic functions */
extern int inflateInit OF((z_stream *strm));
-/*
+/*
Initializes the internal stream state for decompression. The fields
zalloc and zfree must be initialized before by the caller. If zalloc and
zfree are set to Z_NULL, inflateInit updates them to use default allocation
extern int inflateInit2 OF((z_stream *strm,
int windowBits));
-/*
+/*
This is another version of inflateInit with more compression options. The
fields next_out, zalloc and zfree must be initialized before by the caller.
*/
extern int inflateSync OF((z_stream *strm));
-/*
+/*
Skips invalid compressed data until the special marker (see deflate()
above) can be found, or until all available input is skipped. No output
is provided.
/* deflate.h -- internal compression state
* Copyright (C) 1995 Jean-loup Gailly
- * For conditions of distribution and use, see copyright notice in zlib.h
+ * For conditions of distribution and use, see copyright notice in zlib.h
*/
/* WARNING: this file should *not* be used by applications. It is
/*+++++*/
/* infblock.h -- header to use infblock.c
* Copyright (C) 1995 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
+ * For conditions of distribution and use, see copyright notice in zlib.h
*/
/* WARNING: this file should *not* be used by applications. It is
/*+++++*/
/* inftrees.h -- header to use inftrees.c
* Copyright (C) 1995 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
+ * For conditions of distribution and use, see copyright notice in zlib.h
*/
/* WARNING: this file should *not* be used by applications. It is
/*+++++*/
/* infcodes.h -- header to use infcodes.c
* Copyright (C) 1995 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
+ * For conditions of distribution and use, see copyright notice in zlib.h
*/
/* WARNING: this file should *not* be used by applications. It is
/*+++++*/
/* inflate.c -- zlib interface to inflate modules
* Copyright (C) 1995 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
+ * For conditions of distribution and use, see copyright notice in zlib.h
*/
/* inflate private state */
/* mode independent information */
int nowrap; /* flag for no wrapper */
uInt wbits; /* log2(window size) (8..15, defaults to 15) */
- inflate_blocks_statef
+ inflate_blocks_statef
*blocks; /* current inflate_blocks state */
};
int inflate(
z_stream *z,
- int f
+ int f
)
{
int r;
/*+++++*/
/* infutil.h -- types and macros common to blocks and codes
* Copyright (C) 1995 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
+ * For conditions of distribution and use, see copyright notice in zlib.h
*/
/* WARNING: this file should *not* be used by applications. It is
} trees; /* if DTREE, decoding info for trees */
struct {
inflate_huft *tl, *td; /* trees to free */
- inflate_codes_statef
+ inflate_codes_statef
*codes;
} decode; /* if CODES, current state */
} sub; /* submode */
/*+++++*/
/* inffast.h -- header to use inffast.c
* Copyright (C) 1995 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
+ * For conditions of distribution and use, see copyright notice in zlib.h
*/
/* WARNING: this file should *not* be used by applications. It is
/*+++++*/
/* infblock.c -- interpret and process block types to last block
* Copyright (C) 1995 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
+ * For conditions of distribution and use, see copyright notice in zlib.h
*/
/* Table for deflate from PKZIP's appnote.txt. */
/*+++++*/
/* inftrees.c -- generate Huffman trees for efficient decoding
* Copyright (C) 1995 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
+ * For conditions of distribution and use, see copyright notice in zlib.h
*/
/* simplify the use of the inflate_huft type with some defines */
q = (--p)->next;
ZFREE(z, p, p->word.Nalloc * sizeof(inflate_huft));
p = q;
- }
+ }
return Z_OK;
}
/*+++++*/
/* infcodes.c -- process literals and length/distance pairs
* Copyright (C) 1995 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
+ * For conditions of distribution and use, see copyright notice in zlib.h
*/
/* simplify the use of the inflate_huft type with some defines */
/*+++++*/
/* inflate_util.c -- data and routines common to blocks and codes
* Copyright (C) 1995 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
+ * For conditions of distribution and use, see copyright notice in zlib.h
*/
/* copy as much as possible from the sliding window to the output area */
/*+++++*/
/* inffast.c -- process literals and length/distance pairs fast
* Copyright (C) 1995 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
+ * For conditions of distribution and use, see copyright notice in zlib.h
*/
/* simplify the use of the inflate_huft type with some defines */
/*+++++*/
/* zutil.c -- target dependent utility functions for the compression library
* Copyright (C) 1995 Jean-loup Gailly.
- * For conditions of distribution and use, see copyright notice in zlib.h
+ * For conditions of distribution and use, see copyright notice in zlib.h
*/
/* From: zutil.c,v 1.8 1995/05/03 17:27:12 jloup Exp */
/*+++++*/
/* adler32.c -- compute the Adler-32 checksum of a data stream
* Copyright (C) 1995 Mark Adler
- * For conditions of distribution and use, see copyright notice in zlib.h
+ * For conditions of distribution and use, see copyright notice in zlib.h
*/
/* From: adler32.c,v 1.6 1995/05/03 17:27:08 jloup Exp */
-
/*
* Copyright (C) Paul Mackerras 1997.
* Copyright (C) Leigh Brown 2002.
int nargs;
int nret;
char *method;
- ihandle mmu_ihandle;
+ ihandle mmu_ihandle;
int misc;
unsigned int phys;
unsigned int virt;
phandle chosen;
of_prom_entry = prom_ptr;
-
+
if ((chosen = finddevice("/chosen")) == OF_INVALID_HANDLE)
return;
if (getprop(chosen, "mmu", &of_prom_mmu, sizeof(ihandle)) != 4)
{
ihandle in, out;
phandle chosen;
-
+
if ((chosen = finddevice("/chosen")) == OF_INVALID_HANDLE)
goto err;
if (getprop(chosen, "stdout", &out, sizeof(out)) != 4)
void *dst;
unsigned char *im;
unsigned int initrd_size, initrd_start;
-
+
printf("chrpboot starting: loaded at 0x%p\n\r", &_start);
initrd_size = &__ramdisk_end - &__ramdisk_begin;
flush_cache(dst, len);
make_bi_recs(((unsigned long) dst + len), "chrpboot", _MACH_chrp,
(PROG_START + PROG_SIZE));
-
+
sa = PROG_START;
printf("start address = 0x%x\n\r", sa);
void *dst;
unsigned char *im;
unsigned initrd_start, initrd_size;
-
+
printf("coffboot starting: loaded at 0x%p\n", &_start);
setup_bats(ram_start);
void *dst;
unsigned char *im;
unsigned initrd_start, initrd_size;
-
+
printf("chrpboot starting: loaded at 0x%p\n", &_start);
initrd_size = (char *)(&__ramdisk_end) - (char *)(&__ramdisk_begin);
LIBS := $(common)/lib.a $(bootlib)/lib.a
targets := $(boot-y) dummy.o ../simple/legacy.o
-OBJS := $(addprefix $(obj)/,$(boot-y)) $(simple)/legacy.o
+OBJS := $(addprefix $(obj)/,$(boot-y)) $(simple)/legacy.o
# Extra include search dirs
CFLAGS_kbd.o += -Idrivers/char
-zImage: initrd :=
+zImage: initrd :=
zImage: $(images)/zImage.prep
@echo ' kernel: $@ is ready ($<)'
OBJCOPY_ARGS := -O elf32-powerpc
# head.o and relocate.o must be at the start.
-boot-y := head.o relocate.o $(extra.o-y) $(misc-y)
+boot-y := head.o relocate.o $(extra.o-y) $(misc-y)
boot-$(CONFIG_40x) += embed_config.o
boot-$(CONFIG_8xx) += embed_config.o
boot-$(CONFIG_8260) += embed_config.o
/*
* arch/ppc/boot/simple/gt64260_tty.c
- *
+ *
* Bootloader version of the embedded MPSC/UART driver for the GT64260[A].
* Note: Due to 64260A errata, DMA will be used for UART input (via SDMA).
*
/*
* arch/ppc/boot/simple/misc-ev64260.S
- *
+ *
* Host bridge init code for the Marvell/Galileo EV-64260-BP evaluation board
* with a GT64260 onboard.
*
/* Relocate galileo's regs */
addis r25,0,GT64260_INTERNAL_SPACE_DEFAULT_ADDR@h
- ori r25,r25,GT64260_INTERNAL_SPACE_DECODE
+ ori r25,r25,GT64260_INTERNAL_SPACE_DECODE
lwbrx r26,0,(r25)
lis r24,0xffff
and r26,r26,r24
/* Change CS2 (UARTS on device module) window */
addis r25,0,EV64260_BRIDGE_REG_BASE@h
- ori r25,r25,GT64260_CPU_CS_DECODE_2_BOT
+ ori r25,r25,GT64260_CPU_CS_DECODE_2_BOT
addis r26,0,EV64260_UART_BASE@h
srw r26,r26,r23
stwbrx r26,0,(r25)
unsigned long rec_loc = _ALIGN((unsigned long)(zimage_size) +
(1 << 20) - 1, (1 << 20));
rec = (struct bi_record *)rec_loc;
-
+
/* We need to make sure that the initrd and bi_recs do not
* overlap. */
if ( initrd_size ) {
puts("\n");
}
}
-
+
rec->tag = BI_FIRST;
rec->size = sizeof(struct bi_record);
rec = (struct bi_record *)((unsigned long)rec + rec->size);
#include <asm/ppc_asm.h>
#define GETSYM(reg, sym) \
- lis reg, sym@h; ori reg, reg, sym@l
-
+ lis reg, sym@h; ori reg, reg, sym@l
+
.text
/* We get called from the early initialization code.
* Register 3 has the address where we were loaded,
cmp cr0,r3,r4
beq start_ldr /* If 0, we don't need to relocate */
- /* Move this code somewhere safe. This is max(load + size, end)
+ /* Move this code somewhere safe. This is max(load + size, end)
* r8 == load address
*/
GETSYM(r4, start)
cmpw r5,r6
bgt 1f
b 2f
-1:
- mr r6, r5
-2:
- /* dest is in r6 */
+1:
+ mr r6, r5
+2:
+ /* dest is in r6 */
/* Ensure alignment --- this code is precautionary */
addi r6,r6,4
li r5,0x0003
GETSYM(r3, start)
/* Size to copy */
- sub r4,r4,r5
+ sub r4,r4,r5
srwi r4,r4,2
-
+
/* Src addr to copy (= __relocate_start - start + where_loaded) */
sub r3,r5,r3
- add r5,r8,r3
+ add r5,r8,r3
/* Save dest */
mr r3, r6
- /* Do the copy */
- mtctr r4
+ /* Do the copy */
+ mtctr r4
3: lwz r4,0(r5)
- stw r4,0(r3)
+ stw r4,0(r3)
addi r3,r3,4
addi r5,r5,4
bdnz 3b
b flush_instruction_cache
.section ".relocate_code","xa"
-
-do_relocate:
- /* We have 2 cases --- start < load, or start > load
+
+do_relocate:
+ /* We have 2 cases --- start < load, or start > load
* This determines whether we copy from the end, or the start.
* Its easier to have 2 loops than to have paramaterised
* loops. Sigh.
*/
li r6,0 /* Clear checksum */
mtctr r7 /* Setup for a loop */
-
+
GETSYM(r4, start)
mr r3,r8 /* Get the load addr */
cmp cr0,r4,r3 /* If we need to copy from the end, do so */
bgt do_relocate_from_end
-
-do_relocate_from_start:
+
+do_relocate_from_start:
1: lwz r5,0(r3) /* Load and decrement */
stw r5,0(r4) /* Store and decrement */
addi r3,r3,4
bdnz 1b /* Are we done? */
b do_relocate_out /* Finished */
-do_relocate_from_end:
+do_relocate_from_end:
GETSYM(r3, end)
slwi r4,r7,2
add r4,r8,r4 /* Get the physical end */
xor r6,r6,r5
bdnz 1b
-do_relocate_out:
+do_relocate_out:
GETSYM(r3,start_ldr)
mtlr r3 /* Easiest way to do an absolute jump */
/* Some boards don't boot up with the I-cache enabled. Do that
b flush_instruction_cache
.previous
-
+
start_ldr:
/* Clear all of BSS and set up stack for C calls */
lis r3,edata@h
fwrite(buf, 1, 4096, file);
}
-void death(const char *msg, FILE *fdesc, const char *fname)
+void death(const char *msg, FILE *fdesc, const char *fname)
{
printf(msg);
fclose(fdesc);
round = actualKernelLen % 4096;
roundedKernelLen = actualKernelLen;
- if ( round )
+ if ( round )
roundedKernelLen += (4096 - round);
printf("actual kernel length rounded up to a 4k multiple = %d\n", roundedKernelLen);
fclose(inputVmlinux);
/* And flush the written output file */
fflush(outputVmlinux);
-
+
/* fseek to the hvReleaseData pointer */
fseek(outputVmlinux, ElfHeaderSize + 0x24, SEEK_SET);
if (fread(&hvReleaseData, 4, 1, outputVmlinux) != 1) {
}
hvReleaseData = ntohl(hvReleaseData); /* Convert to native int */
printf("hvReleaseData is at %08x\n", hvReleaseData);
-
+
/* fseek to the hvReleaseData */
fseek(outputVmlinux, ElfHeaderSize + hvReleaseData, SEEK_SET);
if (fread(inbuf, 0x40, 1, outputVmlinux) != 1) {
/* Check hvReleaseData sanity */
if (memcmp(inbuf, &eyeCatcher, 4) != 0) {
death("hvReleaseData is invalid\n", outputVmlinux, argv[3]);
- }
+ }
/* Get the naca pointer */
naca = ntohl(*((u_int32_t *) &inbuf[0x0c])) - KERNELBASE;
printf("naca is at %08x\n", naca);
-
+
/* fseek to the naca */
fseek(outputVmlinux, ElfHeaderSize + naca, SEEK_SET);
if (fread(inbuf, 0x18, 1, outputVmlinux) != 1) {
/* Fill in the values */
*((u_int32_t *) &inbuf[0x0c]) = htonl(ramStartOffs);
*((u_int32_t *) &inbuf[0x14]) = htonl(ramPages);
-
+
/* Write out the new naca */
fflush(outputVmlinux);
fseek(outputVmlinux, ElfHeaderSize + naca, SEEK_SET);
}
printf("RAM Disk of 0x%x pages size is attached to the kernel at offset 0x%08x\n",
ramPages, ramStartOffs);
-
+
/* Done */
fclose(outputVmlinux);
/* Set permission to executable */
chmod(argv[3], S_IRUSR|S_IWUSR|S_IXUSR|S_IRGRP|S_IXGRP|S_IROTH|S_IXOTH);
-
+
return 0;
}
round = actualKernelLen % 4096;
roundedKernelLen = actualKernelLen;
- if ( round )
+ if ( round )
roundedKernelLen += (4096 - round);
printf("actual kernel length rounded up to a 4k multiple = %ld\n", roundedKernelLen);
/*
* arch/ppc/pp3boot/mkbugboot.c
- *
- * Makes a Motorola PPCBUG ROM bootable image which can be flashed
- * into one of the FLASH banks on a Motorola PowerPlus board.
+ *
+ * Makes a Motorola PPCBUG ROM bootable image which can be flashed
+ * into one of the FLASH banks on a Motorola PowerPlus board.
*
* Author: Matt Porter <mporter@mvista.com>
*
{
uint8_t header_block[HEADER_SIZE];
bug_boot_header_t *bbh = (bug_boot_header_t *)&header_block[0];
-
+
bzero(header_block, HEADER_SIZE);
/* Fill in the PPCBUG ROM boot header */
}
/* Get file args */
-
+
/* kernel image file */
if ((image_fd = open( argv[argptr] , 0)) < 0)
exit(-1);
bugboot_fd = open(bugbootname, O_RDWR);
/* Calculate checksum */
- checksum = calc_checksum(bugboot_fd);
+ checksum = calc_checksum(bugboot_fd);
/* Write out the calculated checksum */
write(bugboot_fd, &checksum, 2);
}
/* needs to handle args more elegantly -- but this is a small/simple program */
-
+
/* check for -pbp */
if ( !strcmp( argv[argptr], "-pbp" ) )
{
prep = 1;
argptr++;
}
-
+
/* check for -asm */
if ( !strcmp( argv[argptr], "-asm" ) )
{
/* skip elf header in input file */
/*if ( !prep )*/
lseek(in_fd, elfhdr_size, SEEK_SET);
-
+
/* write prep partition if necessary */
if ( prep )
write_prep_partition( in_fd, out_fd );
write_asm_data( in_fd, out_fd );
else
copy_image(in_fd, out_fd);
-
+
return 0;
}
dword_t *entry = (dword_t *)&block[0];
dword_t *length = (dword_t *)&block[sizeof(long)];
struct stat info;
-
+
if (fstat(in, &info) < 0)
{
fprintf(stderr,"info failed\n");
exit(-1);
}
-
+
bzero( block, sizeof block );
-
+
/* set entry point and boot image size skipping over elf header */
#ifdef __i386__
*entry = 0x400/*+65536*/;
/* sets magic number for msdos partition (used by linux) */
block[510] = 0x55;
block[511] = 0xAA;
-
+
/*
* Build a "PReP" partition table entry in the boot record
* - "PReP" may only look at the system_indicator
#if 0
pe->beginning_sector = cpu_to_le32(1);
#else
- /* This has to be 0 on the PowerStack? */
+ /* This has to be 0 on the PowerStack? */
#ifdef __i386__
pe->beginning_sector = 0;
#else
pe->beginning_sector = cpu_to_le32(0);
#endif /* __i386__ */
-#endif
+#endif
#ifdef __i386__
pe->number_of_sectors = 2*18*80-1;
write( out, block, sizeof(block) );
write( out, entry, sizeof(*entry) );
- write( out, length, sizeof(*length) );
+ write( out, length, sizeof(*length) );
/* set file position to 2nd sector where image will be written */
lseek( out, 0x400, SEEK_SET );
}
unsigned char *lp;
unsigned char buf[SIZE];
unsigned char str[256];
-
+
write( out, "\t.data\n\t.globl input_data\ninput_data:\n",
strlen( "\t.data\n\t.globl input_data\ninput_data:\n" ) );
pos = 0;
cputable.o ppc_htab.o
obj-$(CONFIG_6xx) += l2cr.o cpu_setup_6xx.o
obj-$(CONFIG_MODULES) += module.o ppc_ksyms.o
-obj-$(CONFIG_PCI) += pci.o
+obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_PCI) += pci-dma.o
obj-$(CONFIG_KGDB) += ppc-stub.o
obj-$(CONFIG_SMP) += smp.o
32, 32,
__setup_cpu_750fx
},
-
+
{ /* 740/750 (L2CR bit need fixup for 740) */
0xffff0000, 0x00080000, "740/750",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
32, 32,
__setup_cpu_generic
},
-#endif /* CLASSIC_PPC */
+#endif /* CLASSIC_PPC */
#ifdef CONFIG_PPC64BRIDGE
{ /* Power3 */
0xffff0000, 0x00400000, "Power3 (630)",
128, 128,
__setup_cpu_power3
},
-#endif /* CONFIG_PPC64BRIDGE */
+#endif /* CONFIG_PPC64BRIDGE */
#ifdef CONFIG_8xx
{ /* 8xx */
0xffff0000, 0x00500000, "8xx",
/*
- * PowerPC version
+ * PowerPC version
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
* Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
* Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
- *
+ *
*/
#include <linux/config.h>
*
* The code which creates the new task context is in 'copy_thread'
* in arch/ppc/kernel/process.c
- */
+ */
_GLOBAL(_switch)
stwu r1,-INT_FRAME_SIZE(r1)
mflr r0
.comm ee_restarts,4
/*
- * PROM code for specific machines follows. Put it
+ * PROM code for specific machines follows. Put it
* here so it's easy to add arch-specific sections later.
* -- Cort
*/
/*
- * PowerPC version
+ * PowerPC version
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
* Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
mtspr DBAT##n##U,RA; \
mtspr DBAT##n##L,RB; \
1:
-#endif /* CONFIG_PPC64BRIDGE */
+#endif /* CONFIG_PPC64BRIDGE */
.text
.stabs "arch/ppc/kernel/",N_SO,0,0,0f
.text
.globl _start
_start:
- /*
+ /*
* These are here for legacy reasons, the kernel used to
* need to look like a coff function entry for the pmac
* but we're always started by some kind of bootloader now.
* early_init() does the early machine identification and does
* the necessary low-level setup and clears the BSS
* -- Cort <cort@fsmlabs.com>
- */
+ */
bl early_init
#ifdef CONFIG_APUS
-/* On APUS the __va/__pa constants need to be set to the correct
- * values before continuing.
+/* On APUS the __va/__pa constants need to be set to the correct
+ * values before continuing.
*/
mr r4,r30
bl fix_mem_constants
bl init_idle_6xx
#endif /* CONFIG_6xx */
-
+
#ifndef CONFIG_APUS
/*
* We need to run with _start at physical address 0.
/*
* Map the memory where the exception handlers will
- * be copied to when hash constants have been patched.
+ * be copied to when hash constants have been patched.
*/
#ifdef CONFIG_APUS_FAST_EXCEPT
lis r8,0xfff0
isync
blr
-/*
+/*
* An undocumented "feature" of 604e requires that the v bit
* be cleared before changing BAT values.
*
* Also, newer IBM firmware does not clear bat3 and 4 so
* this makes sure it's done.
- * -- Cort
+ * -- Cort
*/
clear_bats:
li r10,0
li r26,vector_label@l; \
mtspr SPRN_IVOR##vector_number,r26; \
sync
-
+
/* As with the other PowerPC ports, it is expected that when code
* execution begins here, the following registers contain valid, yet
* optional, information:
* r6 - Start of kernel command line string (e.g. "mem=128")
* r7 - End of kernel command line string
*
- */
+ */
.text
_GLOBAL(_stext)
_GLOBAL(_start)
oris r3,r3,PPC44x_MMUCR_STS@h /* Set STS=1 */
wmmucr: mtspr SPRN_MMUCR,r3 /* Put MMUCR */
sync
-
+
bl invstr /* Find our address */
invstr: mflr r5 /* Make it accessible */
tlbsx r23,0,r5 /* Find entry we are in */
* are used for polled operation.
*/
/* pageid fields */
- lis r3,0xe000
+ lis r3,0xe000
ori r3,r3,(PPC44x_TLB_VALID | PPC44x_TLB_PAGESZ(PPC44x_PAGESZ_256M))
/* xlat fields */
/*
* This is where the main kernel code starts.
- */
+ */
/* ptr to current */
lis r2,init_task@h
* this case we handle interrupts in the kernel virtual address
* space.
*
- * Interrupt vectors are dynamically placed relative to the
+ * Interrupt vectors are dynamically placed relative to the
* interrupt prefix as determined by the address of interrupt_base.
* The interrupt vectors offsets are programmed using the labels
* for each interrupt vector entry.
rlwimi r12, r10, 23, 20, 28 /* Compute pte address */
lwz r11, 4(r12) /* Get pte entry */
-
+
andi. r13, r11, _PAGE_RW /* Is it writeable? */
beq 2f /* Bail if not */
ori r13, r13, tlb_44x_hwater@l
lwz r11, 0(r13)
-
+
/* Increment, rollover, and store TLB index */
addi r14, r14, 1
cmpw 0, r14, r11 /* reserve entries 62-63 for kernel */
* extern void abort(void)
*
* At present, this routine just applies a system reset.
- */
+ */
_GLOBAL(abort)
mfspr r13,SPRN_DBCR0
oris r13,r13,DBCR_RST(DBCR_RST_SYSTEM)@h
* r7 - End of kernel command line string
*
* This is all going to change RSN when we add bi_recs....... -- Dan
- */
+ */
.text
_GLOBAL(_stext)
_GLOBAL(_start)
* Note that we have to have decremented r1 before we write to any fields
* of the exception frame, since a critical interrupt could occur at any
* time, and it will write to the area immediately below the current r1.
- */
+ */
#define NORMAL_EXCEPTION_PROLOG \
mtspr SPRN_SPRG0,r10; /* save two registers to work with */\
mtspr SPRN_SPRG1,r11; \
mr r11, r12
b finish_tlb_load
-
+
5:
/* The bailout. Restore registers to pre-exception conditions
* and call the heavyweights to help us out.
* have vectors from 0x2100 through 0x2F00 defined, but marked as reserved.
* However, for the 4xx-series processors these are neither defined nor
* reserved.
- */
+ */
/* Damn, I came up one instruction too many to fit into the
* exception space :-). Both the instruction and data TLB
blr
/* This is where the main kernel code starts.
- */
+ */
start_here:
/* ptr to current */
*/
initial_mmu:
tlbia /* Invalidate all TLB entries */
- isync
+ isync
/* We should still be executing code at physical address 0x0000xxxx
* at this point. However, start_here is at virtual address
tlbwe r3,r0,TLB_TAG /* Load the tag portion of the entry */
#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(SERIAL_DEBUG_IO_BASE)
-
+
/* Load a TLB entry for the UART, so that ppc4xx_progress() can use
* the UARTs nice and early. We use a 4k real==virtual mapping. */
_GLOBAL(swapper_pg_dir)
.space 4096
-
+
/* Stack for handling critical exceptions from kernel mode */
.section .bss
critical_stack_bottom:
/*
* arch/ppc/kernel/except_8xx.S
*
- * PowerPC version
+ * PowerPC version
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
* Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
- *
+ *
*/
#include <linux/config.h>
* and the CCR at memory location 0.....Someday I'll fix this.....
* -- Dan
*/
-
+
.globl __start
__start:
mr r31,r3 /* save parameters */
STD_EXCEPTION(0x100, Reset, __secondary_start_psurge)
#else
STD_EXCEPTION(0x100, Reset, UnknownException)
-#endif
+#endif
/* Machine check */
STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
do_IRQ_intercept:
.long do_IRQ;
.long ret_from_intercept
-
+
/* Alignment exception */
. = 0x600
andis. r21, r20, 0x0200 /* If set, indicates store op */
beq 2f
- /* The EA of a data TLB miss is automatically stored in the MD_EPN
- * register. The EA of a data TLB error is automatically stored in
- * the DAR, but not the MD_EPN register. We must copy the 20 most
- * significant bits of the EA from the DAR to MD_EPN before we
- * start walking the page tables. We also need to copy the CASID
+ /* The EA of a data TLB miss is automatically stored in the MD_EPN
+ * register. The EA of a data TLB error is automatically stored in
+ * the DAR, but not the MD_EPN register. We must copy the 20 most
+ * significant bits of the EA from the DAR to MD_EPN before we
+ * start walking the page tables. We also need to copy the CASID
* value from the M_CASID register.
- * Addendum: The EA of a data TLB error is _supposed_ to be stored
- * in DAR, but it seems that this doesn't happen in some cases, such
- * as when the error is due to a dcbi instruction to a page with a
- * TLB that doesn't have the changed bit set. In such cases, there
- * does not appear to be any way to recover the EA of the error
- * since it is neither in DAR nor MD_EPN. As a workaround, the
- * _PAGE_HWWRITE bit is set for all kernel data pages when the PTEs
- * are initialized in mapin_ram(). This will avoid the problem,
+ * Addendum: The EA of a data TLB error is _supposed_ to be stored
+ * in DAR, but it seems that this doesn't happen in some cases, such
+ * as when the error is due to a dcbi instruction to a page with a
+ * TLB that doesn't have the changed bit set. In such cases, there
+ * does not appear to be any way to recover the EA of the error
+ * since it is neither in DAR nor MD_EPN. As a workaround, the
+ * _PAGE_HWWRITE bit is set for all kernel data pages when the PTEs
+ * are initialized in mapin_ram(). This will avoid the problem,
* assuming we only use the dcbi instruction on kernel addresses.
*/
mfspr r20, DAR
SYNC
blr
#endif
-
+
/*
* We put a few things here that have to be page-aligned.
* This stuff goes at the beginning of the data segment,
.globl swapper_pg_dir
swapper_pg_dir:
- .space 4096
+ .space 4096
/*
* This space gets a copy of optional info passed to us by the bootstrap
* Used to pass parameters into the kernel like root=/dev/sda1, etc.
- */
+ */
.globl cmd_line
cmd_line:
.space 512
ppc_md.idle();
else
default_idle();
- return 0;
+ return 0;
}
* Adapted for Power Macintosh by Paul Mackerras
* Copyright (C) 1996 Paul Mackerras (paulus@cs.anu.edu.au)
* Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
- *
+ *
* This file contains the code used by various IRQ handling routines:
* asking for different IRQ's should be done through these routines
* instead of just grabbing them. Thus setups with different IRQ numbers
.lock = SPIN_LOCK_UNLOCKED
}
};
-
+
int ppc_spurious_interrupts = 0;
struct irqaction *ppc_irq_action[NR_IRQS];
unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
dump_stack();
return 0;
}
-
+
action = (struct irqaction *)
irq_kmalloc(sizeof(struct irqaction), GFP_KERNEL);
if (!action) {
printk(KERN_ERR "irq_kmalloc() failed for irq %d !\n", irq);
return -ENOMEM;
}
-
+
action->handler = handler;
- action->flags = irqflags;
+ action->flags = irqflags;
action->mask = 0;
action->name = devname;
action->dev_id = dev_id;
action->next = NULL;
-
+
retval = setup_irq(irq, action);
if (retval) {
kfree(action);
return retval;
}
-
+
return 0;
}
* Generic enable/disable code: this just calls
* down into the PIC-specific version for the actual
* hardware disable after having gotten the irq
- * controller lock.
+ * controller lock.
*/
-
+
/**
* disable_irq_nosync - disable an irq without waiting
* @irq: Interrupt to disable
*
* This function may be called - with care - from IRQ context.
*/
-
+
void disable_irq(unsigned int irq)
{
disable_irq_nosync(irq);
*
* This function may be called from IRQ context.
*/
-
+
void enable_irq(unsigned int irq)
{
irq_desc_t *desc = irq_desc + irq;
action = irq_desc[i].action;
if ( !action || !action->handler )
goto skip;
- seq_printf(p, "%3d: ", i);
+ seq_printf(p, "%3d: ", i);
#ifdef CONFIG_SMP
for (j = 0; j < NR_CPUS; j++)
if (cpu_online(j))
seq_printf(p, "%10u ",
kstat_cpu(j).irqs[i]);
-#else
+#else
seq_printf(p, "%10u ", kstat_irqs(i));
#endif /* CONFIG_SMP */
- if (irq_desc[i].handler)
+ if (irq_desc[i].handler)
seq_printf(p, " %s ", irq_desc[i].handler->typename);
else
seq_puts(p, " None ");
/* should this be per processor send/receive? */
seq_printf(p, "IPI (recv/sent): %10u/%u\n",
atomic_read(&ipi_recv), atomic_read(&ipi_sent));
-#endif
+#endif
seq_printf(p, "BAD: %10u\n", ppc_spurious_interrupts);
return 0;
}
kstat_this_cpu.irqs[irq]++;
spin_lock(&desc->lock);
- ack_irq(irq);
+ ack_irq(irq);
/*
REPLAY is when Linux resends an IRQ that was dropped earlier
WAITING is used by probe to mark irqs that are being tested
spin_unlock(&desc->lock);
handle_irq_event(irq, regs, action);
spin_lock(&desc->lock);
-
+
if (likely(!(desc->status & IRQ_PENDING)))
break;
desc->status &= ~IRQ_PENDING;
/*
L2CR functions
Copyright © 1997-1998 by PowerLogix R & D, Inc.
-
+
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
-
+
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
-
+
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
several months. The L2CR is similar, but I'm going
to assume the user of this functions knows what they
are doing.
-
+
Author: Terry Greeniaus (tgree@phys.ualberta.ca)
Please e-mail updates to this file to me, thanks!
*/
#include <asm/cache.h>
/* Usage:
-
+
When setting the L2CR register, you must do a few special
things. If you are enabling the cache, you must perform a
global invalidate. If you are disabling the cache, you must
END_FTR_SECTION_IFCLR(CPU_FTR_L2CR)
mflr r9
-
+
/* Stop DST streams */
BEGIN_FTR_SECTION
DSSALL
mr r5,r3
bl __flush_disable_L1
mr r3,r5
-
+
/* Get the current enable bit of the L2CR into r4 */
mfspr r4,L2CR
-
+
/* Tweak some bits */
rlwinm r5,r3,0,0,0 /* r5 contains the new enable bit */
rlwinm r3,r3,0,11,9 /* Turn off the invalidate bit */
* the size of the L2 cache plus the size of the L1 cache, but 4MB will
* cover everything just to be safe).
*/
-
+
/**** Might be a good idea to set L2DO here - to prevent instructions
from getting into the cache. But since we invalidate
the next time we enable the cache it doesn't really matter.
addi r4,r4,32 /* Go to start of next cache line */
bdnz 1b
isync
-
+
/* Now, flush the first 4MB of memory */
lis r4,0x0002
mtctr r4
21: sync
isync
b 22b
-
+
23:
/* Perform a global invalidation */
oris r3,r3,0x0020
3: mfspr r3,L2CR
rlwinm. r4,r3,0,31,31
bne 3b
-
+
11: rlwinm r3,r3,0,11,9 /* Turn off the L2I bit */
sync
mtspr L2CR,r3
sync
-
+
/* See if we need to enable the cache */
cmplwi r5,0
beq 4f
* Here is a similar routine for dealing with the L3 cache
* on the 745x family of chips
*/
-
+
_GLOBAL(_set_L3CR)
/* Make sure this is a 745x chip */
BEGIN_FTR_SECTION
/* Stop DST streams */
DSSALL
sync
-
+
/* Get the current enable bit of the L3CR into r4 */
mfspr r4,SPRN_L3CR
-
+
/* Tweak some bits */
rlwinm r5,r3,0,0,0 /* r5 contains the new enable bit */
rlwinm r3,r3,0,22,20 /* Turn off the invalidate bit */
/* Flush the cache.
*/
-
+
/* TODO: use HW flush assist */
lis r4,0x0008
dcbf 0,r4
addi r4,r4,32 /* Go to start of next cache line */
bdnz 1b
-
+
2:
/* Set up the L3CR configuration bits (and switch L3 off) */
sync
li r0,256
mtctr r0
1: bdnz 1b
-
+
/* Perform a global invalidation */
ori r3,r3,0x0400
sync
li r0,256
mtctr r0
1: bdnz 1b
-
+
/* See if we need to enable the cache */
cmplwi r5,0
beq 4f
*/
.globl __flush_disable_L1
__flush_disable_L1:
-
+
/* Stop pending alitvec streams and memory accesses */
BEGIN_FTR_SECTION
DSSALL
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
sync
-
+
/* Load counter to 0x1000 cache lines (128k) and
* load cache with datas
*/
rlwinm r3,r3,0,18,15
mtspr SPRN_HID0,r3
sync
- isync
+ isync
blr
/* inval_enable_L1 - Invalidate and enable L1 cache
blr
-
+
mtspr HID0,r5
isync
sync
-
+
1:
/* Calc new HID1 value */
mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
mtspr HID0,r5
isync
sync
-
-1:
- /* Return */
+
+1:
+ /* Return */
mtmsr r7
blr
mfmsr r4
stw r4,0(r3)
blr
- /*
+ /*
* Need these nops here for taking over save/restore to
* handle lost intrs
* -- Cort
nop
_GLOBAL(local_save_flags_ptr_end)
-/* void local_irq_restore(unsigned long flags) */
+/* void local_irq_restore(unsigned long flags) */
_GLOBAL(local_irq_restore)
/*
* Just set/clear the MSR_EE bit through restore/flags but do not
SYNC /* Some chip revs have problems here... */
mtmsr r0 /* Update machine state */
blr /* Done */
- /*
+ /*
* Need these nops here for taking over save/restore to
* handle lost intrs
* -- Cort
SYNC /* Some chip revs have problems here... */
mtmsr r3 /* Update machine state */
blr
- /*
+ /*
* Need these nops here for taking over save/restore to
* handle lost intrs
* -- Cort
sync
#endif /* CONFIG_SMP */
#endif /* ! defined(CONFIG_40x) */
- blr
+ blr
/*
* Flush MMU TLB for a particular address
li r3, 512
mtctr r3
lis r4, KERNELBASE@h
-1: iccci 0, r4
+1: iccci 0, r4
addi r4, r4, 16
bdnz 1b
#else
mtmsr r10 /* restore DR */
isync
blr
-
+
/*
* Clear a page using the dcbz instruction, which doesn't cause any
* memory traffic (except to write out any cache lines which get
stb r5,0(r3)
eieio
bdnz 00b
- blr
+ blr
_GLOBAL(_insw)
cmpwi 0,r5,0
blelr-
00: lhzu r5,2(r4)
eieio
- sthbrx r5,0,r3
+ sthbrx r5,0,r3
bdnz 00b
- blr
+ blr
_GLOBAL(_insl)
cmpwi 0,r5,0
stwbrx r5,0,r3
eieio
bdnz 00b
- blr
+ blr
_GLOBAL(__ide_mm_insw)
_GLOBAL(_insw_ns)
sth r5,0(r3)
eieio
bdnz 00b
- blr
+ blr
_GLOBAL(__ide_mm_insl)
_GLOBAL(_insl_ns)
stw r5,0(r3)
eieio
bdnz 00b
- blr
+ blr
/*
* Extended precision shifts.
- *
+ *
* Updated to be valid for shift counts from 0 to 63 inclusive.
* -- Gabriel
*
* R5 has shift count
* result in R3/R4
*
- * ashrdi3: arithmetic right shift (sign propagation)
- * lshrdi3: logical right shift
+ * ashrdi3: arithmetic right shift (sign propagation)
+ * lshrdi3: logical right shift
* ashldi3: left shift
*/
_GLOBAL(__ashrdi3)
- subfic r6,r5,32
+ subfic r6,r5,32
srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
addi r7,r5,32 # could be xori, or addi with -32
slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
blr
_GLOBAL(__ashldi3)
- subfic r6,r5,32
+ subfic r6,r5,32
slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
addi r7,r5,32 # could be xori, or addi with -32
srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
blr
_GLOBAL(__lshrdi3)
- subfic r6,r5,32
+ subfic r6,r5,32
srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
addi r7,r5,32 # could be xori, or addi with -32
slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
or r4,r4,r6 # LSW |= t1
srw r3,r3,r5 # MSW = MSW >> count
- or r4,r4,r7 # LSW |= t2
+ or r4,r4,r7 # LSW |= t2
blr
_GLOBAL(abs)
_GLOBAL(_get_SP)
mr r3,r1 /* Close enough */
blr
-
+
/*
* These are used in the alignment trap handler when emulating
* single-precision loads and stores.
/*
* This routine is just here to keep GCC happy - sigh...
- */
+ */
_GLOBAL(__main)
blr
SYSCALL(execve)
SYSCALL(waitpid)
-/* Why isn't this a) automatic, b) written in 'C'? */
+/* Why isn't this a) automatic, b) written in 'C'? */
.data
.align 4
_GLOBAL(sys_call_table)
.long sys_prctl
.long sys_rt_sigreturn
.long sys_rt_sigaction
- .long sys_rt_sigprocmask
+ .long sys_rt_sigprocmask
.long sys_rt_sigpending /* 175 */
.long sys_rt_sigtimedwait
.long sys_rt_sigqueueinfo
.long ppc_vfork
.long sys_getrlimit /* 190 */
.long sys_readahead
- .long sys_mmap2
+ .long sys_mmap2
.long sys_truncate64
.long sys_ftruncate64
.long sys_stat64 /* 195 */
.long sys_lstat64
.long sys_fstat64
.long sys_pciconfig_read
- .long sys_pciconfig_write
+ .long sys_pciconfig_write
.long sys_pciconfig_iobase /* 200 */
.long sys_ni_syscall /* 201 - reserved - MacOnLinux - new */
.long sys_getdents64
/* Set up a trampoline in the PLT to bounce us to the distant function */
static uint32_t do_plt_call(void *location,
- Elf32_Addr val,
+ Elf32_Addr val,
Elf32_Shdr *sechdrs,
struct module *mod)
{
/* Low half of the symbol */
*(uint16_t *)location = value;
break;
-
+
case R_PPC_ADDR16_HA:
/* Sign-adjusted lower 16 bits: PPC ELF ABI says:
(((x >> 16) + ((x & 0x8000) ? 1 : 0))) & 0xFFFF.
value, (uint32_t)location);
DEBUGP("Location before: %08X.\n",
*(uint32_t *)location);
- *(uint32_t *)location
+ *(uint32_t *)location
= (*(uint32_t *)location & ~0x03fffffc)
| ((value - (uint32_t)location)
& 0x03fffffc);
{ PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources },
#ifdef CONFIG_PPC_PMAC
/* We should add per-machine fixup support in xxx_setup.c or xxx_pci.c */
- { PCI_FIXUP_FINAL, PCI_VENDOR_ID_TI, PCI_ANY_ID, pcibios_fixup_cardbus },
+ { PCI_FIXUP_FINAL, PCI_VENDOR_ID_TI, PCI_ANY_ID, pcibios_fixup_cardbus },
#endif /* CONFIG_PPC_PMAC */
{ 0 }
};
/* Enable PCI interrupt */
if (pci_read_config_byte(dev, 0x91, &val) == 0)
pci_write_config_byte(dev, 0x91, val | 0x30);
- /* Disable ISA interrupt mode */
+ /* Disable ISA interrupt mode */
if (pci_read_config_byte(dev, 0x92, &val) == 0)
pci_write_config_byte(dev, 0x92, val & ~0x06);
}
signal out the MFUNC0 pin */
if (pci_read_config_byte(dev, 0x8c, &val) == 0)
pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2);
- /* Disable ISA interrupt mode */
+ /* Disable ISA interrupt mode */
if (pci_read_config_byte(dev, 0x92, &val) == 0)
pci_write_config_byte(dev, 0x92, val & ~0x06);
}
/* Only set up the requested stuff */
if (!(mask & (1<<idx)))
continue;
-
+
r = &dev->resource[idx];
if (r->flags & IORESOURCE_UNSET) {
printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
hose = (struct pci_controller *)alloc_bootmem(sizeof(*hose));
memset(hose, 0, sizeof(struct pci_controller));
-
+
*hose_tail = hose;
hose_tail = &hose->next;
{
int *bus_range;
int len;
-
+
if (pci_bus >= pci_bus_count)
return;
bus_range = (int *) get_property(node, "bus-range", &len);
return;
}
pci_to_OF_bus_map[pci_bus] = bus_range[0];
-
+
for (node=node->child; node != 0;node = node->sibling) {
struct pci_dev* dev;
unsigned int *class_code, *reg;
-
+
class_code = (unsigned int *) get_property(node, "class-code", 0);
if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
(*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
make_one_node_map(node, dev->subordinate->number);
}
}
-
+
void __openfirmware
pcibios_make_OF_bus_map(void)
{
int i;
struct pci_controller* hose;
u8* of_prop_map;
-
+
pci_to_OF_bus_map = (u8*)kmalloc(pci_bus_count, GFP_KERNEL);
if (!pci_to_OF_bus_map) {
printk(KERN_ERR "Can't allocate OF bus map !\n");
return;
}
-
+
/* We fill the bus map with invalid values, that helps
* debugging.
*/
for (i=0; i<pci_bus_count; i++)
pci_to_OF_bus_map[i] = 0xff;
-
+
/* For each hose, we begin searching bridges */
for(hose=hose_head; hose; hose=hose->next) {
- struct device_node* node;
+ struct device_node* node;
node = (struct device_node *)hose->arch_data;
if (!node)
continue;
continue;
printk("%d -> %d\n", i, pci_to_OF_bus_map[i]);
}
-#endif
+#endif
}
typedef int (*pci_OF_scan_iterator)(struct device_node* node, void* data);
scan_OF_pci_childs(struct device_node* node, pci_OF_scan_iterator filter, void* data)
{
struct device_node* sub_node;
-
+
for (; node != 0;node = node->sibling) {
unsigned int *class_code;
-
+
if (filter(node, data))
return node;
{
unsigned int *reg;
u8* fdata = (u8*)data;
-
+
reg = (unsigned int *) get_property(node, "reg", 0);
if (reg && ((reg[0] >> 8) & 0xff) == fdata[1]
&& ((reg[0] >> 16) & 0xff) == fdata[0])
return scan_OF_pci_childs(node, scan_OF_pci_childs_iterator, filter_data);
}
-/*
+/*
* Scans the OF tree for a device node matching a PCI device
*/
struct device_node *
struct pci_controller *hose;
struct device_node *node;
int busnr;
-
+
if (!have_of)
return NULL;
-
+
/* Lookup the hose */
busnr = bus->number;
hose = pci_bus_to_hose(busnr);
busnr = pci_to_OF_bus_map[busnr];
if (busnr == 0xff)
return NULL;
-
+
/* Now, lookup childs of the hose */
return scan_OF_childs_for_device(node->child, busnr, devfn);
}
return ((void *)node == data);
}
-/*
+/*
* Returns the PCI device matching a given OF node
*/
int
unsigned int *reg;
struct pci_controller* hose;
struct pci_dev* dev = NULL;
-
+
if (!have_of)
return -ENODEV;
/* Make sure it's really a PCI device */
pci_create_OF_bus_map(void)
{
struct property* of_prop;
-
+
of_prop = (struct property*) alloc_bootmem(sizeof(struct property) + 256);
if (of_prop && find_path_device("/")) {
memset(of_prop, -1, sizeof(struct property) + 256);
/*
* This set of routines checks for PCI<->PCI bridges that have closed
* IO resources and have child devices. It tries to re-open an IO
- * window on them.
- *
+ * window on them.
+ *
* This is a _temporary_ fix to workaround a problem with Apple's OF
* closing IO windows on P2P bridges when the OF drivers of cards
* below this bridge don't claim any IO range (typically ATI or
* Adaptec).
- *
+ *
* A more complete fix would be to use drivers/pci/setup-bus.c, which
* involves a working pcibios_fixup_pbus_ranges(), some more care about
* ordering when creating the host bus resources, and maybe a few more
u32 l;
u16 w;
struct resource res;
-
+
res = *(bus->resource[0]);
DBG("Remapping Bus %d, bridge: %s\n", bus->number, bridge->name);
break;
if (parent_io >= 4)
return;
-
+
for (ln=bus->children.next; ln != &bus->children; ln=ln->next) {
struct pci_bus *b = pci_bus_b(ln);
struct pci_dev *d = b->self;
*/
if (tmp_res.start == 0)
tmp_res.start = 0x1000;
-
+
if (!list_empty(&b->devices) && res && res->flags == 0 &&
res != bus->resource[parent_io] &&
(d->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
*res = tmp_res;
res->flags = IORESOURCE_IO;
res->name = b->name;
-
+
/* Find a resource in the parent where we can allocate */
for (i = 0 ; i < 4; i++) {
struct resource *r = bus->resource[i];
DBG("Trying to allocate from %08lx, size %08lx from parent"
" res %d: %08lx -> %08lx\n",
res->start, res->end, i, r->start, r->end);
-
+
if (allocate_resource(r, res, res->end + 1, res->start, max,
res->end + 1, NULL, NULL) < 0) {
DBG("Failed !\n");
if (ppc_md.pcibios_enable_device_hook)
if (ppc_md.pcibios_enable_device_hook(dev, 0))
return -EINVAL;
-
+
pci_read_config_word(dev, PCI_COMMAND, &cmd);
old_cmd = cmd;
for (idx=0; idx<6; idx++) {
if (!hose)
return -ENODEV;
-
+
switch (which) {
case IOBASE_BRIDGE_NUMBER:
return (long)hose->first_busno;
default:
return "unknown";
}
-}
+}
static char *pmc2_lookup(unsigned long mmcr0)
{
default:
return "unknown";
}
-}
+}
/*
* print some useful info about the hash table. This function
else
uptes++;
}
-
+
n += sprintf( buffer + n,
"PTE Hash Table Information\n"
"Size\t\t: %luKb\n"
if (cur_cpu_spec[0]->cpu_features & CPU_FTR_604_PERF_MON) {
asm volatile ("mtspr %0, %3 \n\t"
"mtspr %1, %3 \n\t"
- "mtspr %2, %3 \n\t"
+ "mtspr %2, %3 \n\t"
:: "i" (MMCR0), "i" (PMC1), "i" (PMC2), "r" (0));
}
}
"i" (PMC1), "r" (0), "i"(PMC2) );
}
}
-
+
/* PMC1 values */
if ( !strncmp( buffer, "dtlb", 4) )
{
:: "r" (tmp), "i" (MMCR0), "i" (MMCR0_PMC1_DTLB),
"i" (PMC1), "r" (0) );
}
- }
+ }
if ( !strncmp( buffer, "ic miss", 7) )
{
:: "r" (tmp), "i" (MMCR0),
"i" (MMCR0_PMC1_ICACHEMISS), "i" (PMC1), "r" (0));
}
- }
+ }
/* PMC2 values */
if ( !strncmp( buffer, "load miss time", 14) )
"i" (PMC2), "r" (0) );
}
}
-
+
if ( !strncmp( buffer, "itlb", 4) )
{
if (cur_cpu_spec[0]->cpu_features & CPU_FTR_604_PERF_MON) {
: "i" (MMCR0), "i" (MMCR0_PMC2_DCACHEMISS),
"i" (PMC2), "r" (0) );
}
- }
-
+ }
+
return count;
#else /* CONFIG_PPC_STD_MMU */
return 0;
if (!(cur_cpu_spec[0]->cpu_features & CPU_FTR_L2CR))
return -EFAULT;
-
+
if ( /*!table->maxlen ||*/ (filp->f_pos && !write)) {
*lenp = 0;
return 0;
}
-
+
vleft = table->maxlen / sizeof(int);
left = *lenp;
p += sprintf(p, "%s", (val>>15)&1 ? ", DLL slow" : "");
p += sprintf(p, "%s", (val>>14)&1 ? ", diff clock" :"");
p += sprintf(p, "%s", (val>>13)&1 ? ", DLL bypass" :"");
-
+
p += sprintf(p,"\n");
-
+
len = strlen(buf);
if (len > left)
len = left;
* Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
* Paul Mackerras (paulus@cs.anu.edu.au)
*
- * PowerPC version
+ * PowerPC version
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
* This program is free software; you can redistribute it and/or
unsigned long tsk_top = task_top(tsk);
int ret = 0;
-#if 0
+#if 0
/* check thread magic */
if ( tsk->thread.magic != THREAD_MAGIC )
{
if ( !tsk )
printk("check_stack(): tsk bad tsk %p\n",tsk);
-
+
/* check if stored ksp is bad */
if ( (tsk->thread.ksp > stack_top) || (tsk->thread.ksp < tsk_top) )
{
tsk_top, tsk->thread.ksp, stack_top);
ret |= 2;
}
-
+
/* check if stack ptr RIGHT NOW is bad */
if ( (tsk == current) && ((_get_SP() > stack_top ) || (_get_SP() < tsk_top)) )
{
ret |= 4;
}
-#if 0
+#if 0
/* check amount of free stack */
for ( i = (unsigned long *)task_top(tsk) ; i < kernel_stack_top(tsk) ; i++ )
{
return 1;
}
-void
+void
enable_kernel_altivec(void)
{
#ifdef CONFIG_SMP
struct thread_struct *new_thread, *old_thread;
unsigned long s;
struct task_struct *last;
-
+
local_irq_save(s);
#ifdef CHECK_STACK
check_stack(prev);
/* avoid complexity of lazy save/restore of fpu
* by just saving it every time we switch out if
* this task used the fpu during the last quantum.
- *
+ *
* If it tries to use the fpu again, it'll trap and
* reload its fp regs. So we don't have to do a restore
* every switch, just a save.
*/
if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP))
giveup_fpu(prev);
-#ifdef CONFIG_ALTIVEC
+#ifdef CONFIG_ALTIVEC
/*
* If the previous thread used altivec in the last quantum
* (thus changing altivec regs) then save them.
*/
if ((prev->thread.regs && (prev->thread.regs->msr & MSR_VEC)))
giveup_altivec(prev);
-#endif /* CONFIG_ALTIVEC */
+#endif /* CONFIG_ALTIVEC */
#endif /* CONFIG_SMP */
/* Avoid the trap. On smp this this never happens since
mfdcr(DCRN_POB0_BEAR), mfdcr(DCRN_POB0_BESR0),
mfdcr(DCRN_POB0_BESR1));
#endif
-
+
#ifdef CONFIG_SMP
printk(" CPU: %d", smp_processor_id());
#endif /* CONFIG_SMP */
#ifdef CONFIG_ALTIVEC
if (regs->msr & MSR_VEC)
giveup_altivec(current);
-#endif /* CONFIG_ALTIVEC */
+#endif /* CONFIG_ALTIVEC */
error = do_execve(filename, (char __user *__user *) a1,
(char __user *__user *) a2, regs);
if (error == 0)
return;
}
-#if 0
+#if 0
if ( have_of )
{
prom_print(s);
y = 0;
}
} else {
- vidmem [ ( x + cols * y ) * 2 ] = c;
+ vidmem [ ( x + cols * y ) * 2 ] = c;
if ( ++x >= cols ) {
x = 0;
if ( ++y >= lines ) {
/* copy AltiVec registers VR[0] .. VR[31] */
for (i = 0; i < 32; i++)
- for (j = 0; j < 4; j++, data++)
+ for (j = 0; j < 4; j++, data++)
if (__get_user(task->thread.vr[i].u[j], data))
return -EFAULT;
/* copy VSCR */
- for (i = 0; i < 4; i++, data++)
+ for (i = 0; i < 4; i++, data++)
if (__get_user(task->thread.vscr.u[i], data))
return -EFAULT;
switch (request) {
/* when I and D space are separate, these will need to be fixed. */
- case PTRACE_PEEKTEXT: /* read word at location addr. */
+ case PTRACE_PEEKTEXT: /* read word at location addr. */
case PTRACE_PEEKDATA: {
unsigned long tmp;
int copied;
}
/*
- * make the child exit. Best I can do is send it a sigkill.
- * perhaps it should be put in the status that it wants to
+ * make the child exit. Best I can do is send it a sigkill.
+ * perhaps it should be put in the status that it wants to
* exit.
*/
case PTRACE_KILL: {
unsigned long sysmap_size;
/* Used with the BI_MEMSIZE bootinfo parameter to store the memory
- size value reported by the boot loader. */
+ size value reported by the boot loader. */
unsigned long boot_mem_size;
unsigned long ISA_DMA_THRESHOLD;
{
ppc_md.restart(cmd);
}
-
+
void machine_power_off(void)
{
ppc_md.power_off();
}
-
+
void machine_halt(void)
{
ppc_md.halt();
break;
}
- seq_printf(m, "revision\t: %hd.%hd (pvr %04x %04x)\n",
+ seq_printf(m, "revision\t: %hd.%hd (pvr %04x %04x)\n",
maj, min, PVR_VER(pvr), PVR_REV(pvr));
seq_printf(m, "bogomips\t: %lu.%02lu\n",
{
struct device_node *cpu_node;
int *fp, s;
-
+
cpu_node = find_type_devices("cpu");
if (!cpu_node)
return 0;
{
char *model;
struct device_node *root;
-
+
/* ask the OF info if we're a chrp or pmac */
root = find_path_device("/");
if (root != 0) {
btext_clearscreen();
btext_welcome();
}
-#endif
+#endif
parse_bootinfo(find_bootinfo());
* bootargs property of the /chosen node.
* If an initial ramdisk is present, r3 and r4
* are used for initrd_start and initrd_size,
- * otherwise they contain 0xdeadbeef.
+ * otherwise they contain 0xdeadbeef.
*/
cmd_line[0] = 0;
if (r3 >= 0x4000 && r3 < 0x800000 && r4 == 0) {
} else {
struct device_node *chosen;
char *p;
-
+
#ifdef CONFIG_BLK_DEV_INITRD
if (r3 && r4 && r4 != 0xdeadbeef) {
if (r3 < KERNELBASE)
extern int __adb_probe_sync;
__adb_probe_sync = 1;
}
-#endif /* CONFIG_ADB */
+#endif /* CONFIG_ADB */
switch (_machine) {
case _MACH_Pmac:
int __init ppc_init(void)
{
int i;
-
+
/* clear the progress line */
if ( ppc_md.progress ) ppc_md.progress(" ", 0xffff);
init_mm.end_code = (unsigned long) _etext;
init_mm.end_data = (unsigned long) _edata;
init_mm.brk = (unsigned long) klimit;
-
+
/* Save unparsed command line copy for /proc/cmdline */
strcpy(saved_command_line, cmd_line);
*cmdline_p = cmd_line;
/*
* arch/ppc/kernel/signal.c
*
- * PowerPC version
+ * PowerPC version
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
* Derived from "arch/i386/kernel/signal.c"
return do_sigaltstack(uss, uoss, regs->gpr[1]);
}
-int
+int
sys_sigaction(int sig, const struct old_sigaction __user *act,
struct old_sigaction __user *oact)
{
|| __put_user(0, &rt_sf->uc.uc_flags)
|| __put_user(0, &rt_sf->uc.uc_link)
|| __put_user(current->sas_ss_sp, &rt_sf->uc.uc_stack.ss_sp)
- || __put_user(sas_ss_flags(regs->gpr[1]),
+ || __put_user(sas_ss_flags(regs->gpr[1]),
&rt_sf->uc.uc_stack.ss_flags)
|| __put_user(current->sas_ss_size, &rt_sf->uc.uc_stack.ss_size)
|| __put_user(&rt_sf->uc.uc_mcontext, &rt_sf->uc.uc_regs)
extern void __save_cpu_setup(void);
/* Since OpenPIC has only 4 IPIs, we use slightly different message numbers.
- *
+ *
* Make sure this matches openpic_request_IPIs in open_pic.c, or what shows up
* in /proc/interrupts will be wrong!!! --Troy */
#define PPC_MSG_CALL_FUNCTION 0
smp_ops->message_pass((t),(m),(d),(w)); \
} while(0)
-/*
+/*
* Common functions
*/
void smp_local_timer_interrupt(struct pt_regs * regs)
void smp_message_recv(int msg, struct pt_regs *regs)
{
atomic_inc(&ipi_recv);
-
+
switch( msg ) {
case PPC_MSG_CALL_FUNCTION:
smp_call_function_interrupt();
break;
- case PPC_MSG_RESCHEDULE:
+ case PPC_MSG_RESCHEDULE:
set_need_resched();
break;
case PPC_MSG_INVALIDATE_TLB:
/* wake up cpu */
smp_ops->kick_cpu(cpu);
-
+
/*
* wait to see if the cpu made a callin (is actually up).
* use this value that I found through experimentation.
/*
* arch/ppc/kernel/sys_ppc.c
*
- * PowerPC version
+ * PowerPC version
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
* Derived from "arch/i386/kernel/sys_i386.c"
ret = put_user (raddr, (ulong __user *) third);
break;
}
- case SHMDT:
+ case SHMDT:
ret = sys_shmdt ((char __user *)ptr);
break;
case SHMGET:
if (!(file = fget(fd)))
goto out;
}
-
+
down_write(¤t->mm->mmap_sem);
ret = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
up_write(¤t->mm->mmap_sem);
return -EFAULT;
if (!access_ok(VERIFY_WRITE,name,sizeof(struct oldold_utsname)))
return -EFAULT;
-
+
down_read(&uts_sem);
error = __copy_to_user(&name->sysname,&system_utsname.sysname,__OLD_UTS_LEN);
error -= __put_user(0,name->sysname+__OLD_UTS_LEN);
* TODO:
* dynamic power management to limit peak CPU temp (using ICTC)
* calibration???
- *
+ *
* Silly, crazy ideas: use cpu load (from scheduler) and ICTC to extend battery
* life in portables, and add a 'performance/watt' metric somewhere in /proc
*/
#endif
#ifndef CONFIG_TAU_INT /* tau_timeout will do this if not using interrupts */
- set_thresholds(cpu);
+ set_thresholds(cpu);
#endif
}
irq_enter();
tau[cpu].interrupts++;
-
+
TAUupdate(cpu);
irq_exit();
unsigned long flags;
int size;
int shrink;
-
+
/* disabling interrupts *should* be okay */
local_irq_save(flags);
cpu = smp_processor_id();
#ifndef CONFIG_TAU_INT
TAUupdate(cpu);
#endif
-
+
size = tau[cpu].high - tau[cpu].low;
if (size > min_window && ! tau[cpu].grew) {
/* do an exponential shrink of half the amount currently over size */
}
tau[cpu].grew = 0;
-
+
set_thresholds(cpu);
/*
* Do the enable every time, since otherwise a bunch of (relatively)
* complex sleep code needs to be added. One mtspr every time
* tau_timeout is called is probably not a big deal.
- *
+ *
* Enable thermal sensor and set up sample interval timer
* need 20 us to do the compare.. until a nice 'cpu_speed' function
* call is implemented, just assume a 500 mhz clock. It doesn't really
- * matter if we take too long for a compare since it's all interrupt
- * driven anyway.
+ * matter if we take too long for a compare since it's all interrupt
+ * driven anyway.
*
* use a extra long time.. (60 us @ 500 mhz)
*/
/*
* setup the TAU
- *
+ *
* Set things up to use THRM1 as a temperature lower bound, and THRM2 as an upper bound.
* Start off at zero
*/
void __init TAU_init_smp(void * info)
{
unsigned long cpu = smp_processor_id();
-
+
/* set these to a reasonable value and let the timer shrink the
* window */
tau[cpu].low = 5;
tau_timer.function = tau_timeout_smp;
tau_timer.expires = jiffies + shrink_timer;
add_timer(&tau_timer);
-
+
on_each_cpu(TAU_init_smp, NULL, 1, 0);
-
+
printk("Thermal assist unit ");
#ifdef CONFIG_TAU_INT
printk("using interrupts, ");
#else
printk("using timers, ");
#endif
- printk("shrink_timer: %d jiffies\n", shrink_timer);
+ printk("shrink_timer: %d jiffies\n", shrink_timer);
tau_initialized = 1;
return 0;
do_IRQ(regs);
irq_enter();
-
+
while ((next_dec = tb_ticks_per_jiffy - tb_delta(&jiffy_stamp)) < 0) {
jiffy_stamp += tb_ticks_per_jiffy;
if (!user_mode(regs))
* harmful to relatively short timers.
*/
- /* This works perfectly on SMP only if the tb are in sync but
+ /* This works perfectly on SMP only if the tb are in sync but
* guarantees an error < 1 jiffy even if they are off by eons,
* still reasonable when gettimeofday resolution is 1 jiffy.
*/
set_normalized_timespec(&xtime, new_sec, new_nsec);
set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec);
- /* In case of a large backwards jump in time with NTP, we want the
+ /* In case of a large backwards jump in time with NTP, we want the
* clock to be updated as soon as the PLL is again in lock.
*/
last_rtc_update = new_sec - 658;
ppc_md.calibrate_decr();
}
- /* Now that the decrementer is calibrated, it can be used in case the
+ /* Now that the decrementer is calibrated, it can be used in case the
* clock is stuck, but the fact that we have to handle the 601
* makes things more complex. Repeatedly read the RTC until the
* next second boundary to try to achieve some precision. If there
sec = ppc_md.get_rtc_time();
elapsed = 0;
do {
- old_stamp = stamp;
+ old_stamp = stamp;
old_sec = sec;
stamp = get_native_tbl();
if (__USE_RTC() && stamp < old_stamp)
. = ALIGN(4096);
__init_begin = .;
- .init.text : {
+ .init.text : {
_sinittext = .;
*(.init.text)
_einittext = .;
}
- .init.data : {
+ .init.data : {
*(.init.data);
__vtop_table_begin = .;
*(.vtop_fixup);
__stop___param = .;
__initcall_start = .;
.initcall.init : {
- *(.initcall1.init)
- *(.initcall2.init)
- *(.initcall3.init)
- *(.initcall4.init)
- *(.initcall5.init)
- *(.initcall6.init)
+ *(.initcall1.init)
+ *(.initcall2.init)
+ *(.initcall3.init)
+ *(.initcall4.init)
+ *(.initcall5.init)
+ *(.initcall6.init)
*(.initcall7.init)
}
__initcall_end = .;
/*
- * Locks for smp ppc
- *
+ * Locks for smp ppc
+ *
* Written by Cort Dougan (cort@cs.nmt.edu)
*/
{
if (__spin_trylock(&lock->lock))
return 0;
- lock->owner_cpu = smp_processor_id();
+ lock->owner_cpu = smp_processor_id();
lock->owner_pc = (unsigned long)__builtin_return_address(0);
return 1;
}
unsigned long stuck = INIT_STUCK;
int cpu = smp_processor_id();
-again:
+again:
/* get our read lock in there */
atomic_inc((atomic_t *) &(rw)->lock);
if ( (signed long)((rw)->lock) < 0) /* someone has a write lock */
}
goto again;
}
-
+
if ( (rw)->lock & ~(1<<31)) /* someone has a read lock */
{
/* clear our write lock and wait for reads to go away */
*ccr &= ~(15 << ((7 - crfD) << 2));
*ccr |= (cmp << ((7 - crfD) << 2));
-
+
#ifdef DEBUG
printk("CR: %08x\n", *ccr);
#endif
udiv_qrnnd(_q, _r, _nh, _nl, Y##_f); \
R##_f = _q | (_r != 0); \
} while (0)
-
-
+
+
/*
* Square root algorithms:
* We have just one right now, maybe Newton approximation
* should be added for those machines where division is fast.
*/
-
+
#define _FP_SQRT_MEAT_1(R, S, T, X, q) \
do { \
while (q) \
} while (0)
/*
- * Assembly/disassembly for converting to/from integral types.
+ * Assembly/disassembly for converting to/from integral types.
* No shifting or overflow handled here.
*/
#define _FP_MINFRAC_2 0, 1
/*
- * Internals
+ * Internals
*/
#define __FP_FRAC_SET_2(X,I1,I0) (X##_f0 = I0, X##_f1 = I1)
/* This next macro appears to be totally broken. Fortunately nowhere
* seems to use it :-> The problem is that we define _z[4] but
* then use it in _FP_FRAC_SRS_4, which will attempt to access
- * _z_f[n] which will cause an error. The fix probably involves
- * declaring it with _FP_FRAC_DECL_4, see previous macro. -- PMM 02/1998
+ * _z_f[n] which will cause an error. The fix probably involves
+ * declaring it with _FP_FRAC_DECL_4, see previous macro. -- PMM 02/1998
*/
#define _FP_MUL_MEAT_2_gmp(fs, R, X, Y) \
do { \
/*
* Division algorithms:
- * This seems to be giving me difficulties -- PMM
+ * This seems to be giving me difficulties -- PMM
* Look, NetBSD seems to be able to comment algorithms. Can't you?
* I've thrown printks at the problem.
* This now appears to work, but I still don't really know why.
* We have just one right now, maybe Newton approximation
* should be added for those machines where division is fast.
*/
-
+
#define _FP_SQRT_MEAT_2(R, S, T, X, q) \
do { \
while (q) \
/*
- * Assembly/disassembly for converting to/from integral types.
+ * Assembly/disassembly for converting to/from integral types.
* No shifting or overflow handled here.
*/
* _FP_MUL_MEAT_2_wide() uses _FP_FRAC_DECL_4, _FP_FRAC_WORD_4,
* _FP_FRAC_ADD_4, _FP_FRAC_SRS_4
* _FP_MUL_MEAT_2_gmp() uses _FP_FRAC_SRS_4 (and should use
- * _FP_FRAC_DECL_4: it appears to be broken and is not used
+ * _FP_FRAC_DECL_4: it appears to be broken and is not used
* anywhere anyway. )
*
* I've now fixed all the macros that were here from the sparc64 code.
* [*none* of the shift macros were correct!] -- PMM 02/1998
- *
- * The only quadword stuff that remains to be coded is:
- * 1) the conversion to/from ints, which requires
+ *
+ * The only quadword stuff that remains to be coded is:
+ * 1) the conversion to/from ints, which requires
* that we check (in op-common.h) that the following do the right thing
* for quadwords: _FP_TO_INT(Q,4,r,X,rsz,rsg), _FP_FROM_INT(Q,4,X,r,rs,rt)
* 2) multiply, divide and sqrt, which require:
/* The _FP_FRAC_SET_n(X,I) macro is intended for use with another
* macro such as _FP_ZEROFRAC_n which returns n comma separated values.
* The result is that we get an expansion of __FP_FRAC_SET_n(X,I0,I1,I2,I3)
- * which just assigns the In values to the array X##_f[].
+ * which just assigns the In values to the array X##_f[].
* This is why the number of parameters doesn't appear to match
- * at first glance... -- PMM
+ * at first glance... -- PMM
*/
#define _FP_FRAC_SET_4(X,I) __FP_FRAC_SET_4(X, I)
#define _FP_FRAC_HIGH_4(X) (X##_f[3])
} while (0)
-/* Right shift with sticky-lsb.
+/* Right shift with sticky-lsb.
* What this actually means is that we do a standard right-shift,
* but that if any of the bits that fall off the right hand side
* were one then we always set the LSbit.
/*
- * Internals
+ * Internals
*/
#define __FP_FRAC_SET_4(X,I3,I2,I1,I0) \
/* Convert FP values between word sizes. This appears to be more
* complicated than I'd have expected it to be, so these might be
* wrong... These macros are in any case somewhat bogus because they
- * use information about what various FRAC_n variables look like
+ * use information about what various FRAC_n variables look like
* internally [eg, that 2 word vars are X_f0 and x_f1]. But so do
- * the ones in op-2.h and op-1.h.
+ * the ones in op-2.h and op-1.h.
*/
#define _FP_FRAC_CONV_1_4(dfs, sfs, D, S) \
do { \
D##_f1 = S##_f[1]; \
} while (0)
-/* Assembly/disassembly for converting to/from integral types.
+/* Assembly/disassembly for converting to/from integral types.
* No shifting or overflow handled here.
*/
/* Put the FP value X into r, which is an integer of size rsize. */
* Convert from FP to integer
*/
-/* "When a NaN, infinity, large positive argument >= 2147483648.0, or
+/* "When a NaN, infinity, large positive argument >= 2147483648.0, or
* large negative argument <= -2147483649.0 is converted to an integer,
* the invalid_current bit...should be set and fp_exception_IEEE_754 should
* be raised. If the floating point invalid trap is disabled, no trap occurs
* -- SPARC Architecture Manual V9, Appendix B, which specifies how
* SPARCs resolve implementation dependencies in the IEEE-754 spec.
* I don't believe that the code below follows this. I'm not even sure
- * it's right!
+ * it's right!
* It doesn't cope with needing to convert to an n bit integer when there
* is no n bit integer type. Fortunately gcc provides long long so this
* isn't a problem for sparc32.
* -- PMM 02/1998
* NB: rsigned is not 'is r declared signed?' but 'should the value stored
* in r be signed or unsigned?'. r is always(?) declared unsigned.
- * Comments below are mine, BTW -- PMM
+ * Comments below are mine, BTW -- PMM
*/
#define _FP_TO_INT(fs, wc, r, X, rsize, rsigned) \
do { \
You should have received a copy of the GNU Library General Public
License along with the GNU C Library; see the file COPYING.LIB. If
not, write to the Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
Actually, this is a PPC (32bit) version, written based on the
- i386, sparc, and sparc64 versions, by me,
+ i386, sparc, and sparc64 versions, by me,
Peter Maydell (pmaydell@chiark.greenend.org.uk).
Comments are by and large also mine, although they may be inaccurate.
/* We need to know how to multiply and divide. If the host word size
* is >= 2*fracbits you can use FP_MUL_MEAT_n_imm(t,R,X,Y) which
* codes the multiply with whatever gcc does to 'a * b'.
- * _FP_MUL_MEAT_n_wide(t,R,X,Y,f) is used when you have an asm
- * function that can multiply two 1W values and get a 2W result.
+ * _FP_MUL_MEAT_n_wide(t,R,X,Y,f) is used when you have an asm
+ * function that can multiply two 1W values and get a 2W result.
* Otherwise you're stuck with _FP_MUL_MEAT_n_hard(t,R,X,Y) which
* does bitshifting to avoid overflow.
* For division there is FP_DIV_MEAT_n_imm(t,R,X,Y,f) for word size
- * >= 2*fracbits, where f is either _FP_DIV_HELP_imm or
+ * >= 2*fracbits, where f is either _FP_DIV_HELP_imm or
* _FP_DIV_HELP_ldiv (see op-1.h).
* _FP_DIV_MEAT_udiv() is if you have asm to do 2W/1W => (1W, 1W).
* [GCC and glibc have longlong.h which has the asm macro udiv_qrnnd
#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_udiv(S,R,X,Y)
#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv_64(D,R,X,Y)
-/* These macros define what NaN looks like. They're supposed to expand to
+/* These macros define what NaN looks like. They're supposed to expand to
* a comma-separated set of 32bit unsigned ints that encode NaN.
*/
#define _FP_NANFRAC_S _FP_QNANBIT_S
#define _FP_KEEPNANFRACP 1
-/* This macro appears to be called when both X and Y are NaNs, and
+/* This macro appears to be called when both X and Y are NaNs, and
* has to choose one and copy it to R. i386 goes for the larger of the
* two, sparc64 just picks Y. I don't understand this at all so I'll
- * go with sparc64 because it's shorter :-> -- PMM
+ * go with sparc64 because it's shorter :-> -- PMM
*/
#define _FP_CHOOSENAN(fs, wc, R, X, Y) \
do { \
_FP_FRAC_COPY_##wc(R,Y); \
R##_c = FP_CLS_NAN; \
} while (0)
-
+
extern void fp_unpack_d(long *, unsigned long *, unsigned long *,
long *, long *, void *);
_flo->bits.exp = X##_e; \
_flo->bits.sign = X##_s; \
} while (0)
-
+
#define __FP_PACK_RAW_2(fs, val, X) \
do { \
union _FP_UNION_##fs *_flo = \
"r" ((USItype)(bl))); \
} while (0)
-/* asm fragments for mul and div */
+/* asm fragments for mul and div */
/* umul_ppmm(high_prod, low_prod, multipler, multiplicand) multiplies two
* UWtype integers MULTIPLER and MULTIPLICAND, and generates a two UWtype
#include <linux/types.h>
#include <linux/errno.h>
#include <asm/uaccess.h>
-
+
int
stfd(void *frS, void *ea)
{
* This file contains the routines for initializing the MMU
* on the 4xx series of chips.
* -- paulus
- *
+ *
* Derived from arch/ppc/mm/init.c:
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
* This file contains the routines for initializing the MMU
* on the 4xx series of chips.
* -- paulus
- *
+ *
* Derived from arch/ppc/mm/init.c:
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
p += LARGE_PAGE_SIZE_16M;
s += LARGE_PAGE_SIZE_16M;
}
-
+
while (s <= (total_lowmem - LARGE_PAGE_SIZE_4M)) {
pmd_t *pmdp;
unsigned long val = p | _PMD_SIZE_4M | _PAGE_HWEXEC | _PAGE_HWWRITE;
/*
* arch/ppc/mm/fault.c
*
- * PowerPC version
+ * PowerPC version
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
* Derived from "arch/i386/mm/fault.c"
/* Guarded storage error. */
goto bad_area;
#endif /* CONFIG_8xx */
-
+
/* a write */
if (is_write) {
if (!(vma->vm_flags & VM_WRITE))
bad_area:
up_read(&mm->mmap_sem);
- pte_errors++;
+ pte_errors++;
/* User mode accesses cause a SIGSEGV */
if (user_mode(regs)) {
unsigned long va_to_phys(unsigned long address)
{
pte_t *pte;
-
+
pte = va_to_pte(address);
if (pte)
return(((unsigned long)(pte_val(*pte)) & PAGE_MASK) | (address & ~(PAGE_MASK)));
if (pte) {
printk(" (0x%08lx)->(0x%08lx)->0x%08lx\n",
(long)pgd, (long)pte, (long)pte_val(*pte));
-#define pp ((long)pte_val(*pte))
+#define pp ((long)pte_val(*pte))
printk(" RPN: %05lx PP: %lx SPS: %lx SH: %lx "
"CI: %lx v: %lx\n",
pp>>12, /* rpn */
(pp>>1)&1, /* cache inhibit */
pp&1 /* valid */
);
-#undef pp
+#undef pp
}
else {
printk("no pte\n");
*
* $Id: hashtable.S,v 1.6 1999/10/08 01:56:15 paulus Exp $
*
- * PowerPC version
+ * PowerPC version
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
* Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
- *
+ *
*/
#include <linux/config.h>
lwz r7,GPR7(r11)
lwz r8,GPR8(r11)
b fast_exception_return
-
+
#ifdef CONFIG_SMP
hash_page_out:
eieio
* memory as high as possible (it must be outside of the
* bus address seen as the AGP aperture). It will be used
* by the r128 DRM driver
- *
+ *
* FIXME: We need to make sure that page doesn't overlap any of the\
* above. This could be done by improving mem_pieces_find to be able
* to do a backward search from the end of the list.
*/
if (_machine == _MACH_Pmac && find_devices("uni-north-agp")) {
agp_special_page = (total_memory - PAGE_SIZE);
- mem_pieces_remove(&phys_avail, agp_special_page, PAGE_SIZE, 0);
+ mem_pieces_remove(&phys_avail, agp_special_page, PAGE_SIZE, 0);
agp_special_page = (unsigned long)__va(agp_special_page);
}
#endif /* CONFIG_PPC_PMAC */
}
}
panic("Couldn't find %u bytes at %u alignment\n", size, align);
-
+
return NULL;
}
/*
* Remove some memory from an array of pieces
*/
-void __init
+void __init
mem_pieces_remove(struct mem_pieces *mp, unsigned int start, unsigned int size,
int must_exist)
{
* architecture specification. This includes the 6xx, 7xx, 7xxx,
* 8260, and POWER3 implementations but excludes the 8xx and 4xx.
* -- paulus
- *
+ *
* Derived from arch/ppc/mm/init.c:
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
/*
* Declarations of procedures and variables shared between files
* in arch/ppc/mm/.
- *
+ *
* Derived from arch/ppc/mm/init.c:
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
/*
* This file contains the routines setting up the linux page tables.
* -- paulus
- *
+ *
* Derived from arch/ppc/mm/init.c:
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
*/
if ((v = p_mapped_by_bats(p)) /*&& p_mapped_by_bats(p+size-1)*/ )
goto out;
-
+
if (mem_init_done) {
struct vm_struct *area;
area = get_vm_area(size, VM_IOREMAP);
mm = current->mm;
else
mm = &init_mm;
-
+
pa = 0;
if (get_pteptr(mm, addr, &pte)) {
pa = (pte_val(*pte) & PAGE_MASK) | (addr & ~PAGE_MASK);
goto exit;
}
}
-
+
ret = (unsigned long) __va(paddr);
}
exit:
* architecture specification. This includes the 6xx, 7xx, 7xxx,
* 8260, and POWER3 implementations but excludes the 8xx and 4xx.
* -- paulus
- *
+ *
* Derived from arch/ppc/mm/init.c:
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
/*
* This file contains the routines for TLB flushing.
* On machines where the MMU uses a hash table to store virtual to
- * physical translations, these routines flush entries from the
+ * physical translations, these routines flush entries from the
* hash table also.
* -- paulus
- *
+ *
* Derived from arch/ppc/mm/init.c:
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
/*
* FILE NAME: ocp-driver.c
*
- * BRIEF MODULE DESCRIPTION:
+ * BRIEF MODULE DESCRIPTION:
* driver callback, id matching and registration
* Based on drivers/pci/pci-driver, Copyright (c) 1997--1999 Martin Mares
*
* of the IDs listed for a given OCP driver.
* @dev: the generic device struct for the OCP device
* @drv: the generic driver struct for the OCP driver
- *
+ *
* Used by a driver to check whether a OCP device present in the
* system is in its list of supported devices. Returns 1 for a
* match, or 0 if there is no match.
/**
* ocp_register_driver - register a new ocp driver
* @drv: the driver structure to register
- *
+ *
* Adds the driver structure to the list of registered drivers
* Returns the number of ocp devices which were claimed by the driver
* during registration. The driver remains registered even if the
/**
* ocp_unregister_driver - unregister a ocp driver
* @drv: the driver structure to unregister
- *
+ *
* Deletes the driver structure from the list of registered OCP drivers,
* gives it a chance to clean up by calling its remove() function for
* each device it was responsible for, and marks those devices as
/*
* FILE NAME: ocp-probe.c
*
- * BRIEF MODULE DESCRIPTION:
+ * BRIEF MODULE DESCRIPTION:
* Device scanning & bus set routines
* Based on drivers/pci/probe, Copyright (c) 1997--1999 Martin Mares
*
dev->current_state = 4;
sprintf(dev->name, "OCP device %04x:%04x", dev->vendor, dev->device);
-
+
DBG("%s %s 0x%lx irq:%d pm:0x%lx \n", dev->slot_name, dev->name,
(unsigned long) dev->paddr, dev->irq, dev->pm);
* ocp_get_num - This determines how many OCP devices of a given
* device are registered
* @device: OCP device such as HOST, PCI, GPT, UART, OPB, IIC, GPIO, EMAC, ZMII,
- *
+ *
* The routine returns the number that devices which is registered
*/
unsigned int ocp_get_num(unsigned int device)
}
/**
- * ocp_get_dev - get ocp driver pointer for ocp device and instance of it
+ * ocp_get_dev - get ocp driver pointer for ocp device and instance of it
* @device: OCP device such as PCI, GPT, UART, OPB, IIC, GPIO, EMAC, ZMII
* @dev_num: ocp device number whos paddr you want
- *
- * The routine returns ocp device pointer
+ *
+ * The routine returns ocp device pointer
* in list based on device and instance of that device
*
*/
# Makefile for the PowerPC 4xx linux kernel.
obj-$(CONFIG_ASH) += ash.o
-obj-$(CONFIG_BEECH) += beech.o
+obj-$(CONFIG_BEECH) += beech.o
obj-$(CONFIG_CEDAR) += cedar.o
obj-$(CONFIG_CPCI405) += cpci405.o
-obj-$(CONFIG_EBONY) += ebony.o
+obj-$(CONFIG_EBONY) += ebony.o
obj-$(CONFIG_EP405) += ep405.o
obj-$(CONFIG_OAK) += oak.o
obj-$(CONFIG_OCOTEA) += ocotea.o
obj-$(CONFIG_REDWOOD_4) += redwood.o
obj-$(CONFIG_REDWOOD_5) += redwood5.o
-obj-$(CONFIG_REDWOOD_6) += redwood6.o
+obj-$(CONFIG_REDWOOD_6) += redwood6.o
obj-$(CONFIG_SYCAMORE) += sycamore.o
obj-$(CONFIG_WALNUT) += walnut.o
/*
* arch/ppc/platforms/4xx/ash.c
- *
+ *
* Support for the IBM NP405H ash eval board
- *
+ *
* Author: Armin Kuster <akuster@mvista.com>
*
* 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
-
+
/* Enable PTM1 and PTM2, mapped to PLB address 0. */
out_le32((void *) &(pcip->ptm1la), 0x00000000);
/* Write zero to PTM1 BAR. */
early_write_config_dword(hose, hose->first_busno,
- PCI_FUNC(hose->first_busno),
+ PCI_FUNC(hose->first_busno),
PCI_BASE_ADDRESS_1,
0x00000000);
static void beech_ebc_setup(void);
static void beech_fpga_setup(void);
-/*
+/*
Beech board physical memory map:
Main Memory (Initialized by the BIOS)
Touch Panel Controller 0xEF600A00
DES Controller 0xEF600B00
-
+
EBC Space: (Mapped virtual = physical in ppc4xx_map_io(); EBC setup
for PCMCIA left to 4xx_pccf)
Space EBC Bank Physical Addresses EBC Base Address
=========================================================================
- PCMCIA (32 MB) x F0000000 - F1FFFFFF F0000000
+ PCMCIA (32 MB) x F0000000 - F1FFFFFF F0000000
Expansion 2 F8000000 - F8FFFFFF F8000000
Linux Flash (16 MB) F9000000 - F9FFFFFF
NVRAM (32 KB) 1 FFE00000 - FFE07FFF FFE00000
-
+
Ethernet(I/O) 1 FFE20300 - FFE2030F FFE00000
(MEM) FFE40000 - FFE40FFF
speed = 8 cycle access with 2 turnaround cycles (30 ns).
These parameters will work for the SRAM as well, which is a 70 ns
- part.
+ part.
NB: IBM BIOS sets this bank to burst, however bursting will never
happen in Linux because this region is mapped non-cacheable and
/* EBC bank 1 is used for many purposes: NVRAM, Ethernet, and FPGA
registers. This is a 1 MB, 16-bit bank. The access parameters must
- handle the worst case of all of the devices.
+ handle the worst case of all of the devices.
The Ethernet chip needs 20 ns setup of the addresses to the I/O
write signal (generated from the chip select), a minimum 150 ns
* IBM Research, Austin Center for Low-Power Computing
* bcbrock@us.ibm.com
* March, 2002
- *
+ *
*/
#ifdef __KERNEL__
* Data structure defining board information maintained by the standard boot
* ROM on the IBM Beech board. An effort has been made to
* keep the field names consistent with the 8xx 'bd_t' board info
- * structures.
+ * structures.
*/
typedef struct board_info {
bank. The lower 16 MB are available for expansion devices. The upper 16 MB
are used for the "Linux" flash.
- Partitioning information is for the benefit of the MTD driver. See
+ Partitioning information is for the benefit of the MTD driver. See
drivers/mtd/maps/ibm4xx.c. We currently allocate the lower 1 MB for a
kernel, and the other 15 MB for a filesystem.
/*
* arch/ppc/platforms/4xx/cedar.c
- *
+ *
* Support for the IBM NP405L ceder eval board
*
* Author: Armin Kuster <akuster@mvista.com>
#define CEDAR_RTC_VADDR CEDAR_RTC_PADDR
#define CEDAR_RTC_SIZE ((uint)8*1024)
-
/* Early initialization address mapping for block_io.
* Standard 405GP map.
*/
#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
-
#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK
#define BASE_BAUD 201600
#else
#define PPC4xx_MACHINE_NAME "IBM NP405L Cedar"
-
-
-
#endif /* !__ASSEMBLY__ */
#endif /* __ASM_CEDAR_H__ */
#endif /* __KERNEL__ */
#include <asm/machdep.h>
#include <asm/todc.h>
-void *cpci405_nvram;
+void *cpci405_nvram;
/*
* Some IRQs unique to CPCI-405.
freq = EBONY_440GP_RC_SYSCLK;
break;
}
-
+
tb_ticks_per_jiffy = freq / HZ;
tb_to_us = mulhwu_scale_factor(freq, 1000000);
{
static char pci_irq_table[][4] =
/*
- * PCI IDSEL/INTPIN->INTLINE
+ * PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
PCIX_WRITEL(0, PCIX0_PIM0SA);
PCIX_WRITEL(0, PCIX0_PIM1SA);
PCIX_WRITEL(0, PCIX0_PIM2SA);
-
+
/* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
*/
ibm440gp_get_clocks(&clocks, 33333333, 6 * 1843200);
__res.bi_opb_busfreq = clocks.opb;
-
+
/* Use IIC in standard (100 kHz) mode */
__res.bi_iic_fast[0] = __res.bi_iic_fast[1] = 0;
* http://www.embeddedplanet.com
*
* Author: Matthew Locke <mlocke@mvista.com>
- *
+ *
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
#ifdef CONFIG_PM
/* Set up the 405LP clock and power management unit for aggressive power
- management.
+ management.
Briefly, there are 3 CPM "classes":
Class 1 - Either completely asleep or awake. The "force" state is
- equivalent to the "enabled" state. Many Class 1 units are
+ equivalent to the "enabled" state. Many Class 1 units are
critical system components and are never power managed.
Class 2 - Can be enabled for power management, where sleep requests are
awaken the unit whenever it is targeted with a transaction.
Class 3 - Can be enabled for power management, where sleep requests are
- made by the CPM. Power management for these units typically
+ made by the CPM. Power management for these units typically
will require intelligence in a device driver.
In the current implementation, the "force" bits are only used on Class 1
devices, and only when the associated driver has the intelligence necessary
to "unforce" the power management state. A previous scheme, which tried to
enable power management based on whether a particular driver was compiled
- with the kernel, caused many problems and is never used here.
+ with the kernel, caused many problems and is never used here.
Class 2 devices with timeouts are normally initialized for the most
aggressive values. There is no power management benefit of "forcing" Class
2 devices over letting their inactivity timeouts take effect. Therefore,
after being set up here, Class 2 device drivers don't need to worry about
- CPM.
+ CPM.
No Class 3 devices are handled yet. */
enable |= IBM_CPM_DMA;
/* BRG - Class 2. Seems to crash the system when enabled in 405LP Pass
- 1
+ 1
DCP (CodePack) - Class 2. The semantics of the sleep delay are not
documented. We'll use 32 (what the heck). */
mtdcri(DCRN_SLA0, SLPMD, sla0_slpmd.reg);
enable |= IBM_CPM_SLA;
- /* CSI - Class 1.
+ /* CSI - Class 1.
TPC - Class 1.
TDES - Class 1.
At the end of the DCR defines several synonyms are defined for backwards
compatibility, but all new code specific to the 405LP uses the consistent
- names.
+ names.
Version 07/24/02 1.1 - Armin
added default pm define
/*****************************************************************************
* Indirectly accessed DCRs. Note that unlike direct-access DCRs whose numbers
* must be hard-coded into the instruction, indirect-access DCR numbers can be
- * computed.
+ * computed.
*****************************************************************************/
/* Offsets for SDRAM Controler Registers */
#define TDES0_IO_BASE 0xef600b00
/*****************************************************************************
- * CPM bits for the 405LP.
+ * CPM bits for the 405LP.
*****************************************************************************/
#define CPM_BITMASK(i) (((unsigned)0x80000000) >> i)
/* APM0_IER -- APM Interrupt Enable Register
APM0_IPR -- APM Interrupt Polarity Register
APM0_ISR -- APM Interrupt Status Register
- APM0_ITR -- APM Interrupt Trigger Register
+ APM0_ITR -- APM Interrupt Trigger Register
The interrupts are also accessed via standard interrupt numbers:
The mask is a mask with 1s in every reserved bit position.
NB: This routine always writes the register with the valid bit set,
- regardless of the valid bit setting in the 'new' parameter.
+ regardless of the valid bit setting in the 'new' parameter.
Unfortunately this must be a macro to work (due to mtdcr()).
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
- *
+ *
*/
#ifdef __KERNEL__
| IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
| IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
| IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
- | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
+ | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
/* OPB */
#define PPC440GX_OPB_BASE_START 0x0000000140000000ULL
#endif
/* UART 0 is duped here so when the SICC is the default console
- * then ttys1 is configured properly - armin
+ * then ttys1 is configured properly - armin
*/
#define UART1_INT 20
unsigned int freq;
freq = OCOTEA_SYSCLK;
-
+
tb_ticks_per_jiffy = freq / HZ;
tb_to_us = mulhwu_scale_factor(freq, 1000000);
{
static char pci_irq_table[][4] =
/*
- * PCI IDSEL/INTPIN->INTLINE
+ * PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
PCIX_WRITEL(0, PCIX0_PIM1SA);
PCIX_WRITEL(0, PCIX0_PIM2SA);
PCIX_WRITEL(0, PCIX0_PIM2SAH);
-
+
/* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
/* Setup PCI host bridge */
ocotea_setup_hose();
-
+
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
* STB03xxx "Redwood" evaluation board.
*
* Author: Frank Rowand <frank_rowand@mvista.com>, or source@mvista.com
- *
+ *
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
/*
- * Define all of the IRQ senses and polarities.
+ * Define all of the IRQ senses and polarities.
*/
static u_char redwood6_IRQ_initsenses[] __initdata = {
* arch/ppc/platforms/4xx/sycamore.c
*
* Architecture- / platform-specific boot-time initialization code for
- * IBM PowerPC 4xx based boards.
+ * IBM PowerPC 4xx based boards.
*
* Author: Armin Kuster <akuster@mvista.com>
*
void *sycamore_rtc_base;
/*
- * Define all of the IRQ senses and polarities.
+ * Define all of the IRQ senses and polarities.
*/
static u_char Sycamore_IRQ_initsenses[] __initdata = {
/*
* arch/ppc/platforms/adir.h
- *
+ *
* Definitions for SBS Adirondack board support
*
* By Michael Sokolov <msokolov@ivan.Harhan.ORG>
/*
* arch/ppc/platforms/adir_pci.c
- *
+ *
* PCI support for SBS Adirondack
*
* By Michael Sokolov <msokolov@ivan.Harhan.ORG>
if (!hose->index) {
static char pci_irq_table[][4] =
/*
- * PCI IDSEL/INTPIN->INTLINE
+ * PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
} else {
static char pci_irq_table[][4] =
/*
- * PCI IDSEL/INTPIN->INTLINE
+ * PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
if ((dev->vendor == PCI_VENDOR_ID_IBM) &&
(dev->device == PCI_DEVICE_ID_IBM_CPC710_PCI64))
- {
+ {
DBG("Fixup CPC710 resources\n");
for (i=0; i<DEVICE_COUNT_RESOURCE; i++)
{
* procedure to hang the system, we have no choice but to introduce this hack
* of knowingly avoiding device numbers > 21 on PCI0,
*/
-static int
+static int
adir_exclude_device(u_char bus, u_char devfn)
{
if ((bus == 0) && (PCI_SLOT(devfn) > 21))
/*
* arch/ppc/platforms/adir_pic.c
- *
+ *
* Interrupt controller support for SBS Adirondack
*
* By Michael Sokolov <msokolov@ivan.Harhan.ORG>
/* Change irq to Adirondack onboard native value */
irq -= 16;
- /* Enable requested irq number */
+ /* Enable requested irq number */
out_be16(maskreg, in_be16(maskreg) & ~(1 << irq));
}
/* Change irq to Adirondack onboard native value */
irq -= 16;
- /* Disable requested irq number */
+ /* Disable requested irq number */
out_be16(maskreg, in_be16(maskreg) | (1 << irq));
}
#define DPRINTK(a,b...) printk(KERN_DEBUG "apus_pci: %s: " a, __FUNCTION__ , ## b)
#else
#define DPRINTK(a,b...)
-#endif
+#endif
/*
* The _DEFINITIVE_ memory mapping/unmapping functions.
}
-/*
+/*
* This is from pm2fb.c again
- *
+ *
* Check if PCI (B/CVisionPPC) is available, initialize it and set up
* the pcibios_* pointers
*/
/*
* Siemens Card Controller Module specific definitions
- *
+ *
* Copyright (C) 2001-2002 Wolfgang Denk (wd@denx.de)
*/
#define __MACH_CCM_H
#include <linux/config.h>
-
+
#include <asm/ppcboot.h>
#define CCM_IMMR_BASE 0xF0000000 /* phys. addr of IMMR */
* XXX this should be in xmon.h, but putting it there means xmon.h
* has to include <linux/interrupt.h> (to get irqreturn_t), which
* causes all sorts of problems. -- paulus
- */
+ */
extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);
extern dev_t boot_dev;
#ifdef CONFIG_BLK_DEV_INITRD
/* this is fine for chrp */
initrd_below_start_ok = 1;
-
+
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
__pa(log), 1024 );
ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
}
-
+
void __chrp
chrp_restart(char *cmd)
{
int i;
unsigned long chrp_int_ack;
unsigned char init_senses[NR_IRQS - NUM_8259_INTERRUPTS];
-#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
+#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
struct device_node *kbd;
#endif
void __init
chrp_init2(void)
{
-#ifdef CONFIG_NVRAM
+#ifdef CONFIG_NVRAM
// XX replace this in a more saner way
// pmac_nvram_init();
#endif
/*
* Print the banner, then scroll down so boot progress
- * can be printed. -- Cort
+ * can be printed. -- Cort
*/
if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
}
/* Since the UIP flag is set for about 2.2 ms and the clock
* is typically written with a precision of 1 jiffy, trying
- * to obtain a precision better than a few milliseconds is
+ * to obtain a precision better than a few milliseconds is
* an illusion. Only consistency is interesting, this also
* allows to use the routine for /dev/rtc without a potential
- * 1 second kernel busy loop triggered by any reader of /dev/rtc.
+ * 1 second kernel busy loop triggered by any reader of /dev/rtc.
*/
for ( i = 0; i<1000000; i++) {
/*
* arch/ppc/kernel/error_log.c
- *
+ *
* Copyright (c) 2000 Tilmann Bitterberg
* (tilmann@bitterberg.de)
*
#include "error_log.h"
/* ****************************************************************** */
-/*
+/*
* EVENT-SCAN
* The whole stuff below here doesn't take any action when it found
- * an error, it just prints as much information as possible and
+ * an error, it just prints as much information as possible and
* then its up to the user to decide what to do.
*
* Returns 0 if no errors were found
#endif /* VERBOSE_ERRORS */
};
-const char *_errlog_initiator[] = {
+const char *_errlog_initiator[] = {
"Unknown or not applicable",
"CPU",
"PCI",
"Power management"
};
-const char *_errlog_target[] = {
+const char *_errlog_target[] = {
"Unknown or not applicable",
"CPU",
"PCI",
return 0;
}
if (error_log.version != 1)
- printk(KERN_WARNING "Unknown version (%d), please implement me\n",
+ printk(KERN_WARNING "Unknown version (%d), please implement me\n",
error_log.version);
switch (error_log.disposition) {
printk("We have a really serious Problem!\n");
case DISP_LIMITED_RECOVERY:
printk("Error classification\n");
- printk("Severity : %s\n",
+ printk("Severity : %s\n",
ppc_rtas_errorlog_check_severity (error_log));
- printk("Initiator : %s\n",
+ printk("Initiator : %s\n",
ppc_rtas_errorlog_check_initiator (error_log));
- printk("Target : %s\n",
+ printk("Target : %s\n",
ppc_rtas_errorlog_check_target (error_log));
- printk("Type : %s\n",
+ printk("Type : %s\n",
ppc_rtas_errorlog_check_type (error_log));
- printk("Ext. log : %s\n",
+ printk("Ext. log : %s\n",
ppc_rtas_errorlog_check_extended (error_log));
if (error_log.extended)
ppc_rtas_errorlog_disect_extended (logdata);
- return 1;
+ return 1;
default:
/* nothing */
break;
"uncorrectable ECC error",
"corrected ECC error" /* 10 */
};
- if (error_log.type == TYPE_EPOW)
- return "EPOW";
+ if (error_log.type == TYPE_EPOW)
+ return "EPOW";
if (error_log.type >= TYPE_PMGM_POWER_SW_ON)
return "PowerMGM Event (not handled right now)";
return _errlog_type[error_log.type];
#define TYPE_ECC_UNCORR 0x09
#define TYPE_ECC_CORR 0x0a
#define TYPE_EPOW 0x40
-/* I don't add PowerMGM events right now, this is a different topic */
+/* I don't add PowerMGM events right now, this is a different topic */
#define TYPE_PMGM_POWER_SW_ON 0x60
#define TYPE_PMGM_POWER_SW_OFF 0x61
#define TYPE_PMGM_LID_OPEN 0x62
/*
* arch/ppc/platforms/est8260_setup.c
- *
+ *
* EST8260 platform support
*
* Author: Allen Curtis <acurtis@onz.com>
extern unsigned char __res[sizeof(bd_t)];
-extern void m8260_init(unsigned long r3, unsigned long r4,
+extern void m8260_init(unsigned long r3, unsigned long r4,
unsigned long r5, unsigned long r6, unsigned long r7);
static int
/*
* arch/ppc/platforms/ev64260.h
- *
+ *
* Definitions for Marvell/Galileo EV-64260-BP Evaluation Board.
*
* Author: Mark A. Greer <mgreer@mvista.com>
if (hose->index == 0) {
static char pci_irq_table[][4] =
/*
- * PCI IDSEL/INTPIN->INTLINE
+ * PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
else {
static char pci_irq_table[][4] =
/*
- * PCI IDSEL/INTPIN->INTLINE
+ * PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
* arch/ppc/platforms/gemini.h
*
*
- * Onboard registers and descriptions for Synergy Microsystems'
+ * Onboard registers and descriptions for Synergy Microsystems'
* "Gemini" boards.
*
*/
/*
* Multidata HERMES-PRO ( / SL ) board specific definitions
- *
+ *
* Copyright (c) 2000, 2001 Wolfgang Denk (wd@denx.de)
*/
#define __MACH_HERMES_H
#include <linux/config.h>
-
+
#include <asm/ppcboot.h>
#define HERMES_IMMR_BASE 0xFF000000 /* phys. addr of IMMR */
/*
* MicroSys IP860 VMEBus board specific definitions
- *
+ *
* Copyright (c) 2000, 2001 Wolfgang Denk (wd@denx.de)
*/
#define __MACH_IP860_H
#include <linux/config.h>
-
+
#include <asm/ppcboot.h>
#define IP860_IMMR_BASE 0xF1000000 /* phys. addr of IMMR */
/*
* arch/ppc/platforms/k2.h
- *
+ *
* Definitions for SBS K2 board support
*
* Author: Matt Porter <mporter@mvista.com>
/*
* arch/ppc/platforms/k2_pci.c
- *
+ *
* PCI support for SBS K2
*
* Author: Matt Porter <mporter@mvista.com>
{
static char pci_irq_table[][4] =
/*
- * PCI IDSEL/INTPIN->INTLINE
+ * PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
{
static char pci_irq_table[][4] =
/*
- * PCI IDSEL/INTPIN->INTLINE
+ * PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
};
const long min_idsel = 15, max_idsel = 21, irqs_per_slot = 4;
return PCI_IRQ_TABLE_LOOKUP;
- }
+ }
}
void k2_pcibios_fixup(void)
-{
+{
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
struct pci_dev *ide_dev;
if ((dev->vendor == PCI_VENDOR_ID_IBM) &&
(dev->device == PCI_DEVICE_ID_IBM_CPC710_PCI64))
- {
+ {
DBG("Fixup CPC710 resources\n");
for (i=0; i<DEVICE_COUNT_RESOURCE; i++)
{
__raw_writel(0x80100000, K2_PCI32_BAR+TIODLK);
__raw_writel(0xe0008000, K2_PCI32_BAR+DLKCTRL);
__raw_writel(0xffffffff, K2_PCI32_BAR+DLKDEV);
-
+
/* PCI64 mappings */
__raw_writel(0x00100000, K2_PCI64_BAR+PIBAR); /* PCI I/O base */
__raw_writel(0x10000000, K2_PCI64_BAR+PMBAR); /* PCI Mem base */
k2_geo_bits = readb(K2_MSIZ_GEO_REG) & K2_GEO_ADR_MASK;
k2_system_slot = !(readb(K2_MISC_REG) & K2_SYS_SLOT_MASK);
- seq_printf(m, "backplane\t: %s slot board",
+ seq_printf(m, "backplane\t: %s slot board",
k2_system_slot ? "System" : "Non system");
seq_printf(m, "with geographical address %x\n", k2_geo_bits);
/*
* LANTEC board specific definitions
- *
+ *
* Copyright (c) 2001 Wolfgang Denk (wd@denx.de)
*/
#define __MACH_LANTEC_H
#include <linux/config.h>
-
+
#include <asm/ppcboot.h>
#define IMAP_ADDR 0xFFF00000 /* physical base address of IMMR area */
/*
* arch/ppc/platforms/lopec_pci.c
- *
+ *
* PCI setup routines for the Motorola LoPEC.
*
* Author: Dan Cox
/*
* include/asm-ppc/lopec_serial.h
- *
+ *
* Definitions for Motorola LoPEC board.
*
* Author: Dan Cox
/*
* arch/ppc/platforms/lopec_setup.c
- *
+ *
* Setup routines for the Motorola LoPEC.
*
* Author: Dan Cox
request_region(0x80, 0x10, "dma page reg");
request_region(0xa0, 0x20, "pic2");
request_region(0xc0, 0x20, "dma2");
-
+
return 0;
}
conswitchp = &dummy_con;
#endif
#ifdef CONFIG_PPCBUG_NVRAM
- /* Read in NVRAM data */
+ /* Read in NVRAM data */
init_prep_nvram();
/* if no bootargs, look in NVRAM */
/*
* Liebherr LWMON board specific definitions
- *
+ *
* Copyright (c) 2001 Wolfgang Denk (wd@denx.de)
*/
#define __MACH_LWMON_H
#include <linux/config.h>
-
+
#include <asm/ppcboot.h>
#define IMAP_ADDR 0xFFF00000 /* physical base address of IMMR area */
/*
* arch/ppc/platforms/mcpn765.h
- *
+ *
* Definitions for Motorola MCG MCPN765 cPCI Board.
*
* Author: Mark A. Greer
/*
* arch/ppc/platforms/mcpn765_pci.c
- *
+ *
* PCI setup routines for the Motorola MCG MCPN765 cPCI board.
*
* Author: Mark A. Greer
{
static char pci_irq_table[][4] =
/*
- * PCI IDSEL/INTPIN->INTLINE
+ * PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
/*
* include/asm-ppc/mcpn765_serial.h
- *
+ *
* Definitions for Motorola MCG MCPN765 cPCI board support
*
* Author: Mark A. Greer
/*
* arch/ppc/platforms/mpc82xx.h
- *
+ *
* Board specific support for various 82xx platforms.
*
* Author: Allen Curtis <acurtis@onz.com>
/*
* include/asm-ppc/platforms/mvme5100.h
- *
+ *
* Definitions for Motorola MVME5100.
*
* Author: Matt Porter <mporter@mvista.com>
/*
* arch/ppc/platforms/mvme5100_pci.c
- *
+ *
* PCI setup routines for the Motorola MVME5100.
*
* Author: Matt Porter <mporter@mvista.com>
static char pci_irq_table[][4] =
/*
- * PCI IDSEL/INTPIN->INTLINE
+ * PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
/* If lookup is zero, always return 0 */
if (!irq)
return 0;
- else
+ else
#ifdef CONFIG_MVME5100_IPMC761_PRESENT
/* If IPMC761 present, return table value */
return irq;
/*
* include/asm-ppc/mvme5100_serial.h
- *
+ *
* Definitions for Motorola MVME5100 support
*
* Author: Matt Porter <mporter@mvista.com>
/*
* arch/ppc/platforms/pal4.h
- *
+ *
* Definitions for SBS Palomar IV board
*
* Author: Dan Cox
/*
* arch/ppc/platforms/pal4_pci.c
- *
+ *
* PCI support for SBS Palomar IV
*
- * Author: Dan Cox
+ * Author: Dan Cox
*
* 2002 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
/* Could snatch these from the CPC700.... */
pci_init_resource(&hose->io_resource,
- 0x0,
+ 0x0,
0x03ffffff,
IORESOURCE_IO,
"PCI host bridge");
hose->mem_space.start = 0x90000000;
hose->mem_space.end = 0x9fffffff;
hose->io_base_virt = (void *) 0xf8000000;
-
+
setup_indirect_pci(hose, CPC700_PCI_CONFIG_ADDR,
CPC700_PCI_CONFIG_DATA);
-
+
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pci_swizzle = common_swizzle;
/*
* arch/ppc/platforms/pal4_serial.h
- *
- * Definitions for SBS PalomarIV serial support
+ *
+ * Definitions for SBS PalomarIV serial support
*
* Author: Dan Cox
*
{
unsigned long l2;
- TODC_INIT(TODC_TYPE_MK48T37, 0, 0,
+ TODC_INIT(TODC_TYPE_MK48T37, 0, 0,
ioremap(PAL4_NVRAM, PAL4_NVRAM_SIZE), 8);
pal4_find_bridges();
isa_io_base = 0 /*PAL4_ISA_IO_BASE*/;
pci_dram_offset = 0 /*PAL4_PCI_SYS_MEM_BASE*/;
-
+
ppc_md.setup_arch = pal4_setup_arch;
ppc_md.show_cpuinfo = pal4_show_cpuinfo;
-
+
ppc_md.setup_io_mappings = pal4_map_io;
ppc_md.init_IRQ = cpc700_init_IRQ;
/*
* arch/ppc/platforms/pcore.h
- *
+ *
* Definitions for Force PowerCore board support
*
* Author: Matt Porter <mporter@mvista.com>
#define PCORE_NVRAM_AS0 0x73
#define PCORE_NVRAM_AS1 0x75
-#define PCORE_NVRAM_DATA 0x77
+#define PCORE_NVRAM_DATA 0x77
#define PCORE_DCCR_REG (MPC10X_MAPB_ISA_IO_BASE + 0x308)
#define PCORE_DCCR_L2_MASK 0xc0
/*
* arch/ppc/platforms/pcore_pci.c
- *
+ *
* PCI support for Force PCORE boards
*
* Author: Matt Porter <mporter@mvista.com>
#define DBG(x...) printk(x)
#else
#define DBG(x...)
-#endif /* DEBUG */
+#endif /* DEBUG */
static inline int __init
pcore_6750_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
- */
+ */
{
{9, 10, 11, 12}, /* IDSEL 24 - DEC 21554 */
{10, 0, 0, 0}, /* IDSEL 25 - DEC 21143 */
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
- */
+ */
{
{9, 10, 11, 12}, /* IDSEL 24 - Sentinel */
{10, 0, 0, 0}, /* IDSEL 25 - i82559 #1 */
/* Reroute interrupts both IDE channels to 15 */
pci_write_config_byte(dev,
PCORE_WINBOND_IDE_INT,
- 0xff);
+ 0xff);
/* Route INTA-D to IRQ9-12, respectively */
pci_write_config_word(dev,
PCORE_WINBOND_PCI_INT,
- 0x9abc);
+ 0x9abc);
/*
* Set up 8259 edge/level triggering
- */
+ */
outb(0x00, PCORE_WINBOND_PRI_EDG_LVL);
outb(0x1e, PCORE_WINBOND_SEC_EDG_LVL);
}
/*
* Siemens PCU E board specific definitions
- *
+ *
* Copyright (c) 2001 Wolfgang Denk (wd@denx.de)
*/
#define __MACH_PCU_E_H
#include <linux/config.h>
-
+
#include <asm/ppcboot.h>
#define PCU_E_IMMR_BASE 0xFE000000 /* phys. addr of IMMR */
/*
* Miscellaneous procedures for dealing with the PowerMac hardware.
* Contains support for the backlight.
- *
+ *
* Copyright (C) 2000 Benjamin Herrenschmidt
*
*/
int valid = 0;
bk_node = find_devices("backlight");
-
+
#ifdef CONFIG_ADB_PMU
/* Special case for the old PowerBook since I can't test on it */
backlight_autosave = machine_is_compatible("AAPL,3400/2400")
return;
backlighter = ctrler;
backlighter_data = data;
-
+
if (bk_node && !backlight_autosave)
prop = get_property(bk_node, "bklt", NULL);
else
if (backlight_level > BACKLIGHT_MAX)
backlight_level = BACKLIGHT_MAX;
}
-
+
#ifdef CONFIG_ADB_PMU
if (backlight_autosave) {
struct adb_request req;
set_backlight_enable(int enable)
{
int rc;
-
+
if (!backlighter)
return -ENODEV;
rc = backlighter->set_enable(enable, backlight_level, backlighter_data);
set_backlight_level(int level)
{
int rc = 0;
-
+
if (!backlighter)
return -ENODEV;
if (level < BACKLIGHT_MIN)
cpu_750fx_cpu_speed(int low_speed)
{
#ifdef DEBUG_FREQ
- printk(KERN_DEBUG "HID1, before: %x\n", mfspr(SPRN_HID1));
+ printk(KERN_DEBUG "HID1, before: %x\n", mfspr(SPRN_HID1));
#endif
low_choose_750fx_pll(low_speed);
#ifdef DEBUG_FREQ
- printk(KERN_DEBUG "HID1, after: %x\n", mfspr(SPRN_HID1));
+ printk(KERN_DEBUG "HID1, after: %x\n", mfspr(SPRN_HID1));
debug_calc_bogomips();
#endif
struct adb_request req;
unsigned long save_l2cr;
unsigned long save_l3cr;
-
+
#ifdef DEBUG_FREQ
- printk(KERN_DEBUG "HID1, before: %x\n", mfspr(SPRN_HID1));
+ printk(KERN_DEBUG "HID1, before: %x\n", mfspr(SPRN_HID1));
#endif
/* Disable all interrupt sources on openpic */
openpic_suspend(NULL, 1);
/* Prepare the northbridge for the speed transition */
pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,1);
-
+
/* Call low level code to backup CPU state and recover from
* hardware reset
*/
low_sleep_handler();
-
+
/* Restore the northbridge */
pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,0);
set_context(current->active_mm->context, current->active_mm->pgd);
#ifdef DEBUG_FREQ
- printk(KERN_DEBUG "HID1, after: %x\n", mfspr(SPRN_HID1));
+ printk(KERN_DEBUG "HID1, after: %x\n", mfspr(SPRN_HID1));
#endif
/* Restore low level PMU operations */
{
struct cpufreq_freqs freqs;
int rc;
-
+
freqs.old = cur_freq;
freqs.new = (speed_mode == PMAC_CPU_HIGH_SPEED) ? hi_freq : low_freq;
freqs.cpu = smp_processor_id();
};
/* Currently, we support the following machines:
- *
+ *
* - Titanium PowerBook 800 (PMU based, 667Mhz & 800Mhz)
* - Titanium PowerBook 500 (PMU based, 300Mhz & 500Mhz)
* - iBook2 500 (PMU based, 400Mhz & 500Mhz)
*/
static int __init
pmac_cpufreq_setup(void)
-{
+{
struct device_node *cpunode;
u32 *value;
int has_freq_ctl = 0;
-
+
if (strstr(cmd_line, "nocpufreq"))
return 0;
* here */
if (low_freq < 100000)
low_freq *= 10;
-
+
value = (u32 *)get_property(cpunode, "max-clock-frequency", NULL);
if (!value)
goto out;
- hi_freq = (*value) / 1000;
+ hi_freq = (*value) / 1000;
has_freq_ctl = 1;
cpufreq_uses_pmu = 1;
}
/* Else check for 750FX */
else if (PVR_VER(mfspr(PVR)) == 0x7000) {
if (get_property(cpunode, "dynamic-power-step", NULL) == NULL)
- goto out;
+ goto out;
hi_freq = cur_freq;
value = (u32 *)get_property(cpunode, "reduced-clock-frequency", NULL);
if (!value)
out:
if (!has_freq_ctl)
return -ENODEV;
-
+
pmac_cpu_freqs[CPUFREQ_LOW].frequency = low_freq;
pmac_cpu_freqs[CPUFREQ_HIGH].frequency = hi_freq;
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
- *
- * TODO:
- *
+ *
+ * TODO:
+ *
* - Replace mdelay with some schedule loop if possible
* - Shorten some obfuscated delays on some routines (like modem
* power)
{
while(child) {
int i;
-
+
for (i=0; i < MAX_MACIO_CHIPS && macio_chips[i].of_node; i++)
if (child == macio_chips[i].of_node &&
(!type || macio_chips[i].type == type))
return NULL;
}
-static const char* macio_names[] __pmacdata =
+static const char* macio_names[] __pmacdata =
{
"Unknown",
"Grand Central",
/*
* Uninorth reg. access. Note that Uni-N regs are big endian
*/
-
+
#define UN_REG(r) (uninorth_base + ((r) >> 2))
#define UN_IN(r) (in_be32(UN_REG(r)))
#define UN_OUT(r,v) (out_be32(UN_REG(r), (v)))
typedef int (*feature_call)(struct device_node* node, int param, int value);
struct feature_table_entry {
- unsigned int selector;
+ unsigned int selector;
feature_call function;
};
{
struct macio_chip* macio;
unsigned long flags;
-
+
macio = macio_find(node, type);
if (!macio)
return -ENODEV;
unsigned long flags;
int htw, trans;
unsigned long rmask;
-
+
macio = macio_find(node, 0);
if (!macio)
return -ENODEV;
#ifdef CONFIG_ADB_PMU
if ((param & 0xfff) == PMAC_SCC_IRDA)
pmu_enable_irled(1);
-#endif /* CONFIG_ADB_PMU */
+#endif /* CONFIG_ADB_PMU */
LOCK(flags);
fcr = MACIO_IN32(OHARE_FCR);
/* Check if scc cell need enabling */
#ifdef CONFIG_ADB_PMU
if ((param & 0xfff) == PMAC_SCC_IRDA)
pmu_enable_irled(0);
-#endif /* CONFIG_ADB_PMU */
+#endif /* CONFIG_ADB_PMU */
}
return 0;
}
} else if (value == 0) {
MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
}
-
+
return 0;
}
struct macio_chip* macio;
u8 gpio;
unsigned long flags;
-
+
macio = macio_find(node, macio_unknown);
if (!macio)
return -ENODEV;
{
struct macio_chip* macio;
unsigned long flags;
-
+
macio = macio_find(node, macio_unknown);
if (!macio)
return -ENODEV;
MACIO_BIC(HEATHROW_MBCR, 0x00040000);
else
MACIO_BIS(HEATHROW_MBCR, 0x00040000);
-#endif
+#endif
(void)MACIO_IN32(HEATHROW_MBCR);
udelay(10);
UNLOCK(flags);
{
struct macio_chip* macio;
unsigned long flags;
-
+
macio = macio_find(node, 0);
if (!macio)
return -ENODEV;
if (pmac_mb.model_id == PMAC_TYPE_YOSEMITE ||
pmac_mb.model_id == PMAC_TYPE_YIKES)
return 0;
-
+
macio = macio_find(node, 0);
if (!macio)
return -ENODEV;
dbdma_save(struct macio_chip* macio, struct dbdma_regs* save)
{
int i;
-
+
/* Save state & config of DBDMA channels */
for (i=0; i<13; i++) {
volatile struct dbdma_regs* chan = (volatile struct dbdma_regs*)
dbdma_restore(struct macio_chip* macio, struct dbdma_regs* save)
{
int i;
-
+
/* Save state & config of DBDMA channels */
for (i=0; i<13; i++) {
volatile struct dbdma_regs* chan = (volatile struct dbdma_regs*)
unsigned long flags;
unsigned long chan_mask;
u32 fcr;
-
+
macio = macio_find(node, 0);
if (!macio)
return -ENODEV;
if (value) {
int need_reset_scc = 0;
int need_reset_irda = 0;
-
+
LOCK(flags);
fcr = MACIO_IN32(KEYLARGO_FCR0);
/* Check if scc cell need enabling */
unsigned long flags;
/* Hack for internal USB modem */
- if (node == NULL) {
+ if (node == NULL) {
if (macio_chips[0].type != macio_keylargo)
return -ENODEV;
node = macio_chips[0].of_node;
gpio = MACIO_IN8(KL_GPIO_MODEM_RESET);
gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE;
gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA;
-
+
if (!value) {
LOCK(flags);
MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
struct macio_chip* macio;
u8 gpio;
unsigned long flags;
-
+
/* Hack for internal USB modem */
- if (node == NULL) {
+ if (node == NULL) {
if (macio_chips[0].type != macio_pangea &&
macio_chips[0].type != macio_intrepid)
return -ENODEV;
gpio = MACIO_IN8(KL_GPIO_MODEM_RESET);
gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE;
gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA;
-
+
if (!value) {
LOCK(flags);
MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
{
unsigned long flags;
struct macio_chip* macio;
-
+
macio = &macio_chips[0];
if (macio->type != macio_keylargo && macio->type != macio_pangea &&
macio->type != macio_intrepid)
{
struct macio_chip* macio;
unsigned long flags;
-
+
macio = macio_find(node, 0);
if (!macio)
return -ENODEV;
struct macio_chip* macio;
unsigned long flags;
int state;
-
+
macio = macio_find(node, 0);
if (!macio)
return -ENODEV;
-
+
/* Hint: we allow passing of macio itself for the sake of the
* sleep code
*/
KL_GPIO_RESET_CPU1,
KL_GPIO_RESET_CPU2,
KL_GPIO_RESET_CPU3 };
-
+
macio = &macio_chips[0];
if (macio->type != macio_keylargo)
return -ENODEV;
-
+
np = find_path_device("/cpus");
if (np == NULL)
return -ENODEV;
}
if (np == NULL || reset_io == 0)
reset_io = dflt_reset_lines[param];
-
+
LOCK(flags);
MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE);
(void)MACIO_IN8(reset_io);
char* prop;
int number;
u32 reg;
-
+
macio = &macio_chips[0];
if (macio->type != macio_keylargo && macio->type != macio_pangea &&
macio->type != macio_intrepid)
return -ENODEV;
if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED))
return -ENODEV;
-
+
LOCK(flags);
if (value) {
UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW);
return -ENODEV;
if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED))
return -ENODEV;
-
+
LOCK(flags);
if (value) {
MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 0);
core99_read_gpio(struct device_node* node, int param, int value)
{
struct macio_chip* macio = &macio_chips[0];
-
+
return MACIO_IN8(param);
}
KL0_SCC_CELL_ENABLE |
KL0_IRDA_ENABLE | KL0_IRDA_CLK32_ENABLE |
KL0_IRDA_CLK19_ENABLE);
-
+
MACIO_BIC(KEYLARGO_MBCR, KL_MBCR_MB0_DEV_MASK);
MACIO_BIS(KEYLARGO_MBCR, KL_MBCR_MB0_IDE_ENABLE);
if (sleep_mode)
temp |= KL3_SHUTDOWN_PLL_TOTAL;
}
-
+
temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 |
KL3_SHUTDOWN_PLLKW35;
if (sleep_mode)
MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N);
MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
-
+
temp = MACIO_IN32(KEYLARGO_FCR3);
temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 |
KL3_SHUTDOWN_PLLKW35;
MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N);
MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
-
+
temp = MACIO_IN32(KEYLARGO_FCR3);
temp |= KL3_IT_SHUTDOWN_PLL1 | KL3_IT_SHUTDOWN_PLL2 |
KL3_IT_SHUTDOWN_PLL3;
if (macio->type != macio_keylargo && macio->type != macio_pangea &&
macio->type != macio_intrepid)
return -ENODEV;
-
+
/* We power off the wireless slot in case it was not done
* by the driver. We don't power it on automatically however
*/
/* We make sure the sound is off as well */
core99_sound_chip_enable(macio->of_node, 0, 0);
-
+
/*
* Save various bits of KeyLargo
*/
/* Save state & config of DBDMA channels */
dbdma_save(macio, save_dbdma);
-
+
/*
* Turn off as much as we can
*/
intrepid_shutdown(macio, 1);
else if (macio->type == macio_keylargo)
keylargo_shutdown(macio, 1);
-
- /*
+
+ /*
* Put the host bridge to sleep
*/
udelay(10);
UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING);
udelay(10);
-
+
/*
* Restore KeyLargo
*/
return pmac_mb.model_id;
case PMAC_MB_INFO_FLAGS:
return pmac_mb.board_flags;
- case PMAC_MB_INFO_NAME:
+ case PMAC_MB_INFO_NAME:
/* hack hack hack... but should work */
*((const char **)value) = pmac_mb.model_name;
break;
}
-/*
+/*
* Table definitions
*/
-
+
/* Used on any machine
*/
static struct feature_table_entry any_features[] __pmacdata = {
{ PMAC_FTR_WRITE_GPIO, core99_write_gpio },
{ 0, NULL }
};
-
+
static struct pmac_mb_def pmac_mb_defs[] __pmacdata = {
/* Warning: ordering is important as some models may claim
* beeing compatible with several types
int param, value, i;
feature_call func = NULL;
va_list args;
-
+
if (pmac_mb.features)
for (i=0; pmac_mb.features[i].function; i++)
if (pmac_mb.features[i].selector == selector) {
struct macio_chip* macio = &macio_chips[0];
const char* model = NULL;
struct device_node *dt;
-
+
/* Lookup known motherboard type in device-tree. First try an
* exact match on the "model" property, then try a "compatible"
* match is none is found.
if (model && (strncmp(model, "PowerBook", 9) == 0
|| strncmp(model, "iBook", 5) == 0))
pmac_mb.board_flags |= PMAC_MB_MOBILE;
-
-
+
+
printk(KERN_INFO "PowerMac motherboard: %s\n", pmac_mb.model_name);
return 0;
}
probe_uninorth(void)
{
unsigned long actrl;
-
+
/* Locate core99 Uni-N */
uninorth_node = find_devices("uni-n");
if (uninorth_node && uninorth_node->n_addrs > 0) {
uninorth_rev = in_be32(UN_REG(UNI_N_VERSION));
} else
uninorth_node = NULL;
-
+
if (!uninorth_node)
return;
-
+
printk(KERN_INFO "Found Uninorth memory controller & host bridge, revision: %d\n",
uninorth_rev);
printk(KERN_INFO "Mapped at 0x%08lx\n", (unsigned long)uninorth_base);
*/
if ((uninorth_rev >= 0x11 && uninorth_rev <= 0x24) || uninorth_rev == 0xc0)
UN_OUT(0x2160, UN_IN(0x2160) & 0x00ffffff);
-}
+}
static void __init
probe_one_macio(const char* name, const char* compat, int type)
int i;
volatile u32* base;
u32* revp;
-
+
node = find_devices(name);
if (!node || !node->n_addrs)
return;
char *conn;
int port_type = PMAC_SCC_ASYNC;
int modem = 0;
-
+
slots = (struct slot_names_prop *)get_property(np, "slot-names", &len);
conn = get_property(np, "AAPL,connector", &len);
if (conn && (strcmp(conn, "infrared") == 0))
set_initial_features(void)
{
struct device_node* np;
-
+
/* That hack appears to be necessary for some StarMax motherboards
* but I'm not too sure it was audited for side-effects on other
* ohare based machines...
while(np) {
if (np->parent
&& device_is_compatible(np->parent, "uni-north")
- && (device_is_compatible(np, "pci106b,18") ||
+ && (device_is_compatible(np, "pci106b,18") ||
device_is_compatible(np, "pci106b,30") ||
device_is_compatible(np, "pci11c1,5811"))) {
macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED;
}
np = np->next;
}
-
+
/* Enable ATA-100 before PCI probe. */
np = find_devices("ata-6");
while(np) {
}
np = np->next;
}
-
+
/* Switch airport off */
np = find_devices("radio");
while(np) {
pmac_feature_late_init(void)
{
struct device_node* np;
-
+
/* Request some resources late */
if (uninorth_node)
request_OF_resource(uninorth_node, 0, NULL);
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
- *
+ *
* Todo: - cleanup some coding horrors in the flash code
* - add support for the OF persistent properties
*/
}
low %= 65521UL;
high %= 65521UL;
-
+
return (high << 16) | low;
}
if (hdr99->hdr.signature != CORE99_SIGNATURE) {
#ifdef DEBUG
printk("Invalid signature\n");
-#endif
+#endif
return 0;
}
if (hdr99->hdr.cksum != chrp_checksum(&hdr99->hdr)) {
core99_erase_bank(int bank)
{
int stat, i;
-
+
u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
-
+
out_8(base, CORE99_FLASH_CMD_ERASE_SETUP);
out_8(base, CORE99_FLASH_CMD_ERASE_CONFIRM);
do { stat = in_8(base); }
core99_write_bank(int bank, u8* datas)
{
int i, stat = 0;
-
+
u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
-
+
for (i=0; i<NVRAM_SIZE; i++) {
out_8(base+i, CORE99_FLASH_CMD_WRITE_SETUP);
out_8(base+i, datas[i]);
printk("nvram: flash write failed !\n");
return -ENXIO;
}
- return 0;
+ return 0;
}
static void __init
nvram_partitions[pmac_nvram_XPRAM] = -1;
nvram_partitions[pmac_nvram_NR] = -1;
hdr = (struct chrp_header *)buffer;
-
+
offset = 0;
buffer[16] = 0;
do {
nvram_partitions[pmac_nvram_OF] = 0x1800;
nvram_partitions[pmac_nvram_XPRAM] = 0x1300;
nvram_partitions[pmac_nvram_NR] = 0x1400;
- }
+ }
#ifdef DEBUG
printk("nvram: OF partition at 0x%x\n", nvram_partitions[pmac_nvram_OF]);
printk("nvram: XP partition at 0x%x\n", nvram_partitions[pmac_nvram_XPRAM]);
printk("nvram: NR partition at 0x%x\n", nvram_partitions[pmac_nvram_NR]);
-#endif
+#endif
}
void __init
if (is_core_99) {
int i;
u32 gen_bank0, gen_bank1;
-
+
if (nvram_naddrs < 1) {
printk(KERN_ERR "nvram: no address\n");
return;
pmac_nvram_update(void)
{
struct core99_header* hdr99;
-
+
if (!is_core_99 || !nvram_data || !nvram_image)
return;
if (!memcmp(nvram_image, (u8*)nvram_data + core99_bank*NVRAM_SIZE,
pmac_xpram_read(int xpaddr)
{
int offset = nvram_partitions[pmac_nvram_XPRAM];
-
+
if (offset < 0)
return 0;
-
+
return pmac_nvram_read_byte(xpaddr + offset);
}
pmac_xpram_write(int xpaddr, u8 data)
{
int offset = nvram_partitions[pmac_nvram_XPRAM];
-
+
if (offset < 0)
return;
-
+
pmac_nvram_write_byte(data, xpaddr + offset);
}
/*
* Support for PCI bridges found on Power Macintoshes.
- *
+ *
* This includes support for bandit, chaos, grackle (motorola
* MPC106), and uninorth
*
{
for (; node != 0;node = node->sibling) {
int * bus_range;
- unsigned int *class_code;
+ unsigned int *class_code;
int len;
/* For PCI<->PCI bridges or CardBus bridges, we go down */
/* This routine fixes the "bus-range" property of all bridges in the
* system since they tend to have their "last" member wrong on macs
- *
+ *
* Note that the bus numbers manipulated here are OF bus numbers, they
* are not Linux bus numbers.
*/
{
int * bus_range;
int len;
-
- /* Lookup the "bus-range" property for the hose */
+
+ /* Lookup the "bus-range" property for the hose */
bus_range = (int *) get_property(bridge, "bus-range", &len);
if (bus_range == NULL || len < 2 * sizeof(int)) {
printk(KERN_WARNING "Can't get bus-range for %s\n",
/*
* Apple MacRISC (UniNorth, Bandit, Chaos) PCI controllers.
- *
+ *
* The "Bandit" version is present in all early PCI PowerMacs,
* and up to the first ones using Grackle. Some machines may
* have 2 bandit controllers (2 PCI busses).
- *
+ *
* "Chaos" is used in some "Bandit"-type machines as a bridge
* for the separate display bus. It is accessed the same
* way as bandit, but cannot be probed for devices. It therefore
|(((unsigned long)(devfn)) << 8) \
|(((unsigned long)(off)) & 0xFCUL) \
|1UL)
-
+
static unsigned int __pmac
macrisc_cfg_access(struct pci_controller* hose, u8 bus, u8 dev_fn, u8 offset)
{
unsigned int caddr;
-
+
if (bus == hose->first_busno) {
if (dev_fn < (11 << 3))
return 0;
caddr = MACRISC_CFA0(dev_fn, offset);
} else
caddr = MACRISC_CFA1(bus, dev_fn, offset);
-
+
/* Uninorth will return garbage if we don't read back the value ! */
do {
out_le32(hose->cfg_addr, caddr);
out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID);
udelay(2);
vendev = in_le32((volatile unsigned int *)bp->cfg_data);
- if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) +
+ if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) +
PCI_VENDOR_ID_APPLE) {
/* read the revision id */
out_le32(bp->cfg_addr,
if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) {
#ifdef DEBUG
printk("Can't find PCI infos for PCI<->PCI bridge\n");
-#endif
+#endif
return;
}
- /* Warning: At this point, we have not yet renumbered all busses.
+ /* Warning: At this point, we have not yet renumbered all busses.
* So we must use OF walking to find out hose
*/
hose = pci_find_hose_for_OF_device(p2pbridge);
if (!hose) {
#ifdef DEBUG
printk("Can't find hose for PCI<->PCI bridge\n");
-#endif
+#endif
return;
}
if (early_read_config_word(hose, bus, devfn,
char* disp_name;
int *bus_range;
int first = 1, primary;
-
+
for (; dev != NULL; dev = dev->next) {
addr = (struct reg_property *) get_property(dev, "reg", &len);
if (addr == NULL || len < sizeof(*addr)) {
printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
dev->full_name);
}
-
+
hose = pcibios_alloc_controller();
if (!hose)
continue;
#ifdef DEBUG
printk(" ->Hose at 0x%08lx, cfg_addr=0x%08lx,cfg_data=0x%08lx\n",
hose, hose->cfg_addr, hose->cfg_data);
-#endif
-
+#endif
+
/* Interpret the "ranges" property */
/* This also maps the I/O region and sets isa_io/mem_base */
pci_process_bridge_OF_ranges(hose, dev, primary);
static void __init
pcibios_fixup_OF_interrupts(void)
-{
+{
struct pci_dev* dev = NULL;
-
+
/*
* Open Firmware often doesn't initialize the
* PCI_INTERRUPT_LINE config register properly, so we
uninorth_child = node->parent &&
device_is_compatible(node->parent, "uni-north");
-
+
/* Firewire & GMAC were disabled after PCI probe, the driver is
* claiming them, we must re-enable them now.
*/
- if (uninorth_child && !strcmp(node->name, "firewire") &&
- (device_is_compatible(node, "pci106b,18") ||
+ if (uninorth_child && !strcmp(node->name, "firewire") &&
+ (device_is_compatible(node, "pci106b,18") ||
device_is_compatible(node, "pci106b,30") ||
device_is_compatible(node, "pci11c1,5811"))) {
pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1);
pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1);
updatecfg = 1;
}
- if (uninorth_child && !strcmp(node->name, "ethernet") &&
+ if (uninorth_child && !strcmp(node->name, "ethernet") &&
device_is_compatible(node, "gmac")) {
pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1);
updatecfg = 1;
if (updatecfg) {
u16 cmd;
-
+
/*
* Make sure PCI is correctly configured
*
* We use old pci_bios versions of the function since, by
* default, gmac is not powered up, and so will be absent
- * from the kernel initial PCI lookup.
- *
+ * from the kernel initial PCI lookup.
+ *
* Should be replaced by 2.4 new PCI mecanisms and really
* regiser the device.
*/
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16);
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
}
-
+
return 0;
}
/* OF fails to initialize IDE controllers on macs
* (and maybe other machines)
- *
+ *
* Ideally, this should be moved to the IDE layer, but we need
* to check specifically with Andre Hedrick how to do it cleanly
* since the common IDE code seem to care about the fact that the
* BIOS may have disabled a controller.
- *
+ *
* -- BenH
*/
while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
* XXX this should be in xmon.h, but putting it there means xmon.h
* has to include <linux/interrupt.h> (to get irqreturn_t), which
* causes all sorts of problems. -- paulus
- */
+ */
extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);
struct pmac_irq_hw {
static irqreturn_t gatwick_action(int cpl, void *dev_id, struct pt_regs *regs)
{
int irq, bits;
-
+
for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
int i = irq >> 5;
bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
#ifdef CONFIG_SMP
void psurge_smp_message_recv(struct pt_regs *);
-
+
/* IPI's are a hack on the powersurge -- Cort */
if ( smp_processor_id() != 0 ) {
psurge_smp_message_recv(regs);
{
struct device_node *node;
int count;
-
+
memset(gatwick_int_pool, 0, sizeof(gatwick_int_pool));
node = gw->child;
count = 0;
node->child->intrs = &gatwick_int_pool[count];
count += 3;
}
- node->child->n_intrs = 3;
+ node->child->n_intrs = 3;
node->child->intrs[0].line = 15+irq_base;
node->child->intrs[1].line = 4+irq_base;
node->child->intrs[2].line = 5+irq_base;
node->intrs[0].line = 29+irq_base;
printk(KERN_INFO "irq: fixed media-bay on second controller (%d)\n",
node->intrs[0].line);
-
+
ya_node = node->child;
while(ya_node)
{
ya_node->intrs[1].line = 1+irq_base;
printk(KERN_INFO "irq: fixed floppy on second controller (%d,%d)\n",
ya_node->intrs[0].line, ya_node->intrs[1].line);
- }
+ }
if (strcasecmp(ya_node->name, "ata4") == 0) {
if (ya_node->n_intrs < 2) {
ya_node->intrs = &gatwick_int_pool[count];
ya_node->intrs[1].line = 3+irq_base;
printk(KERN_INFO "irq: fixed ide on second controller (%d,%d)\n",
ya_node->intrs[0].line, ya_node->intrs[1].line);
- }
+ }
ya_node = ya_node->sibling;
}
}
struct device_node *irqctrler;
unsigned long addr;
int irq_cascade = -1;
-
+
/* We first try to detect Apple's new Core99 chipset, since mac-io
* is quite different on those machines and contains an IBM MPIC2.
*/
/*
* G3 powermacs and 1999 G3 PowerBooks have 64 interrupts,
- * 1998 G3 Series PowerBooks have 128,
+ * 1998 G3 Series PowerBooks have 128,
* other powermacs have 32.
* The combo ethernet/modem card for the Powerstar powerbooks
* (2400/3400/3500, ohare based) has a second ohare chip
/* get addresses of first controller */
if (irqctrler) {
if (irqctrler->n_addrs > 0) {
- addr = (unsigned long)
+ addr = (unsigned long)
ioremap(irqctrler->addrs[0].address, 0x40);
for (i = 0; i < 2; ++i)
pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
(addr + (2 - i) * 0x10);
}
-
+
/* get addresses of second controller */
irqctrler = irqctrler->next;
if (irqctrler && irqctrler->n_addrs > 0) {
- addr = (unsigned long)
+ addr = (unsigned long)
ioremap(irqctrler->addrs[0].address, 0x40);
for (i = 2; i < 4; ++i)
pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
for (i = 0; i < max_irqs; i++)
if (level_mask[i >> 5] & (1UL << (i & 0x1f)))
irq_desc[i].status = IRQ_LEVEL;
-
+
/* get interrupt line of secondary interrupt controller */
if (irq_cascade >= 0) {
printk(KERN_INFO "irq: secondary controller on irq %d\n",
static int pmacpic_find_viaint(void)
{
int viaint = -1;
-
+
#ifdef CONFIG_ADB_PMU
struct device_node *np;
static int pmacpic_suspend(struct sys_device *sysdev, u32 state)
{
int viaint = pmacpic_find_viaint();
-
+
sleep_save_mask[0] = ppc_cached_irq_mask[0];
sleep_save_mask[1] = ppc_cached_irq_mask[1];
ppc_cached_irq_mask[0] = 0;
#ifdef CONFIG_PM
.suspend = &pmacpic_suspend,
.resume = &pmacpic_resume,
-#endif /* CONFIG_PM */
+#endif /* CONFIG_PM */
};
static int __init init_pmacpic_sysfs(void)
/*
* arch/ppc/platforms/setup.c
*
- * PowerPC version
+ * PowerPC version
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
* Adapted for Power Macintosh by Paul Mackerras
if (pmac_call_feature(PMAC_FTR_GET_MB_INFO, NULL, PMAC_MB_INFO_NAME, (int)&mbname) != 0)
mbname = "Unknown";
-
+
/* find motherboard type */
seq_printf(m, "machine\t\t: ");
np = find_devices("device-tree");
/* print parsed model */
seq_printf(m, "detected as\t: %d (%s)\n", mbmodel, mbname);
seq_printf(m, "pmac flags\t: %08x\n", mbflags);
-
+
/* find l2 cache info */
np = find_devices("l2-cache");
if (np == 0)
int n;
struct reg_property *reg = (struct reg_property *)
get_property(np, "reg", &n);
-
+
if (reg != 0) {
unsigned long total = 0;
}
/* Checks "l2cr-value" property in the registry */
- np = find_devices("cpus");
+ np = find_devices("cpus");
if (np == 0)
- np = find_type_devices("cpu");
+ np = find_type_devices("cpu");
if (np != 0) {
unsigned int *l2cr = (unsigned int *)
get_property(np, "l2cr-value", NULL);
seq_printf(m, "l2cr override\t: 0x%x\n", *l2cr);
}
}
-
+
/* Indicate newworld/oldworld */
seq_printf(m, "pmac-generation\t: %s\n",
pmac_newworld ? "NewWorld" : "OldWorld");
-
+
return 0;
}
struct device_node *cpu;
int *fp;
unsigned long pvr;
-
+
pvr = PVR_VER(mfspr(PVR));
/* Set loops_per_jiffy to a half-way reasonable value,
/* Lookup PCI hosts */
pmac_find_bridges();
-
+
/* Checks "l2cr-value" property in the registry */
if (cur_cpu_spec[0]->cpu_features & CPU_FTR_L2CR) {
- struct device_node *np = find_devices("cpus");
+ struct device_node *np = find_devices("cpus");
if (np == 0)
- np = find_type_devices("cpu");
+ np = find_type_devices("cpu");
if (np != 0) {
unsigned int *l2cr = (unsigned int *)
get_property(np, "l2cr-value", NULL);
printk(KERN_INFO "L2CR overriden (0x%x), backside cache is %s\n",
ppc_override_l2cr_value, (ppc_override_l2cr_value & 0x80000000)
? "enabled" : "disabled");
-
+
#ifdef CONFIG_KGDB
zs_kgdb_hook(0);
#endif
printk("WARNING ! Your machine is Cuda based but your kernel\n");
printk(" wasn't compiled with CONFIG_ADB_CUDA option !\n");
}
-#endif
+#endif
#ifdef CONFIG_ADB_PMU
find_via_pmu();
#else
printk("WARNING ! Your machine is PMU based but your kernel\n");
printk(" wasn't compiled with CONFIG_ADB_PMU option !\n");
}
-#endif
+#endif
#ifdef CONFIG_NVRAM
pmac_nvram_init();
#endif
#ifdef CONFIG_NVRAM
pmac_nvram_update();
#endif
-
+
switch (sys_ctrler) {
#ifdef CONFIG_ADB_CUDA
case SYS_CTRLER_CUDA:
cuda_poll();
break;
#endif /* CONFIG_ADB_CUDA */
-#ifdef CONFIG_ADB_PMU
+#ifdef CONFIG_ADB_PMU
case SYS_CTRLER_PMU:
pmu_restart();
break;
-#endif /* CONFIG_ADB_PMU */
+#endif /* CONFIG_ADB_PMU */
default: ;
}
}
#ifdef CONFIG_NVRAM
pmac_nvram_update();
#endif
-
+
switch (sys_ctrler) {
#ifdef CONFIG_ADB_CUDA
case SYS_CTRLER_CUDA:
ppc_md.irq_canonicalize = NULL;
ppc_md.init_IRQ = pmac_pic_init;
ppc_md.get_irq = pmac_get_irq; /* Changed later on ... */
-
+
ppc_md.pcibios_fixup = pmac_pcibios_fixup;
ppc_md.pcibios_enable_device_hook = pmac_pci_enable_device_hook;
ppc_md.pcibios_after_init = pmac_pcibios_after_init;
#endif /* CONFIG_BOOTX_TEXT */
if (ppc_md.progress) ppc_md.progress("pmac_init(): exit", 0);
-
+
}
#ifdef CONFIG_BOOTX_TEXT
mftbu r3
cmpw r3,r4
bne 1b
-
+
/* Save SPRGs */
mfsprg r4,0
stw r4,SL_SPRG0(r1)
sync
mtspr SPRN_HID0,r3
sync
-
+
/* Turn off data relocation. */
mfmsr r3 /* Save MSR in r7 */
rlwinm r3,r3,0,28,26 /* Turn off DR bit */
isync
b 1b
-/*
+/*
* Here is the resume code.
*/
/* Won't that cause problems on CPU that doesn't support it ? */
lis r3, 0
mtspr SPRN_MMCR0, r3
-
+
/* sanitize MSR */
mfmsr r3
ori r3,r3,MSR_EE|MSR_IP
lwz r1,0(r3)
/* Pass thru to older resume code ... */
-/*
+/*
* Here is the resume code for older machines.
* r1 has the physical address of SL_PC(sp).
*/
-
+
grackle_wake_up:
/* Invalidate & enable L1 cache, we don't care about
* whatever the ROM may have tried to write to memory
bdnz 3b
sync
isync
-
+
subi r1,r1,SL_PC
/* Restore various CPU config stuffs */
/* restore the MSR and turn on the MMU */
lwz r3,SL_MSR(r1)
- bl turn_on_mmu
+ bl turn_on_mmu
/* get back the stack pointer */
tovirt(r1,r1)
*
* We support both the old "powersurge" SMP architecture
* and the current Core99 (G4 PowerMac) machines.
- *
+ *
* Note that we don't support the very first rev. of
* Apple/DayStar 2 CPUs board, the one with the funky
* watchdog. Hopefully, none of these should be there except
local_irq_save(flags);
local_irq_disable();
-
+
/* Save reset vector */
save_vector = *vector;
-
- /* Setup fake reset vector that does
+
+ /* Setup fake reset vector that does
* b __secondary_start_psurge - KERNELBASE
- */
+ */
switch(nr) {
case 1:
new_vector = (unsigned long)__secondary_start_psurge;
break;
}
*vector = 0x48000002 + new_vector - KERNELBASE;
-
+
/* flush data cache and inval instruction cache */
flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
-
+
/* Put some life in our friend */
pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
-
+
/* FIXME: We wait a bit for the CPU to take the exception, I should
* instead wait for the entry code to set something for me. Well,
* ideally, all that crap will be done in prom.c and the CPU left
* in a RAM-based wait loop like CHRP.
*/
mdelay(1);
-
+
/* Restore our exception vector */
*vector = save_vector;
flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
-
+
local_irq_restore(flags);
if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
}
/* Setup some registers */
if (cpu_nr != 0)
core99_init_caches(cpu_nr);
-
+
/* Setup openpic */
do_openpic_setup_cpu();
/*
* arch/ppc/platforms/powerpmc250.c
- *
+ *
* Board setup routines for Force PowerPMC-250 Processor PMC
*
* Author: Troy Benjegerdes <tbenjegerdes@mvista.com>
{
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
-
+
/* Lookup PCI host bridges */
powerpmc250_find_bridges();
-
+
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
}
#endif
-static void __init
+static void __init
powerpmc250_calibrate_decr(void)
{
unsigned long freq;
/* yuck, better hope your ram size is a power of 2 -- paulus */
powerpmc250_set_bat();
- return mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
+ return mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
}
static void __init
*(char *)(r7 + KERNELBASE) = 0;
strcpy(cmd_line, (char *)(r6 + KERNELBASE));
}
-
+
isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
- pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
+ pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
ppc_md.setup_arch = powerpmc250_setup_arch;
ppc_md.show_cpuinfo = powerpmc250_show_cpuinfo;
ppc_md.find_end_of_memory = powerpmc250_find_end_of_memory;
ppc_md.setup_io_mappings = powerpmc250_map_io;
-
+
ppc_md.restart = powerpmc250_restart;
ppc_md.power_off = powerpmc250_power_off;
ppc_md.halt = powerpmc250_halt;
/*
* (This used to be arch/ppc/platforms/powerpmc250_pci.c)
- *
+ *
* PCI support for Force PowerPMC250
*
*/
#define DBG(x...) printk(x)
#else
#define DBG(x...)
-#endif /* DEBUG */
+#endif /* DEBUG */
static inline int __init
powerpmc250_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
- */
+ */
{
{17, 0, 0, 0}, /* Device 11 - 82559 */
{0, 0, 0, 0}, /* 12 */
return PCI_IRQ_TABLE_LOOKUP;
};
-static int
+static int
powerpmc250_exclude_device(u_char bus, u_char devfn)
{
/*
* device on the PCI Bus, will create an incorrect response and
* later will respond incorrectly to Configuration read coming
* from another device.
- *
+ *
* The work around is that when doing a PCI Scan one
* should skip its own device number in the scan.
- *
+ *
* The top IDsel is AD13 and the middle is AD14.
*
* -- Note from force
*/
-
+
if ((bus == 0) && (PCI_SLOT(devfn) == 13 || PCI_SLOT(devfn) == 14)) {
return PCIBIOS_DEVICE_NOT_FOUND;
}
hose->mem_resources[0].end = 0xffffffff;
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
-
+
/* ppc_md.pcibios_fixup = pcore_pcibios_fixup; */
ppc_md.pci_swizzle = common_swizzle;
-
+
ppc_md.pci_exclude_device = powerpmc250_exclude_device;
ppc_md.pci_map_irq = powerpmc250_map_irq;
} else {
/*
* include/asm-ppc/platforms/powerpmc250.h
- *
+ *
* Definitions for Force PowerPMC-250 board support
*
* Author: Troy Benjegerdes <tbenjegerdes@mvista.com>
- *
+ *
* Borrowed heavily from prpmc750.h by Matt Porter <mporter@mvista.com>
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
/*
* include/asm-ppc/platforms/powerpmc250_serial.h
- *
+ *
* Motorola PrPMC750 serial support
*
* Author: Troy Benjegerdes <tbenjegerdes@mvista.com>
unsigned char *Motherboard_map_name;
-/* Tables for known hardware */
+/* Tables for known hardware */
/* Motorola Mesquite */
static inline int
/* 2300
* Raven 31
* ISA 11
- * Univ 13
+ * Univ 13
* eth 14 - IRQ2
* PMC1 16 - 9,10,11,12 = A-D
* PMC2 17 - 9,10,11,12 = B,C,D,A
* Perform specific configuration for the Via Tech or
* or Winbond PCI-ISA-Bridge part.
*/
- if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
+ if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_82C586_1, dev))) {
/*
* PPCBUG does not set the enable bits
pplus_set_VIA_IDE_legacy();
- hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
+ hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pcibios_fixup = pplus_pcibios_fixup;
ppc_md.pci_swizzle = common_swizzle;
if ( ppc_md.progress )
ppc_md.progress("pplus_setup_arch: find_bridges\n", 0);
-
+
/* Setup PCI host bridge */
pplus_setup_hose();
-
+
/* Set up floppy in PS/2 mode */
outb(0x09, SIO_CONFIG_RA);
reg = inb(SIO_CONFIG_RD);
conswitchp = &dummy_con;
#endif
#ifdef CONFIG_PPCBUG_NVRAM
- /* Read in NVRAM data */
+ /* Read in NVRAM data */
init_prep_nvram();
/* if no bootargs, look in NVRAM */
openpic_init(1, NUM_8259_INTERRUPTS, 0, -1);
for ( i = 0 ; i < NUM_8259_INTERRUPTS ; i++ )
irq_desc[i].handler = &i8259_pic;
- i8259_init(NULL);
+ i8259_init(NULL);
}
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
/*
* IDE stuff.
*/
-static int
+static int
pplus_ide_default_irq(unsigned long base)
{
switch (base) {
}
}
-static unsigned long
+static unsigned long
pplus_ide_default_io_base(int index)
{
switch (index) {
/* Used for Motorola to store system config register */
static unsigned long *ProcInfo;
-/* Tables for known hardware */
+/* Tables for known hardware */
/* Motorola PowerStackII - Utah */
static char Utah_pci_IRQ_map[23] __prepdata =
15, /* Line 3 */
15 /* Line 4 */
};
-
+
/* Motorola Mesquite */
static char Mesquite_pci_IRQ_map[23] __prepdata =
{
{
0, /* This is a dummy structure */
};
-
+
/* Motorola MVME16xx */
static char Genesis_pci_IRQ_map[16] __prepdata =
{
14, /* Line 3 */
15 /* Line 4 */
};
-
+
static char Genesis2_pci_IRQ_map[23] __prepdata =
{
0, /* Slot 0 - unused */
OpenPIC_NumInitSenses = sizeof(prep_openpic_initsenses);
ppc_md.get_irq = openpic_get_irq;
-
+
/* If raven is present on Motorola store the system config register
* for later use.
*/
unsigned char *ibc_pirq = (unsigned char *)0x80800860;
unsigned char *ibc_pcicon = (unsigned char *)0x80800840;
int i;
-
+
if ( _prep_type == _PREP_Motorola)
{
unsigned short irq_mode;
printk("No known machine pci routing!\n");
return;
}
-
+
/* Set up mapping from slots */
for (i = 1; i <= 4; i++)
ibc_pirq[i-1] = Motherboard_routes[i];
* Perform specific configuration for the Via Tech or
* or Winbond PCI-ISA-Bridge part.
*/
- if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
+ if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_82C586_1, dev))) {
/*
* PPCBUG does not set the enable bits
* the devfn of the bus bridge with secondary inputs, use those.
* Otherwise, assume it's a PMC site and get the interrupt line
* value from the interrupt routing table.
- */
+ */
if (mot_info[mot_entry].secondary_bridge_devfn) {
pbus = dev->bus;
{
#if 0
struct pci_dev *dev;
-
- /* If there is a WD 90C, reset the IO BAR to 0x0 (it started that
+
+ /* If there is a WD 90C, reset the IO BAR to 0x0 (it started that
* way, but the PCI layer relocated it because it thought 0x0 was
* invalid for a BAR).
* If you don't do this, the card's VGA base will be <IO BAR>+0xc0000
PREP_ISA_IO_BASE + 0xcfc);
printk("PReP architecture\n");
-#ifdef CONFIG_PREP_RESIDUAL
+#ifdef CONFIG_PREP_RESIDUAL
{
PPC_DEVICE *hostbridge;
3, 0);
if(pkt) {
#define p pkt->L4_Pack.L4_Data.L4_PPCPack
- setup_indirect_pci(hose,
+ setup_indirect_pci(hose,
ld_le32((unsigned *) (p.PPCData)),
ld_le32((unsigned *) (p.PPCData+8)));
#undef p
/* for the mac fs */
dev_t boot_dev;
-#ifdef CONFIG_SOUND_CS4232
+#ifdef CONFIG_SOUND_CS4232
long ppc_cs4232_dma, ppc_cs4232_dma2;
#endif
extern int probingmem;
extern unsigned long loops_per_jiffy;
-#ifdef CONFIG_SOUND_CS4232
+#ifdef CONFIG_SOUND_CS4232
EXPORT_SYMBOL(ppc_cs4232_dma);
EXPORT_SYMBOL(ppc_cs4232_dma2);
#endif
/* print info about the SCSI fuse */
seq_printf(m, "scsi fuse\t: ");
- if (equip_reg & PREP_IBM_EQUIPMENT_SCSIFUSE)
+ if (equip_reg & PREP_IBM_EQUIPMENT_SCSIFUSE)
seq_printf(m, "ok");
else
seq_printf(m, "bad");
for (i = 0; (res->ActualNumMemories) && (i < MAX_MEMS); i++) {
if (res->Memories[i].SIMMSize != 0)
seq_printf(m, "%d:%ldMiB ", i,
- (res->Memories[i].SIMMSize > 1024) ?
- res->Memories[i].SIMMSize>>20 :
+ (res->Memories[i].SIMMSize > 1024) ?
+ res->Memories[i].SIMMSize>>20 :
res->Memories[i].SIMMSize);
}
seq_printf(m, "\n");
seq_printf(m, "async, ");
else
seq_printf(m, "sync burst, ");
-
+
if (l2_reg & 0x4)
seq_printf(m, "parity, ");
else
seq_printf(m, "no parity, ");
-
+
switch (l2_reg & 0x3) {
case 0x0:
seq_printf(m, "256KiB\n");
for (i = 0; (res->ActualNumMemories) && (i < MAX_MEMS); i++) {
if (res->Memories[i].SIMMSize != 0)
seq_printf(m, "%d:%ldM ", i,
- (res->Memories[i].SIMMSize > 1024) ?
- res->Memories[i].SIMMSize>>20 :
+ (res->Memories[i].SIMMSize > 1024) ?
+ res->Memories[i].SIMMSize>>20 :
res->Memories[i].SIMMSize);
}
seq_printf(m, "\n");
{
/* PREP's without residual data will give incorrect values here */
seq_printf(m, "clock\t\t: ");
-#ifdef CONFIG_PREP_RESIDUAL
+#ifdef CONFIG_PREP_RESIDUAL
if (res->ResidualLength)
seq_printf(m, "%ldMHz\n",
(res->VitalProductData.ProcessorHz > 1024) ?
return 0;
}
-#ifdef CONFIG_SOUND_CS4232
+#ifdef CONFIG_SOUND_CS4232
static long __init masktoint(unsigned int i)
{
int t = -1;
/*
* ppc_cs4232_dma and ppc_cs4232_dma2 are used in include/asm/dma.h
- * to distinguish sound dma-channels from others. This is because
+ * to distinguish sound dma-channels from others. This is because
* blocksize on 16 bit dma-channels 5,6,7 is 128k, but
* the cs4232.c uses 64k like on 8 bit dma-channels 0,1,2,3
*/
/*
* Get the needed resource informations from residual data.
- *
+ *
*/
#ifdef CONFIG_PREP_RESIDUAL
audiodevice = residual_find_device(~0, NULL, MultimediaController,
/*
* These are the PReP specs' defaults for the cs4231. We use these
* as fallback incase we don't have residual data.
- * At least the IBM Thinkpad 850 with IDE DMA Channels at 6 and 7
+ * At least the IBM Thinkpad 850 with IDE DMA Channels at 6 and 7
* will use the other values.
*/
if (audiodevice == NULL) {
ppc_cs4232_dma = 1;
ppc_cs4232_dma2 = -1;
break;
- default:
+ default:
ppc_cs4232_dma = 6;
ppc_cs4232_dma2 = 7;
}
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000;
-
+
/* Lookup PCI host bridges */
prep_find_bridges();
-
+
/* Set up floppy in PS/2 mode */
outb(0x09, SIO_CONFIG_RA);
reg = inb(SIO_CONFIG_RD);
break;
}
- /* Read in NVRAM data */
+ /* Read in NVRAM data */
init_prep_nvram();
/* if no bootargs, look in NVRAM */
}
}
-#ifdef CONFIG_SOUND_CS4232
+#ifdef CONFIG_SOUND_CS4232
prep_init_sound();
#endif /* CONFIG_SOUND_CS4232 */
tb_ticks_per_jiffy = freq / HZ / divisor;
return 0;
} else
-#endif
+#endif
return 1;
}
tmp = ppc_md.nvram_read_val(MK48T59_RTC_CONTROLB);
if (tmp & MK48T59_RTC_CB_STOP) {
printk("Warning: RTC was stopped, date will be wrong.\n");
- ppc_md.nvram_write_val(MK48T59_RTC_CONTROLB,
+ ppc_md.nvram_write_val(MK48T59_RTC_CONTROLB,
tmp & ~MK48T59_RTC_CB_STOP);
/* Low frequency crystal oscillators may take a very long
* time to startup and stabilize. For now just ignore the
* the issue, but attempting to calibrate the decrementer
- * from the RTC just after this wakeup is likely to be very
+ * from the RTC just after this wakeup is likely to be very
* inaccurate. Firmware should not allow to load
* the OS with the clock stopped anyway...
*/
unsigned char save_control;
long i;
unsigned char sec;
-
-
+
+
/* Make sure the time is not stopped. */
save_control = ppc_md.nvram_read_val(MK48T59_RTC_CONTROLB);
-
+
ppc_md.nvram_write_val(MK48T59_RTC_CONTROLA,
(save_control & (~MK48T59_RTC_CB_STOP)));
prep_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
-#ifdef CONFIG_PREP_RESIDUAL
+#ifdef CONFIG_PREP_RESIDUAL
/* make a copy of residual data */
if ( r3 ) {
memcpy((void *)res,(void *)(r3+KERNELBASE),
DMA_MODE_WRITE = 0x48;
/* figure out what kind of prep workstation we are */
-#ifdef CONFIG_PREP_RESIDUAL
+#ifdef CONFIG_PREP_RESIDUAL
if ( res->ResidualLength != 0 ) {
if ( !strncmp(res->VitalProductData.PrintableModel,"IBM",3) )
_prep_type = _PREP_IBM;
/* Since the UIP flag is set for about 2.2 ms and the clock
* is typically written with a precision of 1 jiffy, trying
- * to obtain a precision better than a few milliseconds is
+ * to obtain a precision better than a few milliseconds is
* an illusion. Only consistency is interesting, this also
* allows to use the routine for /dev/rtc without a potential
- * 1 second kernel busy loop triggered by any reader of /dev/rtc.
+ * 1 second kernel busy loop triggered by any reader of /dev/rtc.
*/
for ( i = 0; i<1000000; i++) {
/* Tokens for indicators */
#define TONE_FREQUENCY 0x0001 /* 0 - 1000 (HZ)*/
#define TONE_VOLUME 0x0002 /* 0 - 100 (%) */
-#define SYSTEM_POWER_STATE 0x0003
+#define SYSTEM_POWER_STATE 0x0003
#define WARNING_LIGHT 0x0004
#define DISK_ACTIVITY_LIGHT 0x0005
#define HEX_DISPLAY_UNIT 0x0006
/* 9006 - 9999: Vendor specific */
/* other */
-#define MAX_SENSORS 17 /* I only know of 17 sensors */
+#define MAX_SENSORS 17 /* I only know of 17 sensors */
#define MAX_LINELENGTH 256
#define SENSOR_PREFIX "ibm,sensor-"
#define cel_to_fahr(x) ((x*9/5)+32)
/* Declarations */
static int ppc_rtas_sensor_read(char * buf, char ** start, off_t off,
int count, int *eof, void *data);
-static ssize_t ppc_rtas_clock_read(struct file * file, char * buf,
+static ssize_t ppc_rtas_clock_read(struct file * file, char * buf,
size_t count, loff_t *ppos);
-static ssize_t ppc_rtas_clock_write(struct file * file, const char * buf,
+static ssize_t ppc_rtas_clock_write(struct file * file, const char * buf,
size_t count, loff_t *ppos);
static ssize_t ppc_rtas_progress_read(struct file * file, char * buf,
size_t count, loff_t *ppos);
};
int ppc_rtas_find_all_sensors (void);
-int ppc_rtas_process_sensor(struct individual_sensor s, int state,
+int ppc_rtas_process_sensor(struct individual_sensor s, int state,
int error, char * buf);
char * ppc_rtas_process_error(int error);
int get_location_code(struct individual_sensor s, char * buf);
if ((rtas == 0) || (_machine != _MACH_chrp)) {
return;
}
-
+
proc_rtas = proc_mkdir("rtas", 0);
if (proc_rtas == 0)
return;
entry = create_proc_entry("progress", S_IRUGO|S_IWUSR, proc_rtas);
if (entry) entry->proc_fops = &ppc_rtas_progress_operations;
- entry = create_proc_entry("clock", S_IRUGO|S_IWUSR, proc_rtas);
+ entry = create_proc_entry("clock", S_IRUGO|S_IWUSR, proc_rtas);
if (entry) entry->proc_fops = &ppc_rtas_clock_operations;
- entry = create_proc_entry("poweron", S_IWUSR|S_IRUGO, proc_rtas);
+ entry = create_proc_entry("poweron", S_IWUSR|S_IRUGO, proc_rtas);
if (entry) entry->proc_fops = &ppc_rtas_poweron_operations;
- create_proc_read_entry("sensors", S_IRUGO, proc_rtas,
+ create_proc_read_entry("sensors", S_IRUGO, proc_rtas,
ppc_rtas_sensor_read, NULL);
-
- entry = create_proc_entry("frequency", S_IWUSR|S_IRUGO, proc_rtas);
+
+ entry = create_proc_entry("frequency", S_IWUSR|S_IRUGO, proc_rtas);
if (entry) entry->proc_fops = &ppc_rtas_tone_freq_operations;
- entry = create_proc_entry("volume", S_IWUSR|S_IRUGO, proc_rtas);
+ entry = create_proc_entry("volume", S_IWUSR|S_IRUGO, proc_rtas);
if (entry) entry->proc_fops = &ppc_rtas_tone_volume_operations;
}
to_tm(nowtime, &tm);
- error = call_rtas("set-time-for-power-on", 7, 1, NULL,
- tm.tm_year, tm.tm_mon, tm.tm_mday,
+ error = call_rtas("set-time-for-power-on", 7, 1, NULL,
+ tm.tm_year, tm.tm_mon, tm.tm_mday,
tm.tm_hour, tm.tm_min, tm.tm_sec, 0 /* nano */);
if (error != 0)
- printk(KERN_WARNING "error: setting poweron time returned: %s\n",
+ printk(KERN_WARNING "error: setting poweron time returned: %s\n",
ppc_rtas_process_error(error));
return count;
}
strcpy(progress_led, buf); /* save the string */
/* Lets see if the user passed hexdigits */
hex = simple_strtoul(buf, NULL, 10);
-
+
ppc_md.progress ((char *)buf, hex);
return count;
/* ****************************************************************** */
/* CLOCK */
/* ****************************************************************** */
-static ssize_t ppc_rtas_clock_write(struct file * file, const char * buf,
+static ssize_t ppc_rtas_clock_write(struct file * file, const char * buf,
size_t count, loff_t *ppos)
{
struct rtc_time tm;
}
to_tm(nowtime, &tm);
- error = call_rtas("set-time-of-day", 7, 1, NULL,
- tm.tm_year, tm.tm_mon, tm.tm_mday,
+ error = call_rtas("set-time-of-day", 7, 1, NULL,
+ tm.tm_year, tm.tm_mon, tm.tm_mday,
tm.tm_hour, tm.tm_min, tm.tm_sec, 0);
if (error != 0)
- printk(KERN_WARNING "error: setting the clock returned: %s\n",
+ printk(KERN_WARNING "error: setting the clock returned: %s\n",
ppc_rtas_process_error(error));
return count;
}
/* ****************************************************************** */
-static ssize_t ppc_rtas_clock_read(struct file * file, char * buf,
+static ssize_t ppc_rtas_clock_read(struct file * file, char * buf,
size_t count, loff_t *ppos)
{
unsigned int year, mon, day, hour, min, sec;
int n, error;
error = call_rtas("get-time-of-day", 0, 8, ret);
-
+
year = ret[0]; mon = ret[1]; day = ret[2];
hour = ret[3]; min = ret[4]; sec = ret[5];
if (error != 0){
- printk(KERN_WARNING "error: reading the clock returned: %s\n",
+ printk(KERN_WARNING "error: reading the clock returned: %s\n",
ppc_rtas_process_error(error));
n = sprintf (buf, "0");
- } else {
+ } else {
n = sprintf (buf, "%lu\n", mktime(year, mon, day, hour, min, sec));
}
kfree(ret);
j = sensors.sensor[i].quant;
/* A sensor may have multiple instances */
while (j >= 0) {
- error = call_rtas("get-sensor-state", 2, 2, &ret,
+ error = call_rtas("get-sensor-state", 2, 2, &ret,
sensors.sensor[i].token, sensors.sensor[i].quant-j);
state = (int) ret;
n += ppc_rtas_process_sensor(sensors.sensor[i], state, error, buffer+n );
* Builds a string out of what the sensor said
*/
-int ppc_rtas_process_sensor(struct individual_sensor s, int state,
- int error, char * buf)
+int ppc_rtas_process_sensor(struct individual_sensor s, int state,
+ int error, char * buf)
{
/* Defined return vales */
const char * key_switch[] = { "Off\t", "Normal\t", "Secure\t", "Mainenance" };
const char * lid_status[] = { " ", "Open", "Closed" };
const char * power_source[] = { "AC\t", "Battery", "AC & Battery" };
const char * battery_remaining[] = { "Very Low", "Low", "Mid", "High" };
- const char * epow_sensor[] = {
+ const char * epow_sensor[] = {
"EPOW Reset", "Cooling warning", "Power warning",
"System shutdown", "System halt", "EPOW main enclosure",
"EPOW power off" };
/* ****************************************************************** */
-/*
- * Format:
+/*
+ * Format:
* ${LETTER}${NUMBER}[[-/]${LETTER}${NUMBER} [ ... ] ]
* the '.' may be an abbrevation
*/
len = strlen(tmp);
while (strlen(tmp) < 4)
n += sprintf (tmp+n, "0");
-
+
/* invert the string */
while (tmp[i]) {
if (i<len)
error = call_rtas("set-indicator", 3, 1, NULL,
TONE_FREQUENCY, 0, freq);
if (error != 0)
- printk(KERN_WARNING "error: setting tone frequency returned: %s\n",
+ printk(KERN_WARNING "error: setting tone frequency returned: %s\n",
ppc_rtas_process_error(error));
return count;
}
}
if (volume < 0) volume = 0;
if (volume > 100) volume = 100;
-
+
rtas_tone_volume = volume; /* save it for later */
error = call_rtas("set-indicator", 3, 1, NULL,
TONE_VOLUME, 0, volume);
if (error != 0)
- printk(KERN_WARNING "error: setting tone volume returned: %s\n",
+ printk(KERN_WARNING "error: setting tone volume returned: %s\n",
ppc_rtas_process_error(error));
return count;
}
/*
* include/asm-ppc/platforms/prpmc750.h
- *
+ *
* Definitions for Motorola PrPMC750 board support
*
* Author: Matt Porter <mporter@mvista.com>
/*
* arch/ppc/platforms/prpmc750_pci.c
- *
+ *
* PCI support for Motorola PrPMC750
*
* Author: Matt Porter <mporter@mvista.com>
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
- */
+ */
{
{12, 0, 0, 0}, /* IDSEL 14 - Ethernet, base */
{0, 0, 0, 0}, /* IDSEL 15 - unused */
hose->mem_space.end = PRPMC750_PCI_UPPER_MEM_AUTO;
hose->io_base_virt = (void *)PRPMC750_ISA_IO_BASE;
-
+
setup_indirect_pci(hose,
PRPMC750_PCI_CONFIG_ADDR,
PRPMC750_PCI_CONFIG_DATA);
/*
* include/asm-ppc/platforms/prpmc750_serial.h
- *
+ *
* Motorola PrPMC750 serial support
*
* Author: Matt Porter <mporter@mvista.com>
/*
* include/asm-ppc/platforms/prpmc800.h
- *
+ *
* Definitions for Motorola PrPMC800 board support
*
* Author: Dale Farnsworth <dale.farnsworth@mvista.com>
/*
* arch/ppc/platforms/prpmc800_pci.c
- *
+ *
* PCI support for Motorola PrPMC800
*
* Author: Dale Farnsworth <dale.farnsworth@mvista.com>
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
- */
+ */
{
{12, 0, 0, 0}, /* IDSEL 14 - Ethernet, base */
{0, 0, 0, 0}, /* IDSEL 15 - unused */
/*
* arch/ppc/platforms/prpmc800_serial.h
- *
+ *
* Definitions for Motorola MCG PRPMC800 cPCI board support
*
* Author: Dale Farnsworth dale.farnsworth@mvista.com
"\001\002\006CHRP_Floppy", /* CHRP Floppy in PR*P system */
"\001\003\000GeneralIPI",
-
+
"\002\000\000GeneralEther",
"\002\001\000GeneralToken",
"\002\002\000GeneralFDDI",
-
+
"\003\000\000GeneralVGA",
"\003\001\000GeneralSVGA",
"\003\002\000GeneralXGA",
-
+
"\004\000\000GeneralVideo",
"\004\001\000GeneralAudio",
"\004\001\001CS4232Audio", /* CS 4232 Plug 'n Play Configured */
"\005\000\000PCIMemoryController", /* PCI Config Method */
"\005\000\001RS6KMemoryController", /* RS6K Config Method */
"\005\001\000GeneralFLASH",
-
+
"\006\000\000GeneralHostBridge",
"\006\001\000GeneralISABridge",
"\006\002\000GeneralEISABridge",
"\006\004\002PCIBridgeRS6K",
"\006\005\000GeneralPCMCIABridge",
"\006\006\000GeneralVMEBridge",
-
+
"\007\000\000GeneralRS232",
"\007\000\001COMx",
"\007\000\002Compatible16450",
"\007\001\003NS26EParPort", /* Ports 26E and 26F */
"\007\001\004NS15CParPort", /* Ports 15C and 15D */
"\007\001\005NS2EParPort", /* Ports 2E and 2F */
-
+
"\010\000\000GeneralPIC",
"\010\000\001ISA_PIC",
"\010\000\002EISA_PIC",
"\010\002\002EISA_Timer",
"\010\003\000GeneralRTC",
"\010\003\001ISA_RTC",
-
+
"\010\004\001StoreThruOnly",
"\010\004\002StoreInEnabled",
"\010\004\003RS6KL2Cache",
"\010\006\000GeneralPowerManagement",
"\010\006\001EPOWPowerManagement",
"\010\006\002PowerControl", // d1378
-
+
"\010\007\000GeneralCMOS",
"\010\010\000GeneralOPPanel",
"\010\011\000GeneralServiceProcessor",
"\010\012\000GeneralServiceProcessor",
"\010\013\000GeneralServiceProcessor",
-
+
"\010\014\001TransferData",
"\010\014\002IGMC32",
"\010\014\003IGMC64",
-
+
"\010\017\000GeneralSystemPlanar", /* 10/5/95 */
NULL
};
-static const unsigned char __init *PnP_SUB_TYPE_STR(unsigned char BaseType,
+static const unsigned char __init *PnP_SUB_TYPE_STR(unsigned char BaseType,
unsigned char SubType) {
unsigned char ** s=PnP_SUB_TYPES;
- while (*s && !((*s)[0]==BaseType
+ while (*s && !((*s)[0]==BaseType
&& (*s)[1]==SubType)) s++;
if (*s) return *s+2;
else return("Unknown !");
};
-static const unsigned char __init *PnP_INTERFACE_STR(unsigned char BaseType,
+static const unsigned char __init *PnP_INTERFACE_STR(unsigned char BaseType,
unsigned char SubType,
unsigned char Interface) {
unsigned char ** s=PnP_INTERFACES;
- while (*s && !((*s)[0]==BaseType
- && (*s)[1]==SubType
+ while (*s && !((*s)[0]==BaseType
+ && (*s)[1]==SubType
&& (*s)[2]==Interface)) s++;
if (*s) return *s+3;
else return NULL;
switch (tag_small_item_name(pkt->S1_Pack.Tag)) {
case PnPVersion:
- printk(" PnPversion 0x%x.%x\n",
+ printk(" PnPversion 0x%x.%x\n",
pkt->S1_Pack.Version[0], /* How to interpret version ? */
pkt->S1_Pack.Version[1]);
break;
break;
case IRQFormat:
#define p pkt->S4_Pack
- printk(" IRQ Mask 0x%4.4x, %s %s sensitive\n",
+ printk(" IRQ Mask 0x%4.4x, %s %s sensitive\n",
ld_le16((unsigned short *)p.IRQMask),
intlevel[(size>3) ? !(p.IRQInfo&0x05) : 0],
intsense[(size>3) ? !(p.IRQInfo&0x03) : 0]);
p.IOInfo&ISAAddr16bit?16:10,
ld_le16((unsigned short *)p.RangeMin),
ld_le16((unsigned short *)p.RangeMax),
- p.IOAlign, p.IONum);
+ p.IOAlign, p.IONum);
#undef p
break;
case FixedIOPort:
printk(" Fixed (10 decoded bits) I/O port from %3.3x to %3.3x\n",
(p.Range[1]<<8)|p.Range[0],
((p.Range[1]<<8)|p.Range[0])+p.IONum-1);
-#undef p
+#undef p
break;
case Res1:
case Res2:
case Res3:
- printk(" Undefined packet type %d!\n",
+ printk(" Undefined packet type %d!\n",
tag_small_item_name(pkt->S1_Pack.Tag));
break;
case SmallVendorItem:
printsmallvendor(pkt,size);
break;
default:
- printk(" Type 0x2.2x%d, size=%d\n",
- pkt->S1_Pack.Tag, size);
+ printk(" Type 0x2.2x%d, size=%d\n",
+ pkt->S1_Pack.Tag, size);
break;
}
}
break;
case 7:
printk(" SCSI buses: %d, id(s):", p.PPCData[0]);
- for(i=1; i<=p.PPCData[0]; i++)
+ for(i=1; i<=p.PPCData[0]; i++)
printk(" %d%c", p.PPCData[i], i==p.PPCData[0] ? '\n' : ',');
break;
case 9:
p.PPCData[1]);
printk(" ISA interrupts routed to %s\n"
- " lines",
+ " lines",
tmpstr);
for(i=0; i<16; i++) {
int line=ld_le16((unsigned short *)p.PPCData+i+1);
- if (line!=0xffff) printk(" %d(IRQ%d)", line, i);
+ if (line!=0xffff) printk(" %d(IRQ%d)", line, i);
}
printk("\n");
break;
printlargevendor(pkt, size);
break;
default:
- printk(" Type 0x2.2x%d, size=%d\n",
- pkt->S1_Pack.Tag, size);
+ printk(" Type 0x2.2x%d, size=%d\n",
+ pkt->S1_Pack.Tag, size);
break;
}
}
int size;
if (tag_type(pkt->S1_Pack.Tag)) {
size= 3 +
- pkt->L1_Pack.Count0 +
+ pkt->L1_Pack.Count0 +
pkt->L1_Pack.Count1*256;
printlargepacket(pkt, size);
} else {
int i;
PPC_DEVICE *dev;
#define did dev->DeviceId
-
+
/* make sure we have residual data first */
if ( res->ResidualLength == 0 )
return;
-
+
printk("Residual: %ld devices\n", res->ActualNumDevices);
for ( i = 0;
i < res->ActualNumDevices ;
char decomp[4], sn[20];
const char * s;
dev = &res->Devices[i];
- s = PnP_INTERFACE_STR(did.BaseType, did.SubType,
+ s = PnP_INTERFACE_STR(did.BaseType, did.SubType,
did.Interface);
if(!s) {
sprintf(sn, "interface %d", did.Interface);
s=sn;
}
- if ( did.BusId & PCIDEVICE )
+ if ( did.BusId & PCIDEVICE )
printk("PCI Device, Bus %d, DevFunc 0x%x:",
dev->BusAccess.PCIAccess.BusNumber,
dev->BusAccess.PCIAccess.DevFuncNumber);
if ( did.BusId & PNPISADEVICE ) printk("PNPISA Device:");
- if ( did.BusId & ISADEVICE )
+ if ( did.BusId & ISADEVICE )
printk("ISA Device, Slot %d, LogicalDev %d:",
dev->BusAccess.ISAAccess.SlotNumber,
dev->BusAccess.ISAAccess.LogicalDevNumber);
if ( did.BusId & EISADEVICE ) printk("EISA Device:");
- if ( did.BusId & PROCESSORDEVICE )
+ if ( did.BusId & PROCESSORDEVICE )
printk("ProcBus Device, Bus %d, BUID %d: ",
dev->BusAccess.ProcBusAccess.BusNumber,
dev->BusAccess.ProcBusAccess.BUID);
decomp[1]='A'-1+((did.DevId>>21)&0x1F);
decomp[2]='A'-1+((did.DevId>>16)&0x1F);
decomp[3]=0;
- printk(" %s%4.4lX, %s, %s, %s\n",
+ printk(" %s%4.4lX, %s, %s, %s\n",
decomp, did.DevId&0xffff,
PnP_BASE_TYPES[did.BaseType],
PnP_SUB_TYPE_STR(did.BaseType,did.SubType),
static const char* Usage[]={
"FirmwareStack", "FirmwareHeap", "FirmwareCode", "BootImage",
"Free", "Unpopulated", "ISAAddr", "PCIConfig",
- "IOMemory", "SystemIO", "SystemRegs", "PCIAddr",
- "UnPopSystemRom", "SystemROM", "ResumeBlock", "Other"
+ "IOMemory", "SystemIO", "SystemRegs", "PCIAddr",
+ "UnPopSystemRom", "SystemROM", "ResumeBlock", "Other"
};
static const unsigned char *FWMan[]={
"IBM", "Motorola", "FirmWorks", "Bull"
};
static const unsigned char *FWFlags[]={
"Conventional", "OpenFirmware", "Diagnostics", "LowDebug",
- "MultiBoot", "LowClient", "Hex41", "FAT",
+ "MultiBoot", "LowClient", "Hex41", "FAT",
"ISO9660", "SCSI_ID_Override", "Tape_Boot", "FW_Boot_Path"
};
static const unsigned char *ESM[]={
printk("FirmwareFlags:");
for(j=0; j<12; j++) {
if (vpd.FirmwareSupports & (1<<j)) {
- printk(" %s%c", FWFlags[j],
+ printk(" %s%c", FWFlags[j],
vpd.FirmwareSupports&(-2<<j) ? ',' : '\n');
}
}
printk("NVRamSize: %ld\n", vpd.NvramSize);
printk("SIMMslots: %ld\n", vpd.NumSIMMSlots);
- printk("EndianSwitchMethod: %s\n",
+ printk("EndianSwitchMethod: %s\n",
ESM[vpd.EndianSwitchMethod>2 ? 2 : vpd.EndianSwitchMethod]);
- printk("SpreadIOMethod: %s\n",
+ printk("SpreadIOMethod: %s\n",
SIOM[vpd.SpreadIOMethod>3 ? 3 : vpd.SpreadIOMethod]);
printk("Processor/Bus frequencies (Hz): %ld/%ld\n",
vpd.ProcessorHz, vpd.ProcessorBusHz);
vpd.CoherenceBlockSize, vpd.GranuleSize);
for (i=0; i<res->ActualNumMemSegs; i++) {
int mask=res->Segs[i].Usage, first, j;
- printk("%8.8lx-%8.8lx ",
+ printk("%8.8lx-%8.8lx ",
res->Segs[i].BasePage*ps,
(res->Segs[i].PageCount+res->Segs[i].BasePage)*ps-1);
for(j=15, first=1; j>=0; j--) {
union _PnP_TAG_PACKET *pkt;
PPC_DEVICE *dev;
#define did dev->DeviceId
-
+
/* make sure we have residual data first */
if ( res->ResidualLength == 0 )
return;
pci_strdev(did.DevId>>16,
did.DevId&0xffff)
);
-
+
if ( did.BusId & PNPISADEVICE )
{
printk(" pnp:");
did.BaseType, did.SubType);
printk("\n");
continue;
- }
+ }
/*
* eisa devices
*/
did.BaseType, did.SubType);
printk("\n");
continue;
- }
+ }
/*
* proc bus devices
*/
did.BaseType, did.SubType);
printk("\n");
continue;
- }
+ }
printk("Unknown bus access device: busid %lx\n",
did.BusId);
}
}
-#endif
+#endif
-/* Returns the device index in the residual data,
+/* Returns the device index in the residual data,
any of the search items may be set as -1 for wildcard,
- DevID number field (second halfword) is big endian !
+ DevID number field (second halfword) is big endian !
Examples:
- search for the Interrupt controller (8259 type), 2 methods:
- 1) i8259 = residual_find_device(~0,
- NULL,
- SystemPeripheral,
- ProgrammableInterruptController,
- ISA_PIC,
+ 1) i8259 = residual_find_device(~0,
+ NULL,
+ SystemPeripheral,
+ ProgrammableInterruptController,
+ ISA_PIC,
0);
- 2) i8259 = residual_find_device(~0, "PNP0000", -1, -1, -1, 0)
+ 2) i8259 = residual_find_device(~0, "PNP0000", -1, -1, -1, 0)
- search for the first two serial devices, whatever their type)
iserial1 = residual_find_device(~0,NULL,
RS232Device,
-1, 1)
- but search for typical COM1 and COM2 is not easy due to the
- fact that the interface may be anything and the name "PNP0500" or
- "PNP0501". Quite bad.
+ fact that the interface may be anything and the name "PNP0500" or
+ "PNP0501". Quite bad.
*/
static int __init same_DevID(unsigned short vendor,
unsigned short Number,
- char * str)
+ char * str)
{
static unsigned const char hexdigit[]="0123456789ABCDEF";
if (strlen(str)!=7) return 0;
if (tag_type(packet_tag)) mask=0xff; else mask=0xF8;
masked_tag = packet_tag&mask;
for(; *p != END_TAG; p+=size) {
- if ((*p & mask) == masked_tag && !(n--))
+ if ((*p & mask) == masked_tag && !(n--))
return (PnP_TAG_PACKET *) p;
if (tag_type(*p))
size=ld_le16((unsigned short *)(p+1))+3;
- else
+ else
size=tag_small_count(*p)+1;
}
return 0; /* not found */
int next=0;
while (p) {
p = (unsigned char *) PnP_find_packet(p, 0x70, next);
- if (p && p[1]==packet_type && !(n--))
+ if (p && p[1]==packet_type && !(n--))
return (PnP_TAG_PACKET *) p;
next = 1;
};
int next=0;
while (p) {
p = (unsigned char *) PnP_find_packet(p, 0x84, next);
- if (p && p[3]==packet_type && !(n--))
+ if (p && p[3]==packet_type && !(n--))
return (PnP_TAG_PACKET *) p;
next = 1;
};
/*
* arch/ppc/platforms/sandpoint.h
- *
+ *
* Definitions for Motorola SPS Sandpoint Test Platform
*
* Author: Mark A. Greer
/*
* Speech Design SPD8xxTS board specific definitions
- *
+ *
* Copyright (c) 2000,2001 Wolfgang Denk (wd@denx.de)
*/
#define __ASM_SPD8XX_H__
#include <linux/config.h>
-
+
#include <asm/ppcboot.h>
#ifndef __ASSEMBLY__
/*
* include/asm-ppc/platforms/spruce.h
- *
+ *
* Definitions for IBM Spruce reference board support
*
* Authors: Matt Porter and Johnnie Peters
/*
* arch/ppc/platforms/spruce_pci.c
- *
+ *
* PCI support for IBM Spruce
*
* Author: Johnnie Peters
{
static char pci_irq_table[][4] =
/*
- * PCI IDSEL/INTPIN->INTLINE
+ * PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
/* Setup hose */
hose = pcibios_alloc_controller();
- if (!hose)
+ if (!hose)
return;
hose->first_busno = 0;
/*
* include/asm-ppc/spruce_serial.h
- *
+ *
* Definitions for IBM Spruce reference board support
*
* Authors: Matt Porter and Johnnie Peters
/*
* TQM8260 board specific definitions
- *
+ *
* Copyright (c) 2001 Wolfgang Denk (wd@denx.de)
*/
#define __TQM8260_PLATFORM
#include <linux/config.h>
-
+
#include <asm/ppcboot.h>
#define IMAP_ADDR ((uint)0xFFF00000)
/*
* arch/ppc/platforms/tqm8260_setup.c
- *
+ *
* TQM8260 platform support
*
* Author: Allen Curtis <acurtis@onz.com>
extern unsigned char __res[sizeof(bd_t)];
-extern void m8260_init(unsigned long r3, unsigned long r4,
+extern void m8260_init(unsigned long r3, unsigned long r4,
unsigned long r5, unsigned long r6, unsigned long r7);
static int
/*
* TQM8xx(L) board specific definitions
- *
+ *
* Copyright (c) 1999-2002 Wolfgang Denk (wd@denx.de)
*/
#define __MACH_TQM8xx_H
#include <linux/config.h>
-
+
#include <asm/ppcboot.h>
#ifndef __ASSEMBLY__
/* Calc BAT values for mapping the display and store them
* in disp_BAT. Those values are then used from head.S to map
* the display during identify_machine() and MMU_Init()
- *
+ *
* The display is mapped to virtual address 0xD0000000, rather
* than 1:1, because some some CHRP machines put the frame buffer
* in the region starting at 0xC0000000 (KERNELBASE).
* This mapping is temporary and will disappear as soon as the
* setup done by MMU_Init() is applied.
- *
+ *
* For now, we align the BAT and then map 8Mb on 601 and 16Mb
* on other PPCs. This may cause trouble if the framebuffer
* is really badly aligned, but I didn't encounter this case
lowbits = addr & ~0xFF000000UL;
addr &= 0xFF000000UL;
disp_BAT[0] = vaddr | (BL_16M<<2) | 2;
- disp_BAT[1] = addr | (_PAGE_NO_CACHE | _PAGE_GUARDED | BPP_RW);
+ disp_BAT[1] = addr | (_PAGE_NO_CACHE | _PAGE_GUARDED | BPP_RW);
} else {
/* 601 */
lowbits = addr & ~0xFF800000UL;
/* Here's a small text engine to use during early boot
* or for debugging purposes
- *
+ *
* todo:
- *
+ *
* - build some kind of vgacon with it to enable early printk
* - move to a separate file
* - add a few video driver hooks to keep in sync with display
unsigned long width = ((bi->dispDeviceRect[2] - bi->dispDeviceRect[0]) *
(bi->dispDeviceDepth >> 3)) >> 2;
int i,j;
-
+
for (i=0; i<(bi->dispDeviceRect[3] - bi->dispDeviceRect[1]); i++)
{
unsigned long *ptr = base;
unsigned long width = ((bi->dispDeviceRect[2] - bi->dispDeviceRect[0]) *
(bi->dispDeviceDepth >> 3)) >> 2;
int i,j;
-
+
for (i=0; i<(bi->dispDeviceRect[3] - bi->dispDeviceRect[1]); i++)
{
unsigned long *ptr = base;
unsigned long width = ((bi->dispDeviceRect[2] - bi->dispDeviceRect[0]) *
(bi->dispDeviceDepth >> 3)) >> 2;
int i,j;
-
+
#ifdef CONFIG_ADB_PMU
pmu_suspend(); /* PMU will not shut us down ! */
#endif
btext_drawhex(unsigned long v)
{
static char hex_table[] = "0123456789abcdef";
-
+
if (!boot_text_mapped)
return;
btext_drawchar(hex_table[(v >> 28) & 0x0000000FUL]);
unsigned char *base = calc_base(bi, locX << 3, locY << 4);
unsigned char *font = &vga_font[((unsigned long)c) * 16];
int rb = bi->dispDeviceRowBytes;
-
+
switch(bi->dispDeviceDepth) {
case 24:
case 32:
static void BTEXT
draw_byte_32(unsigned char *font, unsigned long *base, int rb)
{
- int l, bits;
+ int l, bits;
int fg = 0xFFFFFFFFUL;
int bg = 0x00000000UL;
-
+
for (l = 0; l < 16; ++l)
{
bits = *font++;
static void BTEXT
draw_byte_16(unsigned char *font, unsigned long *base, int rb)
{
- int l, bits;
+ int l, bits;
int fg = 0xFFFFFFFFUL;
int bg = 0x00000000UL;
unsigned long *eb = expand_bits_16;
static void BTEXT
draw_byte_8(unsigned char *font, unsigned long *base, int rb)
{
- int l, bits;
+ int l, bits;
int fg = 0x0F0F0F0FUL;
int bg = 0x00000000UL;
unsigned long *eb = expand_bits_8;
}
static unsigned char vga_font[cmapsz] BTDATA = {
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0x81, 0xa5, 0x81, 0x81, 0xbd,
-0x99, 0x81, 0x81, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0xff,
-0xdb, 0xff, 0xff, 0xc3, 0xe7, 0xff, 0xff, 0x7e, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x6c, 0xfe, 0xfe, 0xfe, 0xfe, 0x7c, 0x38, 0x10,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x38, 0x7c, 0xfe,
-0x7c, 0x38, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
-0x3c, 0x3c, 0xe7, 0xe7, 0xe7, 0x18, 0x18, 0x3c, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x18, 0x3c, 0x7e, 0xff, 0xff, 0x7e, 0x18, 0x18, 0x3c,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x3c,
-0x3c, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
-0xff, 0xff, 0xe7, 0xc3, 0xc3, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x66, 0x42, 0x42, 0x66, 0x3c, 0x00,
-0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc3, 0x99, 0xbd,
-0xbd, 0x99, 0xc3, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x1e, 0x0e,
-0x1a, 0x32, 0x78, 0xcc, 0xcc, 0xcc, 0xcc, 0x78, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x3c, 0x66, 0x66, 0x66, 0x66, 0x3c, 0x18, 0x7e, 0x18, 0x18,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x33, 0x3f, 0x30, 0x30, 0x30,
-0x30, 0x70, 0xf0, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0x63,
-0x7f, 0x63, 0x63, 0x63, 0x63, 0x67, 0xe7, 0xe6, 0xc0, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x18, 0x18, 0xdb, 0x3c, 0xe7, 0x3c, 0xdb, 0x18, 0x18,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xc0, 0xe0, 0xf0, 0xf8, 0xfe, 0xf8,
-0xf0, 0xe0, 0xc0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x06, 0x0e,
-0x1e, 0x3e, 0xfe, 0x3e, 0x1e, 0x0e, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x18, 0x3c, 0x7e, 0x18, 0x18, 0x18, 0x7e, 0x3c, 0x18, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66,
-0x66, 0x00, 0x66, 0x66, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0xdb,
-0xdb, 0xdb, 0x7b, 0x1b, 0x1b, 0x1b, 0x1b, 0x1b, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x7c, 0xc6, 0x60, 0x38, 0x6c, 0xc6, 0xc6, 0x6c, 0x38, 0x0c, 0xc6,
-0x7c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0xfe, 0xfe, 0xfe, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x3c,
-0x7e, 0x18, 0x18, 0x18, 0x7e, 0x3c, 0x18, 0x7e, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x18, 0x3c, 0x7e, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
-0x18, 0x7e, 0x3c, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x18, 0x0c, 0xfe, 0x0c, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x60, 0xfe, 0x60, 0x30, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xc0,
-0xc0, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x24, 0x66, 0xff, 0x66, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x10, 0x38, 0x38, 0x7c, 0x7c, 0xfe, 0xfe, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xfe, 0x7c, 0x7c,
-0x38, 0x38, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x18, 0x3c, 0x3c, 0x3c, 0x18, 0x18, 0x18, 0x00, 0x18, 0x18,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x66, 0x66, 0x66, 0x24, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6c,
-0x6c, 0xfe, 0x6c, 0x6c, 0x6c, 0xfe, 0x6c, 0x6c, 0x00, 0x00, 0x00, 0x00,
-0x18, 0x18, 0x7c, 0xc6, 0xc2, 0xc0, 0x7c, 0x06, 0x06, 0x86, 0xc6, 0x7c,
-0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0xc6, 0x0c, 0x18,
-0x30, 0x60, 0xc6, 0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x6c,
-0x6c, 0x38, 0x76, 0xdc, 0xcc, 0xcc, 0xcc, 0x76, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x30, 0x30, 0x30, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x18, 0x30, 0x30, 0x30, 0x30,
-0x30, 0x30, 0x18, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x18,
-0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x18, 0x30, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x66, 0x3c, 0xff, 0x3c, 0x66, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x7e,
-0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x18, 0x30, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x02, 0x06, 0x0c, 0x18, 0x30, 0x60, 0xc0, 0x80, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x7c, 0xc6, 0xc6, 0xce, 0xde, 0xf6, 0xe6, 0xc6, 0xc6, 0x7c,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x38, 0x78, 0x18, 0x18, 0x18,
-0x18, 0x18, 0x18, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 0xc6,
-0x06, 0x0c, 0x18, 0x30, 0x60, 0xc0, 0xc6, 0xfe, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x7c, 0xc6, 0x06, 0x06, 0x3c, 0x06, 0x06, 0x06, 0xc6, 0x7c,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x1c, 0x3c, 0x6c, 0xcc, 0xfe,
-0x0c, 0x0c, 0x0c, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xc0,
-0xc0, 0xc0, 0xfc, 0x06, 0x06, 0x06, 0xc6, 0x7c, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x38, 0x60, 0xc0, 0xc0, 0xfc, 0xc6, 0xc6, 0xc6, 0xc6, 0x7c,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xc6, 0x06, 0x06, 0x0c, 0x18,
-0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 0xc6,
-0xc6, 0xc6, 0x7c, 0xc6, 0xc6, 0xc6, 0xc6, 0x7c, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x7c, 0xc6, 0xc6, 0xc6, 0x7e, 0x06, 0x06, 0x06, 0x0c, 0x78,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00,
-0x00, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x18, 0x18, 0x00, 0x00, 0x00, 0x18, 0x18, 0x30, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x06, 0x0c, 0x18, 0x30, 0x60, 0x30, 0x18, 0x0c, 0x06,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0x00, 0x00,
-0x7e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
-0x30, 0x18, 0x0c, 0x06, 0x0c, 0x18, 0x30, 0x60, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x7c, 0xc6, 0xc6, 0x0c, 0x18, 0x18, 0x18, 0x00, 0x18, 0x18,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 0xc6, 0xc6, 0xc6, 0xde, 0xde,
-0xde, 0xdc, 0xc0, 0x7c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x38,
-0x6c, 0xc6, 0xc6, 0xfe, 0xc6, 0xc6, 0xc6, 0xc6, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0xfc, 0x66, 0x66, 0x66, 0x7c, 0x66, 0x66, 0x66, 0x66, 0xfc,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x66, 0xc2, 0xc0, 0xc0, 0xc0,
-0xc0, 0xc2, 0x66, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x6c,
-0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x6c, 0xf8, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0xfe, 0x66, 0x62, 0x68, 0x78, 0x68, 0x60, 0x62, 0x66, 0xfe,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x66, 0x62, 0x68, 0x78, 0x68,
-0x60, 0x60, 0x60, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x66,
-0xc2, 0xc0, 0xc0, 0xde, 0xc6, 0xc6, 0x66, 0x3a, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0xc6, 0xc6, 0xc6, 0xc6, 0xfe, 0xc6, 0xc6, 0xc6, 0xc6, 0xc6,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x18, 0x18, 0x18, 0x18, 0x18,
-0x18, 0x18, 0x18, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x0c,
-0x0c, 0x0c, 0x0c, 0x0c, 0xcc, 0xcc, 0xcc, 0x78, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0xe6, 0x66, 0x66, 0x6c, 0x78, 0x78, 0x6c, 0x66, 0x66, 0xe6,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x60, 0x60, 0x60, 0x60, 0x60,
-0x60, 0x62, 0x66, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc3, 0xe7,
-0xff, 0xff, 0xdb, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0xc6, 0xe6, 0xf6, 0xfe, 0xde, 0xce, 0xc6, 0xc6, 0xc6, 0xc6,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 0xc6, 0xc6, 0xc6, 0xc6, 0xc6,
-0xc6, 0xc6, 0xc6, 0x7c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x66,
-0x66, 0x66, 0x7c, 0x60, 0x60, 0x60, 0x60, 0xf0, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x7c, 0xc6, 0xc6, 0xc6, 0xc6, 0xc6, 0xc6, 0xd6, 0xde, 0x7c,
-0x0c, 0x0e, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x66, 0x66, 0x66, 0x7c, 0x6c,
-0x66, 0x66, 0x66, 0xe6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 0xc6,
-0xc6, 0x60, 0x38, 0x0c, 0x06, 0xc6, 0xc6, 0x7c, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0xff, 0xdb, 0x99, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x3c,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc6, 0xc6, 0xc6, 0xc6, 0xc6, 0xc6,
-0xc6, 0xc6, 0xc6, 0x7c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc3, 0xc3,
-0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0x66, 0x3c, 0x18, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xdb, 0xdb, 0xff, 0x66, 0x66,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc3, 0xc3, 0x66, 0x3c, 0x18, 0x18,
-0x3c, 0x66, 0xc3, 0xc3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc3, 0xc3,
-0xc3, 0x66, 0x3c, 0x18, 0x18, 0x18, 0x18, 0x3c, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0xff, 0xc3, 0x86, 0x0c, 0x18, 0x30, 0x60, 0xc1, 0xc3, 0xff,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x30, 0x30, 0x30, 0x30, 0x30,
-0x30, 0x30, 0x30, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
-0xc0, 0xe0, 0x70, 0x38, 0x1c, 0x0e, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x3c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x3c,
-0x00, 0x00, 0x00, 0x00, 0x10, 0x38, 0x6c, 0xc6, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
-0x30, 0x30, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x0c, 0x7c,
-0xcc, 0xcc, 0xcc, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x60,
-0x60, 0x78, 0x6c, 0x66, 0x66, 0x66, 0x66, 0x7c, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 0xc6, 0xc0, 0xc0, 0xc0, 0xc6, 0x7c,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x0c, 0x0c, 0x3c, 0x6c, 0xcc,
-0xcc, 0xcc, 0xcc, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x7c, 0xc6, 0xfe, 0xc0, 0xc0, 0xc6, 0x7c, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x38, 0x6c, 0x64, 0x60, 0xf0, 0x60, 0x60, 0x60, 0x60, 0xf0,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x76, 0xcc, 0xcc,
-0xcc, 0xcc, 0xcc, 0x7c, 0x0c, 0xcc, 0x78, 0x00, 0x00, 0x00, 0xe0, 0x60,
-0x60, 0x6c, 0x76, 0x66, 0x66, 0x66, 0x66, 0xe6, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x18, 0x18, 0x00, 0x38, 0x18, 0x18, 0x18, 0x18, 0x18, 0x3c,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x06, 0x00, 0x0e, 0x06, 0x06,
-0x06, 0x06, 0x06, 0x06, 0x66, 0x66, 0x3c, 0x00, 0x00, 0x00, 0xe0, 0x60,
-0x60, 0x66, 0x6c, 0x78, 0x78, 0x6c, 0x66, 0xe6, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x38, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x3c,
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+0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0xf7, 0x00, 0xff,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0xff, 0x00, 0xf7, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
+0x36, 0x36, 0x36, 0x36, 0x36, 0x37, 0x30, 0x37, 0x36, 0x36, 0x36, 0x36,
+0x36, 0x36, 0x36, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0xff,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x36, 0x36, 0x36, 0x36,
+0x36, 0xf7, 0x00, 0xf7, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
+0x18, 0x18, 0x18, 0x18, 0x18, 0xff, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0xff,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0xff, 0x00, 0xff, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x36, 0x36, 0x36, 0x36,
+0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x3f,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x1f, 0x18, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0x18, 0x1f, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f,
+0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
+0x36, 0x36, 0x36, 0xff, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
+0x18, 0x18, 0x18, 0x18, 0x18, 0xff, 0x18, 0xff, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0xf8,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x1f, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xf0, 0xf0, 0xf0,
+0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0,
+0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f,
+0x0f, 0x0f, 0x0f, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x76, 0xdc, 0xd8, 0xd8, 0xd8, 0xdc, 0x76, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x78, 0xcc, 0xcc, 0xcc, 0xd8, 0xcc, 0xc6, 0xc6, 0xc6, 0xcc,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xc6, 0xc6, 0xc0, 0xc0, 0xc0,
+0xc0, 0xc0, 0xc0, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0xfe, 0x6c, 0x6c, 0x6c, 0x6c, 0x6c, 0x6c, 0x6c, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0xfe, 0xc6, 0x60, 0x30, 0x18, 0x30, 0x60, 0xc6, 0xfe,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0xd8, 0xd8,
+0xd8, 0xd8, 0xd8, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x66, 0x66, 0x66, 0x66, 0x66, 0x7c, 0x60, 0x60, 0xc0, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x76, 0xdc, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0x18, 0x3c, 0x66, 0x66,
+0x66, 0x3c, 0x18, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
+0x6c, 0xc6, 0xc6, 0xfe, 0xc6, 0xc6, 0x6c, 0x38, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x38, 0x6c, 0xc6, 0xc6, 0xc6, 0x6c, 0x6c, 0x6c, 0x6c, 0xee,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x30, 0x18, 0x0c, 0x3e, 0x66,
+0x66, 0x66, 0x66, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x7e, 0xdb, 0xdb, 0xdb, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x03, 0x06, 0x7e, 0xdb, 0xdb, 0xf3, 0x7e, 0x60, 0xc0,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x30, 0x60, 0x60, 0x7c, 0x60,
+0x60, 0x60, 0x30, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
+0xc6, 0xc6, 0xc6, 0xc6, 0xc6, 0xc6, 0xc6, 0xc6, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0xfe, 0x00, 0x00, 0xfe, 0x00, 0x00, 0xfe, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x7e, 0x18,
+0x18, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
+0x18, 0x0c, 0x06, 0x0c, 0x18, 0x30, 0x00, 0x7e, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x0c, 0x18, 0x30, 0x60, 0x30, 0x18, 0x0c, 0x00, 0x7e,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x1b, 0x1b, 0x1b, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0xd8, 0xd8, 0xd8, 0x70, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x7e, 0x00, 0x18, 0x18, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x76, 0xdc, 0x00,
+0x76, 0xdc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x6c, 0x6c,
+0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x0c, 0x0c,
+0x0c, 0x0c, 0x0c, 0xec, 0x6c, 0x6c, 0x3c, 0x1c, 0x00, 0x00, 0x00, 0x00,
+0x00, 0xd8, 0x6c, 0x6c, 0x6c, 0x6c, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0xd8, 0x30, 0x60, 0xc8, 0xf8, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00,
};
/*
* arch/ppc/syslib/cpc700.h
- *
+ *
* Header file for IBM CPC700 Host Bridge, et. al.
*
* Author: Mark A. Greer
*/
extern struct hw_interrupt_type cpc700_pic;
extern unsigned int cpc700_irq_assigns[32][2];
-
+
extern void __init cpc700_init_IRQ(void);
extern int cpc700_get_irq(struct pt_regs *);
/*
* arch/ppc/syslib/cpc700_pic.c
- *
+ *
* Interrupt controller support for IBM Spruce
*
* Authors: Mark Greer, Matt Porter, and Johnnie Peters
/* Know IRQ fits in entry 0 of ppc_cached_irq_mask[] */
ppc_cached_irq_mask[0] |= CPC700_UIC_IRQ_BIT(irq);
-
+
CPC700_OUT_32(CPC700_UIC_UICER, ppc_cached_irq_mask[0]);
}
return;
tmp = CPC700_IN_32(CPC700_UIC_UICCR);
tmp |= CPC700_UIC_IRQ_BIT(irq);
CPC700_OUT_32(CPC700_UIC_UICCR, tmp);
-
+
return;
}
-
+
__init void
cpc700_init_IRQ(void)
{
irq++;
irq_test <<= 1;
} while (irq < NR_IRQS);
-
+
if (irq == NR_IRQS)
irq = 33;
/*
* arch/ppc/syslib/cpc710.h
- *
+ *
* Definitions for the IBM CPC710 PCI Host Bridge
*
* Author: Matt Porter <mporter@mvista.com>
* port(s) to be used can be accomplished by setting
* ppc_md.early_serial_map to a platform-specific mapping function.
*
- * Adapted from ppc4xx_kgdb.c.
+ * Adapted from ppc4xx_kgdb.c.
*
* Author: Matt Porter <mporter@mvista.com>
*
/*
* arch/ppc/syslib/gt64260_common.c
- *
+ *
* Common routines for the Marvell/Galileo GT64260 (Discovery) host bridge,
* interrupt controller, memory controller, serial controller, enet controller,
* etc.
/* Disable all the access control windows */
for (window=0; window<GT64260_PCI_ACC_CNTL_WINDOWS; window++) {
- gt64260_pci_acc_cntl_set_window(0, window, 0, 0, 0, 0);
- gt64260_pci_acc_cntl_set_window(1, window, 0, 0, 0, 0);
+ gt64260_pci_acc_cntl_set_window(0, window, 0, 0, 0, 0);
+ gt64260_pci_acc_cntl_set_window(1, window, 0, 0, 0, 0);
}
/* Disable all the PCI snoop regions */
for (window=0; window<GT64260_PCI_SNOOP_WINDOWS; window++) {
- gt64260_pci_snoop_set_window(0, window, 0, 0, 0, 0);
- gt64260_pci_snoop_set_window(1, window, 0, 0, 0, 0);
+ gt64260_pci_snoop_set_window(0, window, 0, 0, 0, 0);
+ gt64260_pci_snoop_set_window(1, window, 0, 0, 0, 0);
}
gt64260_pci_acc_cntl_set_window(0,
0x00000000,
info->mem_size,
GT64260_PCI_SNOOP_WB);
-
+
gt64260_pci_snoop_set_window(1,
0,
0x00000000,
u32 other_bus_base_addr,
u32 size)
{
- static u32
+ static u32
pci_p2p_mem_windows[GT64260_PCI_BUSES][GT64260_PCI_P2P_MEM_WINDOWS][4]={
{ /* PCI 0 */
{ 2, 0x10,
u32 cpu_base_addr,
u32 size)
{
- static u32
+ static u32
pci_dac_scs_windows[GT64260_PCI_BUSES][GT64260_PCI_DAC_SCS_WINDOWS][5]={
{ /* PCI 0 */
{ 4, 0x10, 0x14,
u32 cpu_base_addr,
u32 size)
{
- static u32
+ static u32
pci_dac_cs_windows[GT64260_PCI_BUSES][GT64260_PCI_DAC_CS_WINDOWS][5] = {
{ /* PCI 0 */
{ 6, 0x10, 0x14,
u32 other_bus_base_addr,
u32 size)
{
- static u32
+ static u32
pci_dac_p2p_mem_windows[GT64260_PCI_BUSES][GT64260_PCI_DAC_P2P_MEM_WINDOWS][5] = {
{ /* PCI 0 */
{ 4, 0x20, 0x24,
* gt64260_putc()
*
* Dump a character out the MPSC port for gt64260_mpsc_progress
- * this assumes the baud rate has already been set up and the
+ * this assumes the baud rate has already been set up and the
* MPSC initialized by the bootloader or firmware.
*/
val <<= 4;
}
gt_putc('\r');
- gt_putc('\n');
-
+ gt_putc('\n');
+
}
void
gt64260_mpsc_progress(char *s, unsigned short hex){
/* spit stuff out the 64260 mpsc */
-
+
volatile char c;
while ((c = *s++) != 0){
gt_putc(c);
- if ( c == '\n' ) gt_putc('\r');
+ if ( c == '\n' ) gt_putc('\r');
}
gt_putc('\n');
gt_putc('\r');
/*
* arch/ppc/syslib/gt64260_pic.c
- *
+ *
* Interrupt controller support for Galileo's GT64260.
*
* Author: Chris Zankel <chris@mvista.com>
* summarizes the interrupts generated by the units of the GT64260.
* Each bit is assigned to an interrupt number, where the low register
* are assigned from IRQ0 to IRQ31 and the high cause register
- * from IRQ32 to IRQ63
- * The GPP (General Purpose Port) interrupts are assigned from IRQ64 (GPP0)
- * to IRQ95 (GPP31).
+ * from IRQ32 to IRQ63
+ * The GPP (General Purpose Port) interrupts are assigned from IRQ64 (GPP0)
+ * to IRQ95 (GPP31).
* get_irq() returns the lowest interrupt number that is currently asserted.
*
- * Note:
- * - This driver does not initialize the GPP when used as an interrupt
+ * Note:
+ * - This driver does not initialize the GPP when used as an interrupt
* input.
*/
/* gt64260_get_irq()
*
* This function returns the lowest interrupt number of all interrupts that
- * are currently asserted.
+ * are currently asserted.
*
* Input Variable(s):
* struct pt_regs* not used
*
* Returns:
* int <interrupt number> or -2 (bogus interrupt)
- *
+ *
*/
int
gt64260_get_irq(struct pt_regs *regs)
if (irq > 31) {
if (irq > 63) {
/* unmask GPP irq */
- gt_write(GT64260_GPP_INTR_MASK,
+ gt_write(GT64260_GPP_INTR_MASK,
ppc_cached_irq_mask[2] |= (1<<(irq-64)));
} else {
/* mask high interrupt register */
- gt_write(GT64260_IC_CPU_INTR_MASK_HI,
+ gt_write(GT64260_IC_CPU_INTR_MASK_HI,
ppc_cached_irq_mask[1] |= (1<<(irq-32)));
}
} else {
/* mask low interrupt register */
- gt_write(GT64260_IC_CPU_INTR_MASK_LO,
+ gt_write(GT64260_IC_CPU_INTR_MASK_LO,
ppc_cached_irq_mask[0] |= (1<<irq));
}
}
if (irq > 31) {
if (irq > 63) {
/* mask GPP irq */
- gt_write(GT64260_GPP_INTR_MASK,
+ gt_write(GT64260_GPP_INTR_MASK,
ppc_cached_irq_mask[2] &= ~(1<<(irq-64)));
} else {
/* mask high interrupt register */
- gt_write(GT64260_IC_CPU_INTR_MASK_HI,
+ gt_write(GT64260_IC_CPU_INTR_MASK_HI,
ppc_cached_irq_mask[1] &= ~(1<<(irq-32)));
}
} else {
/* mask low interrupt register */
- gt_write(GT64260_IC_CPU_INTR_MASK_LO,
+ gt_write(GT64260_IC_CPU_INTR_MASK_LO,
ppc_cached_irq_mask[0] &= ~(1<<irq));
}
/*
* arch/ppc/syslib/harrier.c
- *
+ *
* Motorola MCG Harrier northbridge/memory controller support
*
* Author: Dale Farnsworth
break; /* Register not set correctly */
}
size = size_table[size];
-
+
val &= ~(size-1);
val += size;
outb(cached_A1,0xA1);
outb(cached_21,0x21);
}
-
+
static void i8259_mask_irq(unsigned int irq_nr)
{
unsigned long flags;
* Calculate 440GP clocks
*/
void __init ibm440gp_get_clocks(struct ibm440gp_clocks* p,
- unsigned int sys_clk,
+ unsigned int sys_clk,
unsigned int ser_clk)
{
u32 cpc0_sys0 = mfdcr(DCRN_CPC0_SYS0);
u32 cpc0_cr0 = mfdcr(DCRN_CPC0_CR0);
u32 opdv, epdv;
-
+
if (cpc0_sys0 & 0x2){
/* Bypass system PLL */
p->cpu = p->plb = sys_clk;
}
else {
u32 fbdv, fwdva, fwdvb, m, vco;
-
+
fbdv = (cpc0_sys0 >> 18) & 0x0f;
if (!fbdv)
fbdv = 16;
-
+
fwdva = 8 - ((cpc0_sys0 >> 15) & 0x7);
fwdvb = 8 - ((cpc0_sys0 >> 12) & 0x7);
-
- /* Feedback path */
+
+ /* Feedback path */
if (cpc0_sys0 & 0x00000080){
/* PerClk */
m = fwdvb * opdv * epdv;
p->cpu = vco / fwdva;
p->plb = vco / fwdvb;
}
-
+
opdv = ((cpc0_sys0 >> 10) & 0x3) + 1;
epdv = ((cpc0_sys0 >> 8) & 0x3) + 1;
-
+
p->opb = p->plb / opdv;
p->ebc = p->opb / epdv;
-
+
if (cpc0_cr0 & 0x00400000){
/* External UART clock */
p->uart = ser_clk;
}
else {
- /* Internal UART clock */
+ /* Internal UART clock */
u32 uart_div = ((cpc0_cr0 >> 16) & 0x1f) + 1;
p->uart = p->plb / uart_div;
}
unsigned int plb; /* PLBClk */
unsigned int opb; /* OPBClk */
unsigned int ebc; /* PerClk */
- unsigned int uart;
+ unsigned int uart;
};
/*
* Please, refer to the Figure 13.1 in 440GP user manual
- *
+ *
* if internal UART clock is used, ser_clk is ignored
*/
-void ibm440gp_get_clocks(struct ibm440gp_clocks*, unsigned int sys_clk,
+void ibm440gp_get_clocks(struct ibm440gp_clocks*, unsigned int sys_clk,
unsigned int ser_clk) __init;
-
+
#endif /* __ASSEMBLY__ */
#endif /* __PPC_SYSLIB_IBM440GP_COMMON_H */
#endif /* __KERNEL__ */
/*
* arch/ppc/syslib/mpc10x_common.c
- *
+ *
* Common routines for the Motorola SPS MPC106, MPC107 and MPC8240 Host bridge,
* Mem ctlr, EPIC, etc.
*
printk("Host bridge in Agent mode\n");
/* Read or Set LMBAR & PCSRBAR? */
}
-
+
/* Set base addr of the 8240/107 EUMB. */
early_write_config_dword(hose,
0,
phys_eumb_base);
/* Map EPIC register part of EUMB into vitual memory */
- OpenPIC_Addr =
+ OpenPIC_Addr =
ioremap(phys_eumb_base + MPC10X_EUMB_EPIC_OFFSET,
MPC10X_EUMB_EPIC_SIZE);
}
* of_match structure
* @ids: array of of device match structures to search in
* @dev: the of device structure to match against
- *
+ *
* Used by a driver to check whether an of_device present in the
- * system is in its list of supported devices.
+ * system is in its list of supported devices.
*/
const struct of_match * of_match_device(const struct of_match *matches,
const struct of_device *dev)
return NULL;
}
-static int of_platform_bus_match(struct device *dev, struct device_driver *drv)
+static int of_platform_bus_match(struct device *dev, struct device_driver *drv)
{
struct of_device * of_dev = to_of_device(dev);
struct of_platform_driver * of_drv = to_of_platform_driver(drv);
const struct of_match * matches = of_drv->match_table;
- if (!matches)
+ if (!matches)
return 0;
return of_match_device(matches, of_dev) != NULL;
struct of_device **odprop;
BUG_ON(ofdev->node == NULL);
-
+
odprop = (struct of_device **)get_property(ofdev->node, "linux,device", NULL);
if (!odprop) {
struct property *new_prop;
-
+
new_prop = kmalloc(sizeof(struct property) + sizeof(struct of_device *),
GFP_KERNEL);
if (new_prop == NULL)
{
struct of_device *dev;
u32 *reg;
-
+
dev = kmalloc(sizeof(*dev), GFP_KERNEL);
if (!dev)
return NULL;
/*
* Send an IPI to one or more CPUs
- *
+ *
* Externally called, however, it takes an IPI number (0...OPENPIC_NUM_IPI)
* and not a system-wide interrupt number
*/
void openpic_request_IPIs(void)
{
int i;
-
+
/*
- * Make sure this matches what is defined in smp.c for
- * smp_message_{pass|recv}() or what shows up in
+ * Make sure this matches what is defined in smp.c for
+ * smp_message_{pass|recv}() or what shows up in
* /proc/interrupts will be wrong!!! --Troy */
-
+
if (OpenPIC == NULL)
return;
{
volatile u_int *vpp;
u32 vp;
-
+
check_arg_irq(irq);
vpp = &ISR[irq - open_pic_irq_offset]->Vector_Priority;
openpic_setfield(vpp, OPENPIC_MASK);
#ifdef CONFIG_SMP
/*
* Enable/disable an IPI interrupt source
- *
+ *
* Externally called, irq is an offseted system-wide interrupt number
*/
void openpic_enable_ipi(u_int irq)
static void openpic_cached_enable_irq(u_int irq)
{
check_arg_irq(irq);
- save_irq_src_vp[irq - open_pic_irq_offset] &= ~OPENPIC_MASK;
+ save_irq_src_vp[irq - open_pic_irq_offset] &= ~OPENPIC_MASK;
}
static void openpic_cached_disable_irq(u_int irq)
{
check_arg_irq(irq);
- save_irq_src_vp[irq - open_pic_irq_offset] |= OPENPIC_MASK;
+ save_irq_src_vp[irq - open_pic_irq_offset] |= OPENPIC_MASK;
}
/* WARNING: Can be called directly by the cpufreq code with NULL parameter,
{
int i;
unsigned long flags;
-
+
spin_lock_irqsave(&openpic_setup_lock, flags);
if (openpic_suspend_count++ > 0) {
OPENPIC_MASK;
spin_lock_irqsave(&openpic_setup_lock, flags);
-
+
if ((--openpic_suspend_count) > 0) {
spin_unlock_irqrestore(&openpic_setup_lock, flags);
return 0;
openpic_set_spurious(OPENPIC_VEC_SPURIOUS+open_pic_irq_offset);
} while(openpic_readfield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK)
!= (OPENPIC_VEC_SPURIOUS + open_pic_irq_offset));
-
+
openpic_disable_8259_pass_through();
for (i=0; i<OPENPIC_NUM_IPI; i++)
#ifdef CONFIG_PM
.suspend = &openpic_suspend,
.resume = &openpic_resume,
-#endif /* CONFIG_PM */
+#endif /* CONFIG_PM */
};
static int __init init_openpic_sysfs(void)
/*
* arch/ppc/syslib/pci_auto.c
- *
+ *
* PCI autoconfiguration library
*
* Author: Matt Porter <mporter@mvista.com>
PCI_BASE_ADDRESS_MEM_TYPE_64)
found_mem64 = 1;
- addr_mask = PCI_BASE_ADDRESS_MEM_MASK;
+ addr_mask = PCI_BASE_ADDRESS_MEM_MASK;
upper_limit = &pciauto_upper_memspc;
DBG("PCI Autoconfig: BAR 0x%x, Mem ", bar);
}
* If we are a 64-bit decoder then increment to the
* upper 32 bits of the bar and force it to locate
* in the lower 4GB of memory.
- */
+ */
if (found_mem64) {
bar += 4;
early_write_config_dword(hose,
pci_devfn,
PCI_IO_BASE_UPPER16,
pciauto_upper_iospc >> 16);
-
+
/* Enable memory and I/O accesses, enable bus master */
early_read_config_dword(hose,
current_bus,
/*
* Reserve an additional 4MB for mem space and 16KB for
* I/O space. This should cover any additional space
- * requirement of unusual CardBus devices with
+ * requirement of unusual CardBus devices with
* additional bridges that can consume more address space.
- *
+ *
* Although pcmcia-cs currently will reprogram bridge
* windows, the goal is to add an option to leave them
* alone and use the bridge window ranges as the regions
pci_devfn,
0x2c,
pciauto_upper_iospc);
-
+
/* Enable memory and I/O accesses, enable bus master */
early_read_config_dword(hose,
current_bus,
#include <asm/pci-bridge.h>
#include <asm/ibm_ocp_pci.h>
-
+
extern void bios_fixup(struct pci_controller *, struct pcil0_regs *);
extern int ppc405_map_irq(struct pci_dev *dev, unsigned char idsel,
unsigned char pin);
tmp_addr = tmp_addr +
(0xffffffff - (tmp_size & 0xffffc000));
if (tmp_addr > PPC405_PCI_UPPER_MEM) {
- new_pmm_max = tmp_addr; // PPC405_PCI_UPPER_MEM
+ new_pmm_max = tmp_addr; // PPC405_PCI_UPPER_MEM
} else {
new_pmm_max = PPC405_PCI_UPPER_MEM;
}
/*
* Configures a DMA channel, including the peripheral bus width, if a
* peripheral is attached to the channel, the polarity of the DMAReq and
- * DMAAck signals, etc. This information should really be setup by the boot
+ * DMAAck signals, etc. This information should really be setup by the boot
* code, since most likely the configuration won't change dynamically.
* If the kernel has to call this function, it's recommended that it's
- * called from platform specific init code. The driver should not need to
+ * called from platform specific init code. The driver should not need to
* call this function.
*/
int hw_init_dma_channel(unsigned int dmanr, ppc_dma_ch_t *p_init)
* new value.
*/
- control |= (
+ control |= (
SET_DMA_CIE_ENABLE(p_init->int_enable) | /* interrupt enable */
- SET_DMA_BEN(p_init->buffer_enable) | /* buffer enable */
+ SET_DMA_BEN(p_init->buffer_enable) | /* buffer enable */
SET_DMA_ETD(p_init->etd_output) | /* end of transfer pin */
SET_DMA_TCE(p_init->tce_enable) | /* terminal count enable */
SET_DMA_PL(p_init->pl) | /* peripheral location */
default:
return DMA_STATUS_BAD_CHANNEL;
}
-
+
/* save these values in our dma channel structure */
memcpy(p_dma_ch, p_init, sizeof(ppc_dma_ch_t));
switch (dmanr) {
case 0:
- p_dma_ch->polarity =
+ p_dma_ch->polarity =
polarity & (DMAReq0_ActiveLow | DMAAck0_ActiveLow | EOT0_ActiveLow);
control = mfdcr(DCRN_DMACR0);
break;
case 1:
- p_dma_ch->polarity =
+ p_dma_ch->polarity =
polarity & (DMAReq1_ActiveLow | DMAAck1_ActiveLow | EOT1_ActiveLow);
control = mfdcr(DCRN_DMACR1);
break;
case 2:
- p_dma_ch->polarity =
+ p_dma_ch->polarity =
polarity & (DMAReq2_ActiveLow | DMAAck2_ActiveLow | EOT2_ActiveLow);
control = mfdcr(DCRN_DMACR2);
break;
case 3:
- p_dma_ch->polarity =
+ p_dma_ch->polarity =
polarity & (DMAReq3_ActiveLow | DMAAck3_ActiveLow | EOT3_ActiveLow);
control = mfdcr(DCRN_DMACR3);
break;
/*
* Sets the priority for the DMA channel dmanr.
- * Since this is setup by the hardware init function, this function
+ * Since this is setup by the hardware init function, this function
* can be used to dynamically change the priority of a channel.
*
* Acceptable priorities:
/*
* Returns the width of the peripheral attached to this channel. This assumes
- * that someone who knows the hardware configuration, boot code or some other
+ * that someone who knows the hardware configuration, boot code or some other
* init code, already set the width.
*
* The return value is one of:
* Create a scatter/gather list handle. This is simply a structure which
* describes a scatter/gather list.
*
- * A handle is returned in "handle" which the driver should save in order to
- * be able to access this list later. A chunk of memory will be allocated
- * to be used by the API for internal management purposes, including managing
- * the sg list and allocating memory for the sgl descriptors. One page should
- * be more than enough for that purpose. Perhaps it's a bit wasteful to use
- * a whole page for a single sg list, but most likely there will be only one
+ * A handle is returned in "handle" which the driver should save in order to
+ * be able to access this list later. A chunk of memory will be allocated
+ * to be used by the API for internal management purposes, including managing
+ * the sg list and allocating memory for the sgl descriptors. One page should
+ * be more than enough for that purpose. Perhaps it's a bit wasteful to use
+ * a whole page for a single sg list, but most likely there will be only one
* sg list per channel.
*
* Interrupt notes:
* Each sgl descriptor has a copy of the DMA control word which the DMA engine
- * loads in the control register. The control word has a "global" interrupt
+ * loads in the control register. The control word has a "global" interrupt
* enable bit for that channel. Interrupts are further qualified by a few bits
* in the sgl descriptor count register. In order to setup an sgl, we have to
* know ahead of time whether or not interrupts will be enabled at the completion
* of the transfers. Thus, enable_dma_interrupt()/disable_dma_interrupt() MUST
* be called before calling alloc_dma_handle(). If the interrupt mode will never
- * change after powerup, then enable_dma_interrupt()/disable_dma_interrupt()
+ * change after powerup, then enable_dma_interrupt()/disable_dma_interrupt()
* do not have to be called -- interrupts will be enabled or disabled based
* on how the channel was configured after powerup by the hw_init_dma_channel()
* function. Each sgl descriptor will be setup to interrupt if an error occurs;
- * however, only the last descriptor will be setup to interrupt. Thus, an
+ * however, only the last descriptor will be setup to interrupt. Thus, an
* interrupt will occur (if interrupts are enabled) only after the complete
* sgl transfer is done.
*/
else
/* lets hope this works since in linux/irq.h
* there is no define for EDGE and it's assumed
- * once you set status to LEVEL you would not
+ * once you set status to LEVEL you would not
* want to change it - Armin
*/
desc->status = desc->status & ~IRQ_LEVEL;
else
/* lets hope this works since in linux/irq.h
* there is no define for EDGE and it's assumed
- * once you set status to LEVEL you would not
+ * once you set status to LEVEL you would not
* want to change it - Armin
*/
desc->status = desc->status & ~IRQ_LEVEL;
void __init
ppc4xx_extpic_init(void)
{
- /* set polarity
+ /* set polarity
* 1 = default/pos/rising , 0= neg/falling internal
* 1 = neg/falling , 0= pos/rising external
* Sense
#endif
mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]);
mtdcr(DCRN_UIC_CR(UIC0), 0);
-
+
if (ibm4xxPIC_InitSenses != NULL)
ppc4xx_extpic_init();
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*
- * Console I/O support for Early kernel bringup.
+ * Console I/O support for Early kernel bringup.
*/
#include <linux/config.h>
*/
-#ifdef CONFIG_IBM405GP_INTERNAL_CLOCK
+#ifdef CONFIG_IBM405GP_INTERNAL_CLOCK
/* ftr revisit
** why is bit 19 of chcr0 (0x1000) being set?
*/
static void
ppc405_sercons_write(struct console *co, const char *ptr,
unsigned nb)
-{
+{
int i;
#ifdef CONFIG_UART0_DEBUG_CONSOLE
if (ptr[i] == '\n') {
/* add a carriage return */
-
+
/* wait for transmit reg (possibly fifo) to empty */
while ((*uart_lsr & 0x40) == 0)
;
static int
ppc405_sercons_read(struct console *co, char *ptr, unsigned nb)
-{
+{
#ifdef CONFIG_UART0_DEBUG_CONSOLE
volatile unsigned char *uart_rcv = (char *)0xef600300;
volatile unsigned char *uart_lsr = (char *)0xef600305;
void
register_debug_console(void)
{
- register_console(&ppc405_sercons);
+ register_console(&ppc405_sercons);
}
void
word = irq_nr >> 5;
ppc_cached_irq_mask[word] |= (1 << (31-bit));
- ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask =
+ ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask =
ppc_cached_irq_mask[word];
}
}
irq = ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_sivec >> 26;
/*
- * When we read the sivec without an interrupt to process, we will
+ * When we read the sivec without an interrupt to process, we will
* get back SIU_LEVEL7. In this case, return -1
*/
if (irq == SIU_LEVEL7)
*/
irq = (inl(0x508) >> 24)&0xff;
if ( irq != 0xff ) printk("iack %d\n", irq);
-
+
outb(0x0C, 0x20);
irq = inb(0x20) & 7;
if (irq == 2)
/*
* arch/ppc/syslib/pplus_common.c
- *
+ *
* Common Motorola PowerPlus Platform--really Falcon/Raven or HAWK.
*
* Author: Mark A. Greer
outb(addr>>8, PREP_NVRAM_AS1);
return inb(PREP_NVRAM_DATA);
}
-
+
void __prep prep_nvram_write_val(int addr,
unsigned char val)
{
outb(addr>>8, PREP_NVRAM_AS1);
outb(val, PREP_NVRAM_DATA);
}
-
+
void __init init_prep_nvram(void)
{
unsigned char *nvp;
*nvp = ppc_md.nvram_read_val(i);
nvp++;
}
-
+
/*
* The PReP NvRAM may be any size so read in the header to
* determine how much we must read in order to get the complete
senses[i-off] = (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE);
else
- senses[i-off] = (IRQ_SENSE_EDGE
+ senses[i-off] = (IRQ_SENSE_EDGE
| IRQ_POLARITY_POSITIVE);
}
}
*
* Returns a node pointer with refcount incremented, use
* of_node_put() on it when done.
- */
+ */
struct device_node *of_find_node_by_name(struct device_node *from,
const char *name)
{
* allocation on ppc32
*/
void of_node_put(struct device_node *node)
-{
+{
}
/*
{
unsigned long mask;
int i;
-
- /* Check this one */
+
+ /* Check this one */
mask = bus_space_to_resource_flags(range->space);
for (i=0; i<DEVICE_COUNT_RESOURCE; i++) {
if ((pdev->resource[i].flags & mask) == mask &&
parent = &ioport_resource;
else
goto fail;
-
+
/* Find a PCI parent if any */
nd = node;
pcidev = NULL;
parent = &ioport_resource;
else
return -EINVAL;
-
+
/* Find a PCI parent if any */
nd = node;
pcidev = NULL;
/*
* arch/ppc/syslib/todc_time.c
- *
+ *
* Time of Day Clock support for the M48T35, M48T37, M48T59, and MC146818
* Real Time Clocks/Timekeepers.
*
{
return readb(todc_info->nvram_data + addr);
}
-
+
void
todc_direct_write_val(int addr, unsigned char val)
{
outb(addr>>todc_info->as0_bits, todc_info->nvram_as1);
return inb(todc_info->nvram_data);
}
-
+
void
todc_m48txx_write_val(int addr, unsigned char val)
{
outb(addr, todc_info->nvram_as0);
return inb(todc_info->nvram_data);
}
-
+
void
todc_mc146818_write_val(int addr, unsigned char val)
{
if (todc_info->rtc_type != TODC_TYPE_MC146818) {
switch (todc_info->rtc_type) {
case TODC_TYPE_DS1557:
- case TODC_TYPE_DS1743:
+ case TODC_TYPE_DS1743:
case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */
case TODC_TYPE_DS1747:
break;
ppc_md.nvram_write_val(todc_info->month, tm.tm_mon);
ppc_md.nvram_write_val(todc_info->day_of_month, tm.tm_mday);
ppc_md.nvram_write_val(todc_info->year, tm.tm_year);
-
+
ppc_md.nvram_write_val(todc_info->control_a, save_control);
if (todc_info->rtc_type == TODC_TYPE_MC146818) {
}
return val;
-}
+}
/*
* This was taken from prep_setup.c
ulong tbl, tbu;
long i, loop_count;
u_char sec;
-
+
todc_time_init();
/*
same. */
/*ARGSUSED*/
-static unsigned long
+static unsigned long
insert_bat(unsigned long insn, long value, const char **errmsg)
{
return insn | (((insn >> 21) & 0x1f) << 16);
extraction function just checks that the fields are the same. */
/*ARGSUSED*/
-static unsigned long
+static unsigned long
insert_rbs(unsigned long insn, long value, const char **errmsg)
{
return insn | (((insn >> 21) & 0x1f) << 11);
#ifdef CONFIG_MAGIC_SYSRQ
static void sysrq_handle_xmon(int key, struct pt_regs *regs,
- struct tty_struct *tty)
+ struct tty_struct *tty)
{
xmon(regs);
}
-static struct sysrq_key_op sysrq_xmon_op =
+static struct sysrq_key_op sysrq_xmon_op =
{
.handler = sysrq_handle_xmon,
.help_msg = "Xmon",
{
#ifdef CONFIG_PPC_MULTIPLATFORM
volatile unsigned char *base;
-
+
if (_machine == _MACH_Pmac) {
struct device_node *np;
unsigned long addr;
#endif
TXRDY = 4;
RXRDY = 1;
-
+
np = find_devices("mac-io");
if (np && np->n_addrs)
addr = np->addrs[0].address + 0x13020;
#ifndef __PPC_A_OUT_H__
#define __PPC_A_OUT_H__
-/* grabbed from the intel stuff */
+/* grabbed from the intel stuff */
#define STACK_TOP TASK_SIZE
/* nothing much needed here */
-#define map_page_into_agp(page)
-#define unmap_page_from_agp(page)
-#define flush_agp_mappings()
+#define map_page_into_agp(page)
+#define unmap_page_from_agp(page)
+#define flush_agp_mappings()
#define flush_agp_cache() mb()
#endif
* PowerPC atomic operations
*/
-#ifndef _ASM_PPC_ATOMIC_H_
+#ifndef _ASM_PPC_ATOMIC_H_
#define _ASM_PPC_ATOMIC_H_
typedef struct { volatile int counter; } atomic_t;
/*
* Routines for handling backlight control on PowerBooks
- *
+ *
* For now, implementation resides in arch/ppc/kernel/pmac_support.c
- *
+ *
*/
#ifdef __KERNEL__
#ifndef __ASM_PPC_BACKLIGHT_H
__u32 version;
/* backward compatible down to version: */
__u32 compatible_version;
-
+
/* NEW (vers. 2) this holds the current _logical_ base addr of
the frame buffer (for use by early boot message) */
__u8* logicalDisplayBase;
/* NEW (vers. 4) Detected hw architecture */
__u32 architecture;
-
+
/* The device tree (internal addresses relative to the beginning of the tree,
* device tree offset relative to the beginning of this structure).
* On pre-PCI macintosh (BOOT_ARCH_PCI bit set to 0 in architecture), this
*/
__u32 deviceTreeOffset; /* Device tree offset */
__u32 deviceTreeSize; /* Size of the device tree */
-
+
/* Some infos about the current MacOS display */
__u32 dispDeviceRect[4]; /* left,top,right,bottom */
__u32 dispDeviceDepth; /* (8, 16 or 32) */
/* Optional pointer to boot ramdisk (offset from this structure) */
__u32 ramDisk;
__u32 ramDiskSize; /* size of ramdisk image */
-
+
/* Kernel command line arguments (offset from this structure) */
__u32 kernelParamsOffset;
-
+
/* ALL BELOW NEW (vers. 4) */
-
+
/* This defines the physical memory. Valid with BOOT_ARCH_NUBUS flag
(non-PCI) only. On PCI, memory is contiguous and it's size is in the
device-tree. */
boot_info_map_entry_t
physMemoryMap[MAX_MEM_MAP_SIZE]; /* Where the phys memory is */
__u32 physMemoryMapSize; /* How many entries in map */
-
-
+
+
/* The framebuffer size (optional, currently 0) */
__u32 frameBufferSize; /* Represents a max size, can be 0. */
-
+
/* NEW (vers. 5) */
/* Total params size (args + colormap + device tree + ramdisk) */
/* FIXME: this needs to be written to really do no check -- Cort */
#define csum_partial_copy_nocheck(src, dst, len, sum) \
- csum_partial_copy_generic((src), (dst), (len), (sum), 0, 0)
+ csum_partial_copy_generic((src), (dst), (len), (sum), 0, 0)
/*
* turns a 32-bit partial checksum (e.g. from csum_partial) into a
unsigned long daddr,
unsigned short len,
unsigned short proto,
- unsigned int sum)
+ unsigned int sum)
{
__asm__("\n\
addc %0,%0,%1 \n\
} iic_t;
#define BD_IIC_START ((ushort)0x0400)
-
+
/* SPI parameter RAM.
*/
typedef struct spi {
#define CICR_IEN ((uint)0x00000080) /* Int. enable */
#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
-extern void cpm_install_handler(int vec,
+extern void cpm_install_handler(int vec,
void (*handler)(void *, struct pt_regs *regs), void *dev_id);
extern void cpm_free_handler(int vec);
/*
* include/asm-ppc/gt64260.h
- *
+ *
* Prototypes, etc. for the Marvell/Galileo GT64260 host bridge routines.
*
* Author: Mark A. Greer <mgreer@mvista.com>
gt_write(offs, reg);
}
#endif
-#define gt_set_bits(offs, bits) gt_modify(offs, ~0, bits)
+#define gt_set_bits(offs, bits) gt_modify(offs, ~0, bits)
#define gt_clr_bits(offs, bits) gt_modify(offs, 0, bits)
/*
* include/asm-ppc/gt64260_defs.h
- *
+ *
* Register definitions for the Marvell/Galileo GT64260 host bridge.
*
* Author: Mark A. Greer <mgreer@mvista.com>
#include <linux/smp_lock.h>
#include <asm/irq.h>
-/* The __last_jiffy_stamp field is needed to ensure that no decrementer
- * interrupt is lost on SMP machines. Since on most CPUs it is in the same
- * cache line as local_irq_count, it is cheap to access and is also used on UP
+/* The __last_jiffy_stamp field is needed to ensure that no decrementer
+ * interrupt is lost on SMP machines. Since on most CPUs it is in the same
+ * cache line as local_irq_count, it is cheap to access and is also used on UP
* for uniformity.
*/
typedef struct {
* Gerhard.Wichert@pdb.siemens.de
*
*
- * Redesigned the x86 32-bit VM architecture to deal with
+ * Redesigned the x86 32-bit VM architecture to deal with
* up to 16 Terrabyte physical memory. With current x86 CPUs
* we now support up to 64 Gigabytes physical RAM.
*
/*
* DCRN definitions
- */
+ */
#ifdef CONFIG_440GX
/* SDRs */
-#define DCRN_SDR_CONFIG_ADDR 0xe
+#define DCRN_SDR_CONFIG_ADDR 0xe
#define DCRN_SDR_CONFIG_DATA 0xf
#define DCRN_SDR_PFC0 0x4100
#define DCRN_SDR_PFC1 0x4101
#define DCRN_SDR_MFR_E0RXFH 0x00001000
#define DCRN_SDR_MFR_E1TXFL 0x00000800
#define DCRN_SDR_MFR_E1TXFH 0x00000400
-#define DCRN_SDR_MFR_E1RXFL 0x00000200
+#define DCRN_SDR_MFR_E1RXFL 0x00000200
#define DCRN_SDR_MFR_E1RXFH 0x00000100
#define DCRN_SDR_MFR_E2TXFL 0x00000080
#define DCRN_SDR_MFR_E2TXFH 0x00000040
#define DCRN_MALRXCARR(base) (base + 0x11) /* Rx Channel Active Reset */
#define DCRN_MALRXEOBISR(base) (base + 0x12) /* Rx End of Buffer Interrupt Status */
#define DCRN_MALRXDEIR(base) (base + 0x13) /* Rx Descriptor Error Interrupt */
-#define DCRN_MALTXCTP0R(base) (base + 0x20) /* Channel Tx 0 Channel Table Pointer */
+#define DCRN_MALTXCTP0R(base) (base + 0x20) /* Channel Tx 0 Channel Table Pointer */
#define DCRN_MALTXCTP1R(base) (base + 0x21) /* Channel Tx 1 Channel Table Pointer */
#define DCRN_MALTXCTP2R(base) (base + 0x22) /* Channel Tx 2 Channel Table Pointer */
#define DCRN_MALTXCTP3R(base) (base + 0x23) /* Channel Tx 3 Channel Table Pointer */
-#define DCRN_MALRXCTP0R(base) (base + 0x40) /* Channel Rx 0 Channel Table Pointer */
-#define DCRN_MALRXCTP1R(base) (base + 0x41) /* Channel Rx 1 Channel Table Pointer */
-#define DCRN_MALRCBS0(base) (base + 0x60) /* Channel Rx 0 Channel Buffer Size */
-#define DCRN_MALRCBS1(base) (base + 0x61) /* Channel Rx 1 Channel Buffer Size */
+#define DCRN_MALRXCTP0R(base) (base + 0x40) /* Channel Rx 0 Channel Table Pointer */
+#define DCRN_MALRXCTP1R(base) (base + 0x41) /* Channel Rx 1 Channel Table Pointer */
+#define DCRN_MALRCBS0(base) (base + 0x60) /* Channel Rx 0 Channel Buffer Size */
+#define DCRN_MALRCBS1(base) (base + 0x61) /* Channel Rx 1 Channel Buffer Size */
/* Compatibility DCRN's */
#define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */
#ifndef __PPC_IPC_H__
#define __PPC_IPC_H__
-/*
+/*
* These are used to wrap system calls on PowerPC.
*
* See arch/ppc/kernel/syscalls.c for ugly details..
*
*/
-#define NR_AIC_IRQS 32
+#define NR_AIC_IRQS 32
#define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS)
#elif !defined (CONFIG_403)
* possible level sensitive interrupts assigned and generated internally
* from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
* There are eight external interrupts (IRQs) that can be configured
- * as either level or edge sensitive.
+ * as either level or edge sensitive.
*
* On some implementations, there is also the possibility of an 8259
* through the PCI and PCI-ISA bridges.
#define __PPC_M48T35_H
/* RTC offsets */
-#define M48T35_RTC_FLAGS (-8) /* the negative regs are really T37 only */
+#define M48T35_RTC_FLAGS (-8) /* the negative regs are really T37 only */
#define M48T35_RTC_CENTURY (-7)
-#define M48T35_RTC_AL_SEC (-6)
-#define M48T35_RTC_AL_MIN (-5)
-#define M48T35_RTC_AL_HRS (-4)
-#define M48T35_RTC_AL_DOM (-3)
+#define M48T35_RTC_AL_SEC (-6)
+#define M48T35_RTC_AL_MIN (-5)
+#define M48T35_RTC_AL_HRS (-4)
+#define M48T35_RTC_AL_DOM (-3)
#define M48T35_RTC_INTERRUPT (-2)
#define M48T35_RTC_WATCHDOG (-1)
-#define M48T35_RTC_CONTROL 0 /* T35 starts here */
+#define M48T35_RTC_CONTROL 0 /* T35 starts here */
#define M48T35_RTC_SECONDS 1
#define M48T35_RTC_MINUTES 2
#define M48T35_RTC_HOURS 3
#define M48T35_RTC_MONTH 6
#define M48T35_RTC_YEAR 7
-/* this way help us know which bits go with which regs */
+/* this way help us know which bits go with which regs */
#define M48T35_RTC_FLAGS_BL 0x10
#define M48T35_RTC_FLAGS_AF 0x40
#define M48T35_RTC_FLAGS_WDF 0x80
#define M48T35_RTC_CONTROL_WRITE 0x80
#define M48T35_RTC_CONTROL_READ 0x40
-#define M48T35_RTC_CONTROL_CAL_SIGN 0x20
+#define M48T35_RTC_CONTROL_CAL_SIGN 0x20
#define M48T35_RTC_CONTROL_CAL_VALUE 0x1f
#define M48T35_RTC_CONTROL_LOCKED (M48T35_RTC_WRITE|M48T35_RTC_READ)
#define M48T35_RTC_CONTROL_CALIBRATION (M48T35_RTC_CONTROL_CAL_SIGN|M48T35_RTC_CONTROL_CAL_VALUE)
#define M48T35_RTC_SECONDS_SEC_1 0x0f
-#define M48T35_RTC_SECONDS_SEC_10 0x70
+#define M48T35_RTC_SECONDS_SEC_10 0x70
#define M48T35_RTC_SECONDS_ST 0x80
#define M48T35_RTC_SECONDS_SEC_ALL (M48T35_RTC_SECONDS_SEC_1|M48T35_RTC_SECONDS_SEC_10)
#define M48T35_RTC_MINUTES_MIN_1 0x0f
-#define M48T35_RTC_MINUTES_MIN_10 0x70
+#define M48T35_RTC_MINUTES_MIN_10 0x70
#define M48T35_RTC_MINUTES_MIN_ALL (M48T35_RTC_MINUTES_MIN_1|M48T35_RTC_MINUTES_MIN_10)
#define M48T35_RTC_HOURS_HRS_1 0x0f
* within a MacIO ASIC. It's typically provided by a macio_pci_asic
* PCI device, but could be provided differently as well (nubus
* machines using a fake OF tree).
- *
+ *
* The pdev field can be NULL on non-PCI machines
*/
struct macio_bus
int index; /* macio chip index in system */
#ifdef CONFIG_PCI
struct pci_dev *pdev; /* PCI device hosting this bus */
-#endif
+#endif
};
/*
/*
- * md.h: High speed xor_block operation for RAID4/5
+ * md.h: High speed xor_block operation for RAID4/5
*
*/
-
+
#ifdef __KERNEL__
#ifndef __ASM_MD_H
#define __ASM_MD_H
unsigned long g:1; /* Guarded */
unsigned long :1; /* Unused */
unsigned long pp:2; /* Page protection */
-} PTE;
+} PTE;
/* Values for PP (assumes Ks=0, Kp=1) */
#define PP_RWXX 0 /* Supervisor read/write, User none */
unsigned long bl:11; /* Block size mask */
unsigned long vs:1; /* Supervisor valid */
unsigned long vp:1; /* User valid */
-} BATU;
+} BATU;
typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */
unsigned long brpn:15; /* Real page index (physical address) */
#define TLB_LO 1
#define TLB_HI 0
-
+
#define TLB_DATA TLB_LO
#define TLB_TAG TLB_HI
#define TLB_VALID 0x00000040 /* Entry is valid */
/* Data portion */
-
+
#define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */
#define TLB_PERM_MASK 0x00000300
#define TLB_EX 0x00000200 /* Instruction execution allowed */
/*
* PPC440 support
*/
-#define PPC44x_MMUCR_TID 0x000000ff
+#define PPC44x_MMUCR_TID 0x000000ff
#define PPC44x_MMUCR_STS 0x00010000
#define PPC44x_TLB_PAGEID 0
/*
* arch/ppc/kernel/mpc10x.h
- *
+ *
* Common routines for the Motorola SPS MPC106/8240/107 Host bridge/Mem
* ctlr/EPIC/etc.
*
struct pt_regs;
extern int request_8xxirq(unsigned int irq,
void (*handler)(int, void *, struct pt_regs *),
- unsigned long flags,
+ unsigned long flags,
const char *device,
void *dev_id);
#endif /* !__ASSEMBLY__ */
#ifndef _PPC_MSGBUF_H
#define _PPC_MSGBUF_H
-/*
+/*
* The msqid64_ds structure for the PPC architecture.
*/
/*
* FILE NAME: ocp_ids.h
*
- * BRIEF MODULE DESCRIPTION:
+ * BRIEF MODULE DESCRIPTION:
* OCP device ids based on the ideas from PCI
*
* Maintained by: Armin <akuster@mvista.com>
#define OCP_FUNC_RTC 0x0021
/* Serial 0x0030 - 0x006F*/
-#define OCP_FUNC_16550 0x0031
+#define OCP_FUNC_16550 0x0031
#define OCP_FUNC_SSP 0x0032 /* sync serial port */
#define OCP_FUNC_SCP 0x0033 /* serial controller port */
#define OCP_FUNC_SCC 0x0034 /* serial contoller */
#define OCP_FUNC_SCI 0x0035 /* Smart card */
-#define OCP_FUNC_IIC 0x0040
-#define OCP_FUNC_USB 0x0050
-#define OCP_FUNC_IR 0x0060
+#define OCP_FUNC_IIC 0x0040
+#define OCP_FUNC_USB 0x0050
+#define OCP_FUNC_IR 0x0060
/* Memory devices 0x0090 - 0x009F */
#define OCP_FUNC_SDRAM 0x0091
#define OCP_FUNC_DMA 0x0092
/* Display 0x00A0 - 0x00AF */
-#define OCP_FUNC_VIDEO 0x00A0
+#define OCP_FUNC_VIDEO 0x00A0
#define OCP_FUNC_LED 0x00A1
#define OCP_FUNC_LCD 0x00A2
/* Sound 0x00B0 - 0x00BF */
-#define OCP_FUNC_AUDIO 0x00B0
+#define OCP_FUNC_AUDIO 0x00B0
/* Mass Storage 0x00C0 - 0xxCF */
-#define OCP_FUNC_IDE 0x00C0
+#define OCP_FUNC_IDE 0x00C0
/* Misc 0x00D0 - 0x00DF*/
-#define OCP_FUNC_GPIO 0x00D0
+#define OCP_FUNC_GPIO 0x00D0
#define OCP_FUNC_ZMII 0x00D1
/* Network 0x0200 - 0x02FF */
-#define OCP_FUNC_EMAC 0x0200
+#define OCP_FUNC_EMAC 0x0200
/* Bridge devices 0xE00 - 0xEFF */
-#define OCP_FUNC_HOST 0x0E00
-#define OCP_FUNC_DCR 0x0E01
+#define OCP_FUNC_HOST 0x0E00
+#define OCP_FUNC_DCR 0x0E01
#define OCP_FUNC_OPB 0x0E02
#define OCP_FUNC_PHY 0x0E03
#define OCP_FUNC_EXT 0x0E04
#include <linux/device.h>
#include <asm/prom.h>
-/*
+/*
* The of_platform_bus_type is a bus type used by drivers that do not
* attach to a macio or similar bus but still use OF probing
* mecanism
*/
extern struct bus_type of_platform_bus_type;
-/*
+/*
* The of_device is a kind of "base class" that is a superset of
* struct device for use by devices attached to an OF node and
* probed using OF properties
* ohare.h: definitions for using the "O'Hare" I/O controller chip.
*
* Copyright (C) 1997 Paul Mackerras.
- *
+ *
* BenH: Changed to match those of heathrow (but not all of them). Please
* check if I didn't break anything (especially the media bay).
*/
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
- *
+ *
*/
#ifndef _PPC_KERNEL_OPEN_PIC_H
extern inline int openpic_to_irq(int irq)
{
- /* IRQ 0 usually means 'disabled'.. don't mess with it
- * exceptions to this (sandpoint maybe?)
- * shouldn't use openpic_to_irq
+ /* IRQ 0 usually means 'disabled'.. don't mess with it
+ * exceptions to this (sandpoint maybe?)
+ * shouldn't use openpic_to_irq
*/
if (irq != 0){
return irq += NUM_8259_INTERRUPTS;
#if defined(CONFIG_APUS) && !defined(MODULE)
/* map phys->virtual and virtual->phys for RAM pages */
static inline unsigned long ___pa(unsigned long v)
-{
+{
unsigned long p;
- asm volatile ("1: addis %0, %1, %2;"
+ asm volatile ("1: addis %0, %1, %2;"
".section \".vtop_fixup\",\"aw\";"
".align 1;"
".long 1b;"
".previous;"
- : "=r" (p)
+ : "=r" (p)
: "b" (v), "K" (((-PAGE_OFFSET) >> 16) & 0xffff));
return p;
}
static inline void* ___va(unsigned long p)
-{
+{
unsigned long v;
- asm volatile ("1: addis %0, %1, %2;"
+ asm volatile ("1: addis %0, %1, %2;"
".section \".ptov_fixup\",\"aw\";"
".align 1;"
".long 1b;"
".previous;"
- : "=r" (v)
+ : "=r" (v)
: "b" (p), "K" (((PAGE_OFFSET) >> 16) & 0xffff));
return (void*) v;
int first_busno;
int last_busno;
int bus_offset;
-
+
void *io_base_virt;
unsigned long io_base_phys;
-
+
/* Some machines (PReP) have a non 1:1 mapping of
* the PCI memory space in the CPU bus space
*/
* break this piece out separately.
*/
static inline unsigned char bridge_swizzle(unsigned char pin,
- unsigned char idsel)
+ unsigned char idsel)
{
return (((pin-1) + idsel) % 4) + 1;
}
* The PCI bus bridge can translate addresses issued by the processor(s)
* into a different address on the PCI bus. On 32-bit cpus, we assume
* this mapping is 1-1, but on 64-bit systems it often isn't.
- *
+ *
* Obsolete ! Drivers should now use pci_resource_to_bus
*/
extern unsigned long phys_to_bus(unsigned long pa);
extern unsigned long pci_phys_to_bus(unsigned long pa, int busnr);
extern unsigned long pci_bus_to_phys(unsigned int ba, int busnr);
-
+
/*
* Dynamic DMA Mapping stuff
* Originally stolen from i386 by ajoshi and updated by paulus
* this boolean for bounce buffer decisions.
*/
#define PCI_DMA_BUS_IS_PHYS (1)
-
+
/* Allocate and map kernel buffer using consistent mode DMA for a device.
* hwdev should be valid struct pci_dev pointer for PCI devices,
* NULL for PCI-like buses (ISA, EISA).
unsigned long set)
{
unsigned long old, tmp;
-
+
__asm__ __volatile__("\
1: lwarx %0,0,%3\n\
andc %1,%0,%4\n\
#define pmd_page(pmd) \
(mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT))
#endif
-
+
/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(address) pgd_offset(&init_mm, address)
int nocacheflag, unsigned long *memavailp );
/*
- * Set cache mode of (kernel space) address range.
+ * Set cache mode of (kernel space) address range.
*/
extern void kernel_set_cachemode (unsigned long address, unsigned long size,
unsigned int cmode);
/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
#define kern_addr_valid(addr) (1)
-#define io_remap_page_range remap_page_range
+#define io_remap_page_range remap_page_range
/*
* No page table caches to initialise
/*
* Definition of platform feature hooks for PowerMacs
- *
+ *
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1998 Paul Mackerras &
* Ben. Herrenschmidt.
- *
- *
+ *
+ *
* Note: I removed media-bay details from the feature stuff, I beleive it's
* not worth it, the media-bay driver can directly use the mac-io
* ASIC registers.
- *
+ *
* Implementation note: Currently, none of these functions will block.
* However, they may internally protect themselves with a spinlock
* for way too long. Be prepared for at least some of these to block
* in the future.
- *
+ *
* Unless specifically defined, the result code is assumed to be an
* error when negative, 0 is the default success result. Some functions
* may return additional positive result values.
- *
+ *
* To keep implementation simple, all feature calls are assumed to have
* the prototype parameters (struct device_node* node, int value).
* When either is not used, pass 0.
/*
* Known Mac motherboard models
- *
+ *
* Please, report any error here to benh@kernel.crashing.org, thanks !
- *
+ *
* Note that I don't fully maintain this list for Core99 & MacRISC2
* and I'm considering removing all NewWorld entries from it and
* entirely rely on the model string.
#define PMAC_TYPE_UNKNOWN_PADDINGTON 0x4f /* Unknown but paddington based */
/* Core99 machines based on UniNorth 1.0 and 1.5
- *
+ *
* Note: A single entry here may cover several actual models according
* to the device-tree. (Sawtooth is most tower G4s, FW_IMAC is most
* FireWire based iMacs, etc...). Those machines are too similar to be
/* MacRisc2 with UniNorth 2.0 */
#define PMAC_TYPE_RACKMAC 0x80 /* XServe */
-#define PMAC_TYPE_WINDTUNNEL 0x81
+#define PMAC_TYPE_WINDTUNNEL 0x81
/* MacRISC2 machines based on the Pangea chipset
*/
/*
* Feature calls supported on pmac
- *
+ *
*/
/*
#define PMAC_FTR_SOUND_CHIP_ENABLE PMAC_FTR_DEF(9)
/* -- add various tweaks related to sound routing -- */
-
+
/* PMAC_FTR_AIRPORT_ENABLE (struct device_node* node, 0, int value)
* enable/disable the airport card
*/
#define PMAC_FTR_SLEEP_STATE PMAC_FTR_DEF(15)
/* PMAC_FTR_GET_MB_INFO (NULL, selector, 0)
- *
+ *
* returns some motherboard infos.
* selector: 0 - model id
* 1 - model flags (capabilities)
* on the data structures or constants below in a normal driver
*
*/
-
+
#define MAX_MACIO_CHIPS 2
enum {
#undef __FD_ISSET
static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p)
-{
+{
unsigned long _tmp = fd / __NFDBITS;
unsigned long _rem = fd % __NFDBITS;
return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
#define dma_inb inb
-/*
+/*
* Function return status codes
* These values are used to indicate whether or not the function
* call was successful, or a bad/invalid parameter was passed.
#define DMA_MODE_MM_DEVATDST (SET_DMA_TM(TM_D_MM))
-/*
+/*
* DMA Polarity Configuration Register
*/
#define DMAReq0_ActiveLow (1<<31)
#define DMA_CS3 (1<<28)
#define DMA_TS0 (1<<27) /* End of Transfer has been requested */
-#define DMA_TS1 (1<<26)
-#define DMA_TS2 (1<<25)
-#define DMA_TS3 (1<<24)
+#define DMA_TS1 (1<<26)
+#define DMA_TS2 (1<<25)
+#define DMA_TS3 (1<<24)
#define DMA_CH0_ERR (1<<23) /* DMA Chanel 0 Error */
-#define DMA_CH1_ERR (1<<22)
-#define DMA_CH2_ERR (1<<21)
-#define DMA_CH3_ERR (1<<20)
+#define DMA_CH1_ERR (1<<22)
+#define DMA_CH2_ERR (1<<21)
+#define DMA_CH3_ERR (1<<20)
#define DMA_IN_DMA_REQ0 (1<<19) /* Internal DMA Request is pending */
#define DMA_IN_DMA_REQ1 (1<<18)
#define DMA_EXT_DMA_REQ3 (1<<12)
#define DMA_CH0_BUSY (1<<11) /* DMA Channel 0 Busy */
-#define DMA_CH1_BUSY (1<<10)
-#define DMA_CH2_BUSY (1<<9)
-#define DMA_CH3_BUSY (1<<8)
+#define DMA_CH1_BUSY (1<<10)
+#define DMA_CH2_BUSY (1<<9)
+#define DMA_CH3_BUSY (1<<8)
#define DMA_SG0 (1<<7) /* DMA Channel 0 Scatter/Gather in progress */
-#define DMA_SG1 (1<<6)
-#define DMA_SG2 (1<<5)
-#define DMA_SG3 (1<<4)
+#define DMA_SG1 (1<<6)
+#define DMA_SG2 (1<<5)
+#define DMA_SG3 (1<<4)
#define SET_DMA_CIE_ENABLE(x) (((x)&0x1)<<30)
#define GET_DMA_CIE_ENABLE(x) (((x)&DMA_CIE_ENABLE)>>30)
-#define DMA_TD (1<<29)
+#define DMA_TD (1<<29)
#define SET_DMA_TD(x) (((x)&0x1)<<29)
#define GET_DMA_TD(x) (((x)&DMA_TD)>>29)
#define SET_DMA_PRIORITY(x) (((x)&0x3)<<6) /* DMA Channel Priority */
#define DMA_PRIORITY_MASK SET_DMA_PRIORITY(3)
-#define PRIORITY_LOW 0
+#define PRIORITY_LOW 0
#define PRIORITY_MID_LOW 1
#define PRIORITY_MID_HIGH 2
#define PRIORITY_HIGH 3
#define SSG2_ENABLE (1<<29)
#define SSG3_ENABLE (1<<28)
#define SSG0_MASK_ENABLE (1<<15) /* Enable writing to SSG0 bit */
-#define SSG1_MASK_ENABLE (1<<14)
-#define SSG2_MASK_ENABLE (1<<13)
-#define SSG3_MASK_ENABLE (1<<12)
+#define SSG1_MASK_ENABLE (1<<14)
+#define SSG2_MASK_ENABLE (1<<13)
+#define SSG3_MASK_ENABLE (1<<12)
/*
- * DMA Scatter/Gather Descriptor Bit fields
+ * DMA Scatter/Gather Descriptor Bit fields
*/
#define SG_LINK (1<<31) /* Link */
#define SG_TCI_ENABLE (1<<29) /* Enable Terminal Count Interrupt */
typedef struct {
- /*
+ /*
* Valid polarity settings:
* DMAReq0_ActiveLow
* DMAAck0_ActiveLow
* DMAReq1_ActiveLow
* DMAAck1_ActiveLow
* EOT1_ActiveLow
- *
+ *
* DMAReq2_ActiveLow
* DMAAck2_ActiveLow
* EOT2_ActiveLow
*
- * DMAReq3_ActiveLow
+ * DMAReq3_ActiveLow
* DMAAck3_ActiveLow
* EOT3_ActiveLow
*/
unsigned int polarity;
- char buffer_enable; /* Boolean: buffer enable */
+ char buffer_enable; /* Boolean: buffer enable */
char tce_enable; /* Boolean: terminal count enable */
char etd_output; /* Boolean: eot pin is a tc output */
char pce; /* Boolean: parity check enable */
case 0:
if (p_dma_ch->mode == DMA_MODE_READ) {
/* peripheral to memory */
- mtdcr(DCRN_DMASA0, NULL);
+ mtdcr(DCRN_DMASA0, NULL);
mtdcr(DCRN_DMADA0, p_dma_ch->addr);
}
else if (p_dma_ch->mode == DMA_MODE_WRITE) {
mtdcr(DCRN_DMACR0, control);
break;
case 1:
- if (p_dma_ch->mode == DMA_MODE_READ) {
- mtdcr(DCRN_DMASA1, NULL);
+ if (p_dma_ch->mode == DMA_MODE_READ) {
+ mtdcr(DCRN_DMASA1, NULL);
mtdcr(DCRN_DMADA1, p_dma_ch->addr);
} else if (p_dma_ch->mode == DMA_MODE_WRITE) {
mtdcr(DCRN_DMASA1, p_dma_ch->addr);
mtdcr(DCRN_DMACR1, control);
break;
case 2:
- if (p_dma_ch->mode == DMA_MODE_READ) {
- mtdcr(DCRN_DMASA2, NULL);
+ if (p_dma_ch->mode == DMA_MODE_READ) {
+ mtdcr(DCRN_DMASA2, NULL);
mtdcr(DCRN_DMADA2, p_dma_ch->addr);
- } else if (p_dma_ch->mode == DMA_MODE_WRITE) {
+ } else if (p_dma_ch->mode == DMA_MODE_WRITE) {
mtdcr(DCRN_DMASA2, p_dma_ch->addr);
mtdcr(DCRN_DMADA2, NULL);
}
mtdcr(DCRN_DMACR2, control);
break;
case 3:
- if (p_dma_ch->mode == DMA_MODE_READ) {
- mtdcr(DCRN_DMASA3, NULL);
+ if (p_dma_ch->mode == DMA_MODE_READ) {
+ mtdcr(DCRN_DMASA3, NULL);
mtdcr(DCRN_DMADA3, p_dma_ch->addr);
} else if (p_dma_ch->mode == DMA_MODE_WRITE) {
mtdcr(DCRN_DMASA3, p_dma_ch->addr);
*
* Valid mode values are:
*
- * DMA_MODE_READ peripheral to memory
+ * DMA_MODE_READ peripheral to memory
* DMA_MODE_WRITE memory to peripheral
* DMA_MODE_MM memory to memory
* DMA_MODE_MM_DEVATSRC device-paced memory to memory, device at src
* where each transfer is equal to the bus width. Thus, count
* MUST be a multiple of the bus width.
*/
-static __inline__ void
-set_405gp_dma_count(unsigned int dmanr, unsigned int count)
+static __inline__ void
+set_405gp_dma_count(unsigned int dmanr, unsigned int count)
{
ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
printk("Warning: set_dma_addr addr 0x%x bus width %d\n",
addr, p_dma_ch->pwidth);
}
-#endif
+#endif
/* save dma address and program it later after we know the xfer mode */
- p_dma_ch->addr = addr;
+ p_dma_ch->addr = addr;
}
/*
- * Sets both DMA addresses for a memory to memory transfer.
+ * Sets both DMA addresses for a memory to memory transfer.
* For memory to peripheral or peripheral to memory transfers
* the function set_dma_addr() should be used instead.
*/
-static __inline__ void
+static __inline__ void
set_405gp_dma_addr2(unsigned int dmanr, dma_addr_t src_dma_addr,
dma_addr_t dst_dma_addr)
{
return;
}
if (error)
- printk("Warning: set_dma_addr2 src 0x%x dst 0x%x bus width %d\n",
+ printk("Warning: set_dma_addr2 src 0x%x dst 0x%x bus width %d\n",
src_dma_addr, dst_dma_addr, p_dma_ch->pwidth);
}
#endif
/*
* Enables the channel interrupt.
*
- * If performing a scatter/gatter transfer, this function
+ * If performing a scatter/gatter transfer, this function
* MUST be called before calling alloc_dma_handle() and building
- * the sgl list. Otherwise, interrupts will not be enabled, if
+ * the sgl list. Otherwise, interrupts will not be enabled, if
* they were previously disabled.
*/
-static __inline__ int
+static __inline__ int
enable_405gp_dma_interrupt(unsigned int dmanr)
{
unsigned int control;
/*
* Disables the channel interrupt.
*
- * If performing a scatter/gatter transfer, this function
+ * If performing a scatter/gatter transfer, this function
* MUST be called before calling alloc_dma_handle() and building
- * the sgl list. Otherwise, interrupts will not be disabled, if
+ * the sgl list. Otherwise, interrupts will not be disabled, if
* they were previously enabled.
*/
-static __inline__ int
+static __inline__ int
disable_405gp_dma_interrupt(unsigned int dmanr)
{
unsigned int control;
#ifdef DCRNCAP_DMA_SG
/*
- * Add a new sgl descriptor to the end of a scatter/gather list
- * which was created by alloc_dma_handle().
+ * Add a new sgl descriptor to the end of a scatter/gather list
+ * which was created by alloc_dma_handle().
*
* For a memory to memory transfer, both dma addresses must be
* valid. For a peripheral to memory transfer, one of the addresses
* memory to peripheral: set dst_addr to NULL,
* peripheral to memory: set src_addr to NULL.
*/
-static __inline__ int
+static __inline__ int
add_405gp_dma_sgl(sgl_handle_t handle, dma_addr_t src_addr, dma_addr_t dst_addr,
unsigned int count)
{
sgl_list_info_t *psgl = (sgl_list_info_t *)handle;
ppc_dma_ch_t *p_dma_ch;
-
+
if (!handle) {
#ifdef DEBUG_405DMA
printk("add_dma_sgl: null handle\n");
return DMA_STATUS_GENERAL_ERROR;
}
if (error)
- printk("Alignment warning: add_dma_sgl src 0x%x dst 0x%x count 0x%x bus width var %d\n",
+ printk("Alignment warning: add_dma_sgl src 0x%x dst 0x%x count 0x%x bus width var %d\n",
src_addr, dst_addr, count, p_dma_ch->pwidth);
}
pnext = psgl->phead;
while (pnext) {
- printk("dma descriptor at 0x%x, dma addr 0x%x\n",
+ printk("dma descriptor at 0x%x, dma addr 0x%x\n",
(unsigned)pnext, (unsigned)virt_to_bus(pnext));
printk("control 0x%x src 0x%x dst 0x%x c_count 0x%x, next 0x%x\n",
(unsigned)pnext->control, (unsigned)pnext->src_addr,
*
* An sgl transfer must NOT be active when this function is called.
*/
-static __inline__ int
+static __inline__ int
get_405gp_dma_sgl_residue(sgl_handle_t handle, dma_addr_t *src_addr,
dma_addr_t *dst_addr)
{
*/
pnext++;
- while ((pnext != psgl->ptail) &&
+ while ((pnext != psgl->ptail) &&
((unsigned)pnext < ((unsigned)psgl + SGL_LIST_SIZE))
) {
count_left += pnext->control_count & SG_COUNT_MASK;
/* success */
p_dma_ch = &dma_channels[psgl->dmanr];
return (count_left << p_dma_ch->shift); /* count in bytes */
-
+
} else {
/* this shouldn't happen */
#ifdef DEBUG_405DMA
*
* This function should only be called when the DMA is not active.
*/
-static __inline__ int
+static __inline__ int
delete_405gp_dma_sgl_element(sgl_handle_t handle, dma_addr_t *src_dma_addr,
dma_addr_t *dst_dma_addr)
{
#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
-#define SAVE_2VR(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
-#define SAVE_4VR(n,b,base) SAVE_2VR(n,b,base); SAVE_2VR(n+2,b,base)
-#define SAVE_8VR(n,b,base) SAVE_4VR(n,b,base); SAVE_4VR(n+4,b,base)
+#define SAVE_2VR(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
+#define SAVE_4VR(n,b,base) SAVE_2VR(n,b,base); SAVE_2VR(n+2,b,base)
+#define SAVE_8VR(n,b,base) SAVE_4VR(n,b,base); SAVE_4VR(n+4,b,base)
#define SAVE_16VR(n,b,base) SAVE_8VR(n,b,base); SAVE_8VR(n+8,b,base)
#define SAVE_32VR(n,b,base) SAVE_16VR(n,b,base); SAVE_16VR(n+16,b,base)
#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
-#define REST_2VR(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
-#define REST_4VR(n,b,base) REST_2VR(n,b,base); REST_2VR(n+2,b,base)
-#define REST_8VR(n,b,base) REST_4VR(n,b,base); REST_4VR(n+4,b,base)
-#define REST_16VR(n,b,base) REST_8VR(n,b,base); REST_8VR(n+8,b,base)
+#define REST_2VR(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
+#define REST_4VR(n,b,base) REST_2VR(n,b,base); REST_2VR(n+2,b,base)
+#define REST_8VR(n,b,base) REST_4VR(n,b,base); REST_4VR(n+4,b,base)
+#define REST_16VR(n,b,base) REST_8VR(n,b,base); REST_8VR(n+8,b,base)
#define REST_32VR(n,b,base) REST_16VR(n,b,base); REST_16VR(n+16,b,base)
#ifdef CONFIG_PPC601_SYNC_FIX
/*
* include/asm-ppc/pplus.h
- *
+ *
* Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
*
* Author: Mark A. Greer
#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */
#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
#ifndef CONFIG_BOOKE
-#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
-#define SPRN_DBSR 0x3F0 /* Debug Status Register */
+#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
+#define SPRN_DBSR 0x3F0 /* Debug Status Register */
#define DBSR_IC 0x80000000 /* Instruction Completion */
#define DBSR_BT 0x40000000 /* Branch taken */
#define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */
unsigned long *outputs, ...);
/*
- * PCI <-> OF matching functions
+ * PCI <-> OF matching functions
*/
struct pci_bus;
struct pci_dev;
-/*
+/*
* inclue/asm-ppc/rtc.h
*
* Author: Tom Rini <trini@mvista.com>
#ifndef _PPC_SEMBUF_H
#define _PPC_SEMBUF_H
-/*
+/*
* The semid64_ds structure for PPC architecture.
*/
#ifndef _PPC_SHMBUF_H
#define _PPC_SHMBUF_H
-/*
+/*
* The shmid64_ds structure for PPC architecture.
*/
#define SA_RESTORER 0x04000000
-/*
+/*
* sigaltstack controls
*/
#define SS_ONSTACK 1
#ifdef __KERNEL__
/* ^C ^\ del ^U ^D 1 0 0 0 0 ^W ^R ^Z ^Q ^S ^V ^U */
-#define INIT_C_CC "\003\034\177\025\004\001\000\000\000\000\027\022\032\021\023\026\025"
+#define INIT_C_CC "\003\034\177\025\004\001\000\000\000\000\027\022\032\021\023\026\025"
#endif /* __KERNEL__ */
/* modem lines */
#define __PPC_UNALIGNED_H
/*
- * The PowerPC can do unaligned accesses itself in big endian mode.
+ * The PowerPC can do unaligned accesses itself in big endian mode.
*
* The strange macros are there to make sure these can't
* be misused in a way that makes them not work on other
/*
* Uni-N config space reg. definitions
- *
+ *
* (Little endian)
*/
/* My understanding of UniNorth AGP as of UniNorth rev 1.0x,
* revision 1.5 (x4 AGP) may need further changes.
- *
+ *
* AGP_BASE register contains the base address of the AGP aperture on
* the AGP bus. It doesn't seem to be visible to the CPU as of UniNorth 1.x,
* even if decoding of this address range is enabled in the address select
* register. Apparently, the only supported bases are 256Mb multiples
* (high 4 bits of that register).
- *
+ *
* GART_BASE register appear to contain the physical address of the GART
* in system memory in the high address bits (page aligned), and the
* GART size in the low order bits (number of GART pages)
* This word contains, in little-endian format (!!!), the physical address
* of the page in the high bits, and what appears to be an "enable" bit
* in the LSB bit (0) that must be set to 1 when the entry is valid.
- *
+ *
* Obviously, the GART is not cache coherent and so any change to it
* must be flushed to memory (or maybe just make the GART space non
* cachable). AGP memory itself doens't seem to be cache coherent neither.
- *
+ *
* In order to invalidate the GART (which is probably necessary to inval
* the bridge internal TLBs), the following sequence has to be written,
* in order, to the GART_CTRL register:
- *
+ *
* UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
* UNI_N_CFG_GART_ENABLE
* UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_2xRESET
* UNI_N_CFG_GART_ENABLE
- *
+ *
* As far as AGP "features" are concerned, it looks like fast write may
* not be supported but this has to be confirmed.
- *
+ *
* Turning on AGP seem to require a double invalidate operation, one before
* setting the AGP command register, on after.
- *
+ *
* Turning off AGP seems to require the following sequence: first wait
* for the AGP to be idle by reading the internal status register, then
* write in that order to the GART_CTRL register:
- *
+ *
* UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
* 0
* UNI_N_CFG_GART_2xRESET
* 0
*/
-/*
+/*
* Uni-N memory mapped reg. definitions
- *
+ *
* Those registers are Big-Endian !!
*
* Their meaning come from either Darwin and/or from experiments I made with
/* Version of the UniNorth chip */
#define UNI_N_VERSION 0x0000 /* Known versions: 3,7 and 8 */
-
+
/* This register is used to enable/disable various clocks */
#define UNI_N_CLOCK_CNTL 0x0020
#define UNI_N_CLOCK_CNTL_PCI 0x00000001 /* PCI2 clock control */
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