tg3_chip_reset(tp);
- tw32(GRC_MODE, tp->grc_mode);
+ val = tr32(GRC_MODE);
+ val &= GRC_MODE_HOST_STACKUP;
+ tw32(GRC_MODE, val | tp->grc_mode);
+
tg3_write_mem(tp,
NIC_SRAM_FIRMWARE_MBOX,
NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
u32 misc_ctrl_reg;
u32 cacheline_sz_reg;
u32 pci_state_reg, grc_misc_cfg;
+ u32 val;
u16 pci_cmd;
int err;
udelay(40);
/* Initialize data/descriptor byte/word swapping. */
- tw32(GRC_MODE, tp->grc_mode);
+ val = tr32(GRC_MODE);
+ val &= GRC_MODE_HOST_STACKUP;
+ tw32(GRC_MODE, val | tp->grc_mode);
tg3_switch_clocks(tp);