[ARM PATCH] 1883/1: Bit 4 in pmd should be 0 for the ARMv6 architecture

Patch from Catalin Marinas

Unlike the v5 architecture, the ARM1136 requires that BIT4 is 0 in
the first level page descriptor (ARM1136 TRM, page 6-39). It works
at the moment but it might break future v6 cores.

diff --git a/arch/arm/mm/mm-armv.c b/arch/arm/mm/mm-armv.c
index 1b5a3f75ee0d6590682f21aebe4c8f3c9c4422b4..3a4a7a537b9b7f0f25d2d4bbcc5a47474d6a7f4f 100644 (file)
--- a/arch/arm/mm/mm-armv.c
+++ b/arch/arm/mm/mm-armv.c
@@ -305,27 +305,27 @@ static struct mem_types mem_types[] __initdata = {
        [MT_DEVICE] = {
                .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
                                L_PTE_WRITE,
-               .prot_l1   = PMD_TYPE_TABLE | PMD_BIT4,
-               .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED |
+               .prot_l1   = PMD_TYPE_TABLE,
+               .prot_sect = PMD_TYPE_SECT | PMD_SECT_UNCACHED |
                                PMD_SECT_AP_WRITE,
                .domain    = DOMAIN_IO,
        },
        [MT_CACHECLEAN] = {
-               .prot_sect = PMD_TYPE_SECT | PMD_BIT4,
+               .prot_sect = PMD_TYPE_SECT,
                .domain    = DOMAIN_KERNEL,
        },
        [MT_MINICLEAN] = {
-               .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_MINICACHE,
+               .prot_sect = PMD_TYPE_SECT | PMD_SECT_MINICACHE,
                .domain    = DOMAIN_KERNEL,
        },
        [MT_VECTORS] = {
                .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
                                L_PTE_EXEC,
-               .prot_l1   = PMD_TYPE_TABLE | PMD_BIT4,
+               .prot_l1   = PMD_TYPE_TABLE,
                .domain    = DOMAIN_USER,
        },
        [MT_MEMORY] = {
-               .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_AP_WRITE,
+               .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
                .domain    = DOMAIN_KERNEL,
        }
 };
@@ -353,6 +353,15 @@ static void __init build_mem_type_table(void)
                ecc_mask = 0;
        }
 
+       if (cpu_arch <= CPU_ARCH_ARMv5) {
+               mem_types[MT_DEVICE].prot_l1       |= PMD_BIT4;
+               mem_types[MT_DEVICE].prot_sect     |= PMD_BIT4;
+               mem_types[MT_CACHECLEAN].prot_sect |= PMD_BIT4;
+               mem_types[MT_MINICLEAN].prot_sect  |= PMD_BIT4;
+               mem_types[MT_VECTORS].prot_l1      |= PMD_BIT4;
+               mem_types[MT_MEMORY].prot_sect     |= PMD_BIT4;
+       }
+
        /*
         * ARMv6 and above have extended page tables.
         */
@@ -482,6 +491,7 @@ void setup_mm_for_reboot(char mode)
        pgd_t *pgd;
        pmd_t *pmd;
        int i;
+       int cpu_arch = cpu_architecture();
 
        if (current->mm && current->mm->pgd)
                pgd = current->mm->pgd;
@@ -491,7 +501,9 @@ void setup_mm_for_reboot(char mode)
        for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++) {
                pmdval = (i << PGDIR_SHIFT) |
                         PMD_SECT_AP_WRITE | PMD_SECT_AP_READ |
-                        PMD_BIT4 | PMD_TYPE_SECT;
+                        PMD_TYPE_SECT;
+               if (cpu_arch <= CPU_ARCH_ARMv5)
+                       pmdval |= PMD_BIT4;
                pmd = pmd_offset(pgd + i, i << PGDIR_SHIFT);
                set_pmd(pmd, __pmd(pmdval));
        }