[ARM PATCH] 2123/4: S3C2410 - GPIO IRQ IRQ Filtering and pin number patch

Patch from Ben Dooks

Fixed GPG pin numbering, and missing changelog

Added code to setup the interrupt filtering on
compatible Pins

Signed-off-by: Ben Dooks

diff --git a/arch/arm/mach-s3c2410/gpio.c b/arch/arm/mach-s3c2410/gpio.c
index 22a29e4d71c02a8e55915dd2e45b13e71c1d3580..8996725e9b98ee88e0ff9d6d96a59fe58afd4814 100644 (file)
--- a/arch/arm/mach-s3c2410/gpio.c
+++ b/arch/arm/mach-s3c2410/gpio.c
@@ -26,7 +26,8 @@
  *     30-Sep-2004  BJD  Fixed cfgpin() mask bug
  *     01-Oct-2004  BJD  Added getcfg() to get pin configuration
  *     01-Oct-2004  BJD  Fixed mask bug in pullup() call
- *     01-Oct-2004  BJD  Added getoirq() to turn pin into irqno
+ *     01-Oct-2004  BJD  Added getirq() to turn pin into irqno
+ *     04-Oct-2004  BJD  Added irq filter controls for GPIO
  */
 
 
@@ -155,3 +156,39 @@ int s3c2410_gpio_getirq(unsigned int pin)
 
        return (pin - S3C2410_GPG0) + IRQ_EINT8;
 }
+
+int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
+                          unsigned int config)
+{
+       unsigned long reg = S3C2410_EINFLT0;
+       unsigned long flags;
+       unsigned long val;
+
+       if (pin < S3C2410_GPG8 || pin > S3C2410_GPG15)
+               return -1;
+
+       config &= 0xff;
+
+       pin -= S3C2410_GPG8_EINT16;
+       reg += pin & ~3;
+
+       local_irq_save(flags);
+
+       /* update filter width and clock source */
+
+       val = __raw_readl(reg);
+       val &= ~(0xff << ((pin & 3) * 8));
+       val |= config << ((pin & 3) * 8);
+       __raw_writel(val, reg);
+
+       /* update filter enable */
+
+       val = __raw_readl(S3C2410_EXTINT2);
+       val &= ~(1 << ((pin * 4) + 3));
+       val |= on << ((pin * 4) + 3);
+       __raw_writel(val, S3C2410_EXTINT2);
+
+       local_irq_restore(flags);
+
+       return 0;
+}

diff --git a/include/asm-arm/arch-s3c2410/hardware.h b/include/asm-arm/arch-s3c2410/hardware.h
index d75c3d9e99f3c87e1ebb0a7eff28c126cdc02908..5b58f2aeab46ed57ea7279185c5c2af867c646f2 100644 (file)
--- a/include/asm-arm/arch-s3c2410/hardware.h
+++ b/include/asm-arm/arch-s3c2410/hardware.h
@@ -48,7 +48,6 @@ extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
 
 extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
 
-
 /* s3c2410_gpio_getirq
  *
  * turn the given pin number into the corresponding IRQ number
@@ -60,6 +59,22 @@ extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
 
 extern int s3c2410_gpio_getirq(unsigned int pin);
 
+/* s3c2410_gpio_irqfilter
+ *
+ * set the irq filtering on the given pin
+ *
+ * on = 0 => disable filtering
+ *      1 => enable filtering
+ *
+ * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
+ *          width of filter (0 through 63)
+ *
+ *
+*/
+
+extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
+                                 unsigned int config);
+
 /* s3c2410_gpio_pullup
  *
  * configure the pull-up control on the given pin

diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index e11a898f07db6fa4cb32255fa06bf1f1b68ed3f2..05eb116287830b521b60cf1c5a9f4f38bb0b8486 100644 (file)
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -14,7 +14,8 @@
  *    23-06-2003     BJD     Updated GSTATUS registers
  *    12-03-2004     BJD     Updated include protection
  *    20-07-2004     BJD     Added GPIO pin numbers, added Port A definitions
- */
+ *    04-10-2004     BJD     Fixed number of bugs, added EXT IRQ filter defs
+*/
 
 
 #ifndef __ASM_ARCH_REGS_GPIO_H
@@ -614,31 +615,31 @@
 #define S3C2410_GPG10_OUTP    (0x01 << 20)
 #define S3C2410_GPG10_EINT18  (0x02 << 20)
 
-#define S3C2410_GPG10         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
+#define S3C2410_GPG11         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11)
 #define S3C2410_GPG11_INP     (0x00 << 22)
 #define S3C2410_GPG11_OUTP    (0x01 << 22)
 #define S3C2410_GPG11_EINT19  (0x02 << 22)
 #define S3C2410_GPG11_TCLK1   (0x03 << 22)
 
-#define S3C2410_GPG10         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
+#define S3C2410_GPG12         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12)
 #define S3C2410_GPG12_INP     (0x00 << 24)
 #define S3C2410_GPG12_OUTP    (0x01 << 24)
 #define S3C2410_GPG12_EINT20  (0x02 << 24)
 #define S3C2410_GPG12_XMON    (0x03 << 24)
 
-#define S3C2410_GPG10         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
+#define S3C2410_GPG13         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13)
 #define S3C2410_GPG13_INP     (0x00 << 26)
 #define S3C2410_GPG13_OUTP    (0x01 << 26)
 #define S3C2410_GPG13_EINT21  (0x02 << 26)
 #define S3C2410_GPG13_nXPON   (0x03 << 26)
 
-#define S3C2410_GPG10         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
+#define S3C2410_GPG14         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14)
 #define S3C2410_GPG14_INP     (0x00 << 28)
 #define S3C2410_GPG14_OUTP    (0x01 << 28)
 #define S3C2410_GPG14_EINT22  (0x02 << 28)
 #define S3C2410_GPG14_YMON    (0x03 << 28)
 
-#define S3C2410_GPG10         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
+#define S3C2410_GPG15         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15)
 #define S3C2410_GPG15_INP     (0x00 << 30)
 #define S3C2410_GPG15_OUTP    (0x01 << 30)
 #define S3C2410_GPG15_EINT23  (0x02 << 30)
@@ -783,6 +784,11 @@
 #define S3C2410_EINFLT2           S3C2410_GPIOREG(0x9C)
 #define S3C2410_EINFLT3           S3C2410_GPIOREG(0xA0)
 
+/* values for interrupt filtering */
+#define S3C2410_EINTFLT_PCLK           (0x00)
+#define S3C2410_EINTFLT_EXTCLK         (1<<7)
+#define S3C2410_EINTFLT_WIDTHMSK(x)    ((x) & 0x3f)
+
 /* removed EINTxxxx defs from here, not meant for this */
 
 /* GSTATUS have miscellaneous information in them