arm64: errata: add workaround for cortex-a53 erratum #845719

commit 905e8c5dcaa147163672b06fe9dcb5abaacbc711 upstream.

When running a compat (AArch32) userspace on Cortex-A53, a load at EL0
from a virtual address that matches the bottom 32 bits of the virtual
address used by a recent load at (AArch64) EL1 might return incorrect
data.

This patch works around the issue by writing to the contextidr_el1
register on the exception return path when returning to a 32-bit task.
This workaround is patched in at runtime based on the MIDR value of the
processor.

Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index f1c8e9025cadcc74e0b93c49207abdceada07595..840c232dd4563641bb3e948cb6522b7572b3c97a 100644 (file)
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -306,6 +306,27 @@ config ARM64_ERRATUM_832075
 
          If unsure, say Y.
 
+config ARM64_ERRATUM_845719
+       bool "Cortex-A53: 845719: a load might read incorrect data"
+       depends on COMPAT
+       default y
+       help
+         This option adds an alternative code sequence to work around ARM
+         erratum 845719 on Cortex-A53 parts up to r0p4.
+
+         When running a compat (AArch32) userspace on an affected Cortex-A53
+         part, a load at EL0 from a virtual address that matches the bottom 32
+         bits of the virtual address used by a recent load at (AArch64) EL1
+         might return incorrect data.
+
+         The workaround is to write the contextidr_el1 register on exception
+         return to a 32-bit task.
+         Please note that this does not necessarily enable the workaround,
+         as it depends on the alternative framework, which will only patch
+         the kernel if an affected CPU is detected.
+
+         If unsure, say Y.
+
 endmenu
 
 

diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 07547ccc1f2bd2945edd53a037915c0368ab2400..5fe4befda1a5145a17c288726e944998d38d8020 100644 (file)
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -23,8 +23,9 @@
 
 #define ARM64_WORKAROUND_CLEAN_CACHE           0
 #define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE   1
+#define ARM64_WORKAROUND_845719                        2
 
-#define ARM64_NCAPS                            2
+#define ARM64_NCAPS                            3
 
 #ifndef __ASSEMBLY__
 

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 7c4849489515d672cca4570c4e8c465352ba8223..ad6d52392bb1716dc4d627d29cfa4c97cbeb1575 100644 (file)
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -91,6 +91,14 @@ struct arm64_cpu_capabilities arm64_errata[] = {
                MIDR_RANGE(MIDR_CORTEX_A57, 0x00,
                           (1 << MIDR_VARIANT_SHIFT) | 2),
        },
+#endif
+#ifdef CONFIG_ARM64_ERRATUM_845719
+       {
+       /* Cortex-A53 r0p[01234] */
+               .desc = "ARM erratum 845719",
+               .capability = ARM64_WORKAROUND_845719,
+               MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
+       },
 #endif
        {
        }

diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index fd4fa374e5d2b276821e324eb6066f86bdb514c7..9b870a2815e6fc0625a384ff5e295e22750399ae 100644 (file)
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -21,8 +21,10 @@
 #include <linux/init.h>
 #include <linux/linkage.h>
 
+#include <asm/alternative-asm.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/cpufeature.h>
 #include <asm/errno.h>
 #include <asm/esr.h>
 #include <asm/thread_info.h>
@@ -120,6 +122,24 @@
        ct_user_enter
        ldr     x23, [sp, #S_SP]                // load return stack pointer
        msr     sp_el0, x23
+
+#ifdef CONFIG_ARM64_ERRATUM_845719
+       alternative_insn                                                \
+       "nop",                                                          \
+       "tbz x22, #4, 1f",                                              \
+       ARM64_WORKAROUND_845719
+#ifdef CONFIG_PID_IN_CONTEXTIDR
+       alternative_insn                                                \
+       "nop; nop",                                                     \
+       "mrs x29, contextidr_el1; msr contextidr_el1, x29; 1:",         \
+       ARM64_WORKAROUND_845719
+#else
+       alternative_insn                                                \
+       "nop",                                                          \
+       "msr contextidr_el1, xzr; 1:",                                  \
+       ARM64_WORKAROUND_845719
+#endif
+#endif
        .endif
        msr     elr_el1, x21                    // set up the return data
        msr     spsr_el1, x22