ASoC: SOF: Intel: mtl: Correct rom_status_reg

[ Upstream commit 1f1b820dc3c65b6883da3130ba3b8624dcbf87db ]

ACE1 architecture changed the place where the ROM updates the status code
from the shared SRAM window to HFFLGP1QW0 register for the status and
HFFLGP1QW0 + 4 for the error code.

The rom_status_reg is not used on MTL because it was wrongly assigned based
on older platform convention (SRAM window) and it was giving inconsistent
readings.

Fixes: 064520e8aeaa ("ASoC: SOF: Intel: Add support for MeteorLake (MTL)")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Liam Girdwood <liam.r.girdwood@intel.com>
Link: https://msgid.link/r/20240403105210.17949-3-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/sound/soc/sof/intel/mtl.c b/sound/soc/sof/intel/mtl.c
index 060c34988e90d122caf12cc30fe42ba5f1d0c87d..1454e2a98c3b0c8bb521270d2c9184dece4e71d3 100644 (file)
--- a/sound/soc/sof/intel/mtl.c
+++ b/sound/soc/sof/intel/mtl.c
@@ -727,7 +727,7 @@ const struct sof_intel_dsp_desc mtl_chip_info = {
        .ipc_ack = MTL_DSP_REG_HFIPCXIDA,
        .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
        .ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
-       .rom_status_reg = MTL_DSP_ROM_STS,
+       .rom_status_reg = MTL_DSP_REG_HFFLGPXQWY,
        .rom_init_timeout       = 300,
        .ssp_count = MTL_SSP_COUNT,
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
@@ -755,7 +755,7 @@ const struct sof_intel_dsp_desc arl_s_chip_info = {
        .ipc_ack = MTL_DSP_REG_HFIPCXIDA,
        .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
        .ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
-       .rom_status_reg = MTL_DSP_ROM_STS,
+       .rom_status_reg = MTL_DSP_REG_HFFLGPXQWY,
        .rom_init_timeout       = 300,
        .ssp_count = MTL_SSP_COUNT,
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,

diff --git a/sound/soc/sof/intel/mtl.h b/sound/soc/sof/intel/mtl.h
index ea8c1b83f7127d58f76bd5db018eeb0f0d9b1d7f..3c56427a966bff97682de7f3e5f8305eadc4bc59 100644 (file)
--- a/sound/soc/sof/intel/mtl.h
+++ b/sound/soc/sof/intel/mtl.h
@@ -70,8 +70,8 @@
 #define MTL_DSP_ROM_STS                        MTL_SRAM_WINDOW_OFFSET(0) /* ROM status */
 #define MTL_DSP_ROM_ERROR              (MTL_SRAM_WINDOW_OFFSET(0) + 0x4) /* ROM error code */
 
-#define MTL_DSP_REG_HFFLGPXQWY         0x163200 /* ROM debug status */
-#define MTL_DSP_REG_HFFLGPXQWY_ERROR   0x163204 /* ROM debug error code */
+#define MTL_DSP_REG_HFFLGPXQWY         0x163200 /* DSP core0 status */
+#define MTL_DSP_REG_HFFLGPXQWY_ERROR   0x163204 /* DSP core0 error */
 #define MTL_DSP_REG_HfIMRIS1           0x162088
 #define MTL_DSP_REG_HfIMRIS1_IU_MASK   BIT(0)