perf/x86: Fix exclusion of BTS and LBR for Goldmont

commit b0c1ef52959582144bbea9a2b37db7f4c9e399f7 upstream.

An earlier patch allowed enabling PT and LBR at the same
time on Goldmont. However it also allowed enabling BTS and LBR
at the same time, which is still not supported. Fix this by
bypassing the check only for PT.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: alexander.shishkin@intel.com
Cc: kan.liang@intel.com
Fixes: ccbebba4c6bf ("perf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it")
Link: http://lkml.kernel.org/r/20161209001417.4713-1-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 8c925ecaf5341cb1b8fa19153718976337124efb..7b0f1d932c874cbf6d488e06412a99c3d6917696 100644 (file)
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -364,7 +364,11 @@ int x86_add_exclusive(unsigned int what)
 {
        int i;
 
-       if (x86_pmu.lbr_pt_coexist)
+       /*
+        * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
+        * LBR and BTS are still mutually exclusive.
+        */
+       if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
                return 0;
 
        if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
@@ -387,7 +391,7 @@ fail_unlock:
 
 void x86_del_exclusive(unsigned int what)
 {
-       if (x86_pmu.lbr_pt_coexist)
+       if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
                return;
 
        atomic_dec(&x86_pmu.lbr_exclusive[what]);

diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 181c238d4df9d8b0c7fafe298f3958249cf012f8..4ab002d4c9fd67a6a8b49b60f1d73fc5ed5b63d1 100644 (file)
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -601,7 +601,7 @@ struct x86_pmu {
        u64             lbr_sel_mask;              /* LBR_SELECT valid bits */
        const int       *lbr_sel_map;              /* lbr_select mappings */
        bool            lbr_double_abort;          /* duplicated lbr aborts */
-       bool            lbr_pt_coexist;            /* LBR may coexist with PT */
+       bool            lbr_pt_coexist;            /* (LBR|BTS) may coexist with PT */
 
        /*
         * Intel PT/LBR/BTS are exclusive