#include <asm/agp.h> /* for flush_agp_cache() */
-extern struct agp_bridge_data agp_bridge;
+extern struct agp_bridge_data *agp_bridge;
#define PFX "agpgart: "
#define MB(x) (KB (KB (x)))
#define GB(x) (MB (KB (x)))
-#define CACHE_FLUSH agp_bridge.cache_flush
+#define CACHE_FLUSH agp_bridge->cache_flush
#define A_SIZE_8(x) ((struct aper_size_info_8 *) x)
#define A_SIZE_16(x) ((struct aper_size_info_16 *) x)
#define A_SIZE_32(x) ((struct aper_size_info_32 *) x)
#define A_SIZE_LVL2(x) ((struct aper_size_info_lvl2 *) x)
#define A_SIZE_FIX(x) ((struct aper_size_info_fixed *) x)
-#define A_IDX8() (A_SIZE_8(agp_bridge.aperture_sizes) + i)
-#define A_IDX16() (A_SIZE_16(agp_bridge.aperture_sizes) + i)
-#define A_IDX32() (A_SIZE_32(agp_bridge.aperture_sizes) + i)
-#define A_IDXLVL2() (A_SIZE_LVL2(agp_bridge.aperture_sizes) + i)
-#define A_IDXFIX() (A_SIZE_FIX(agp_bridge.aperture_sizes) + i)
+#define A_IDX8() (A_SIZE_8(agp_bridge->aperture_sizes) + i)
+#define A_IDX16() (A_SIZE_16(agp_bridge->aperture_sizes) + i)
+#define A_IDX32() (A_SIZE_32(agp_bridge->aperture_sizes) + i)
+#define A_IDXLVL2() (A_SIZE_LVL2(agp_bridge->aperture_sizes) + i)
+#define A_IDXFIX() (A_SIZE_FIX(agp_bridge->aperture_sizes) + i)
#define MAXKEY (4096 * 32)
-#define PGE_EMPTY(p) (!(p) || (p) == (unsigned long) agp_bridge.scratch_page)
+#define PGE_EMPTY(p) (!(p) || (p) == (unsigned long) agp_bridge->scratch_page)
/* intel register */
#define INTEL_APBASE 0x10
u32 temp;
struct aper_size_info_32 *values;
- pci_read_config_dword(agp_bridge.dev, ALI_ATTBASE, &temp);
+ pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp);
temp &= ~(0xfffffff0);
- values = A_SIZE_32(agp_bridge.aperture_sizes);
+ values = A_SIZE_32(agp_bridge->aperture_sizes);
- for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+ for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if (temp == values[i].size_value) {
- agp_bridge.previous_size =
- agp_bridge.current_size = (void *) (values + i);
- agp_bridge.aperture_size_idx = i;
+ agp_bridge->previous_size =
+ agp_bridge->current_size = (void *) (values + i);
+ agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
{
u32 temp;
- pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp);
+ pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
// clear tag
- pci_write_config_dword(agp_bridge.dev, ALI_TAGCTRL,
+ pci_write_config_dword(agp_bridge->dev, ALI_TAGCTRL,
((temp & 0xfffffff0) | 0x00000001|0x00000002));
}
struct aper_size_info_32 *previous_size;
u32 temp;
- previous_size = A_SIZE_32(agp_bridge.previous_size);
+ previous_size = A_SIZE_32(agp_bridge->previous_size);
- pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp);
+ pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
// clear tag
- pci_write_config_dword(agp_bridge.dev, ALI_TAGCTRL,
+ pci_write_config_dword(agp_bridge->dev, ALI_TAGCTRL,
((temp & 0xffffff00) | 0x00000001|0x00000002));
- pci_read_config_dword(agp_bridge.dev, ALI_ATTBASE, &temp);
- pci_write_config_dword(agp_bridge.dev, ALI_ATTBASE,
+ pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp);
+ pci_write_config_dword(agp_bridge->dev, ALI_ATTBASE,
((temp & 0x00000ff0) | previous_size->size_value));
}
u32 temp;
struct aper_size_info_32 *current_size;
- current_size = A_SIZE_32(agp_bridge.current_size);
+ current_size = A_SIZE_32(agp_bridge->current_size);
/* aperture size and gatt addr */
- pci_read_config_dword(agp_bridge.dev, ALI_ATTBASE, &temp);
- temp = (((temp & 0x00000ff0) | (agp_bridge.gatt_bus_addr & 0xfffff000))
+ pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp);
+ temp = (((temp & 0x00000ff0) | (agp_bridge->gatt_bus_addr & 0xfffff000))
| (current_size->size_value & 0xf));
- pci_write_config_dword(agp_bridge.dev, ALI_ATTBASE, temp);
+ pci_write_config_dword(agp_bridge->dev, ALI_ATTBASE, temp);
/* tlb control */
- pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp);
- pci_write_config_dword(agp_bridge.dev, ALI_TLBCTRL, ((temp & 0xffffff00) | 0x00000010));
+ pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
+ pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, ((temp & 0xffffff00) | 0x00000010));
/* address to map to */
- pci_read_config_dword(agp_bridge.dev, ALI_APBASE, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev, ALI_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
#if 0
- if (agp_bridge.type == ALI_M1541) {
+ if (agp_bridge->type == ALI_M1541) {
u32 nlvm_addr = 0;
switch (current_size->size_value) {
nlvm_addr--;
nlvm_addr&=0xfff00000;
- nlvm_addr+= agp_bridge.gart_bus_addr;
- nlvm_addr|=(agp_bridge.gart_bus_addr>>12);
+ nlvm_addr+= agp_bridge->gart_bus_addr;
+ nlvm_addr|=(agp_bridge->gart_bus_addr>>12);
printk(KERN_INFO PFX "nlvm top &base = %8x\n",nlvm_addr);
}
#endif
- pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp);
+ pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
temp &= 0xffffff7f; //enable TLB
- pci_write_config_dword(agp_bridge.dev, ALI_TLBCTRL, temp);
+ pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, temp);
return 0;
}
{
/* Memory type is ignored */
- return addr | agp_bridge.masks[0].mask;
+ return addr | agp_bridge->masks[0].mask;
}
static void ali_cache_flush(void)
{
global_cache_flush();
- if (agp_bridge.type == ALI_M1541) {
+ if (agp_bridge->type == ALI_M1541) {
int i, page_count;
u32 temp;
- page_count = 1 << A_SIZE_32(agp_bridge.current_size)->page_order;
+ page_count = 1 << A_SIZE_32(agp_bridge->current_size)->page_order;
for (i = 0; i < PAGE_SIZE * page_count; i += PAGE_SIZE) {
- pci_read_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL, &temp);
- pci_write_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL,
+ pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp);
+ pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
(((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
- (agp_bridge.gatt_bus_addr + i)) |
+ (agp_bridge->gatt_bus_addr + i)) |
ALI_CACHE_FLUSH_EN));
}
}
if (adr == 0)
return 0;
- if (agp_bridge.type == ALI_M1541) {
- pci_read_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL, &temp);
- pci_write_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL,
+ if (agp_bridge->type == ALI_M1541) {
+ pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp);
+ pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
(((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
virt_to_phys(adr)) |
ALI_CACHE_FLUSH_EN ));
global_cache_flush();
- if (agp_bridge.type == ALI_M1541) {
- pci_read_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL, &temp);
- pci_write_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL,
+ if (agp_bridge->type == ALI_M1541) {
+ pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp);
+ pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
(((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
virt_to_phys(addr)) |
ALI_CACHE_FLUSH_EN));
static int __init ali_generic_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = ali_generic_masks;
- agp_bridge.aperture_sizes = (void *) ali_generic_sizes;
- agp_bridge.size_type = U32_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = ali_configure;
- agp_bridge.fetch_size = ali_fetch_size;
- agp_bridge.cleanup = ali_cleanup;
- agp_bridge.tlb_flush = ali_tlbflush;
- agp_bridge.mask_memory = ali_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = ali_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = ali_alloc_page;
- agp_bridge.agp_destroy_page = ali_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = ali_generic_masks;
+ agp_bridge->aperture_sizes = (void *) ali_generic_sizes;
+ agp_bridge->size_type = U32_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = ali_configure;
+ agp_bridge->fetch_size = ali_fetch_size;
+ agp_bridge->cleanup = ali_cleanup;
+ agp_bridge->tlb_flush = ali_tlbflush;
+ agp_bridge->mask_memory = ali_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = ali_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = ali_alloc_page;
+ agp_bridge->agp_destroy_page = ali_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
printk (KERN_INFO PFX "Detected ALi %s chipset\n",
devs[j].chipset_name);
- agp_bridge.type = devs[j].chipset;
+ agp_bridge->type = devs[j].chipset;
if (devs[j].chipset_setup != NULL)
return devs[j].chipset_setup(pdev);
if (agp_try_unsupported) {
printk(KERN_WARNING PFX "Trying generic ALi routines"
" for device id: %04x\n", pdev->device);
- agp_bridge.type = ALI_GENERIC;
+ agp_bridge->type = ALI_GENERIC;
return ali_generic_setup(pdev);
}
/* probe for known chipsets */
if (agp_lookup_host_bridge(dev) != -ENODEV) {
- agp_bridge.dev = dev;
- agp_bridge.capndx = cap_ptr;
+ agp_bridge->dev = dev;
+ agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
- pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
+ pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
ali_agp_driver.dev = dev;
agp_register_driver(&ali_agp_driver);
return 0;
ret_val = pci_module_init(&agp_ali_pci_driver);
if (ret_val)
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
unsigned long address,
int write_access)
{
- alpha_agp_info *agp = agp_bridge.dev_private_data;
+ alpha_agp_info *agp = agp_bridge->dev_private_data;
dma_addr_t dma_addr;
unsigned long pa;
struct page *page;
static int alpha_core_agp_configure(void)
{
- alpha_agp_info *agp = agp_bridge.dev_private_data;
- agp_bridge.gart_bus_addr = agp->aperture.bus_base;
+ alpha_agp_info *agp = agp_bridge->dev_private_data;
+ agp_bridge->gart_bus_addr = agp->aperture.bus_base;
return 0;
}
static void alpha_core_agp_cleanup(void)
{
- alpha_agp_info *agp = agp_bridge.dev_private_data;
+ alpha_agp_info *agp = agp_bridge->dev_private_data;
agp->ops->cleanup(agp);
}
static void alpha_core_agp_tlbflush(agp_memory *mem)
{
- alpha_agp_info *agp = agp_bridge.dev_private_data;
+ alpha_agp_info *agp = agp_bridge->dev_private_data;
alpha_mv.mv_pci_tbi(agp->hose, 0, -1);
}
static unsigned long alpha_core_agp_mask_memory(unsigned long addr, int type)
{
/* Memory type is ignored */
- return addr | agp_bridge.masks[0].mask;
+ return addr | agp_bridge->masks[0].mask;
}
static void alpha_core_agp_enable(u32 mode)
{
- alpha_agp_info *agp = agp_bridge.dev_private_data;
+ alpha_agp_info *agp = agp_bridge->dev_private_data;
agp->mode.lw = agp_collect_device_status(mode, agp->capability.lw);
static int alpha_core_agp_insert_memory(agp_memory *mem, off_t pg_start,
int type)
{
- alpha_agp_info *agp = agp_bridge.dev_private_data;
+ alpha_agp_info *agp = agp_bridge->dev_private_data;
int num_entries, status;
void *temp;
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
num_entries = A_SIZE_FIX(temp)->num_entries;
if ((pg_start + mem->page_count) > num_entries) return -EINVAL;
status = agp->ops->bind(agp, pg_start, mem);
mb();
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return status;
}
static int alpha_core_agp_remove_memory(agp_memory *mem, off_t pg_start,
int type)
{
- alpha_agp_info *agp = agp_bridge.dev_private_data;
+ alpha_agp_info *agp = agp_bridge->dev_private_data;
int status;
status = agp->ops->unbind(agp, pg_start, mem);
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return status;
}
/*
* Build a fake pci_dev struct
*/
- if (!(agp_bridge.dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL))) {
+ if (!(agp_bridge->dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL))) {
return -ENOMEM;
}
- agp_bridge.dev->vendor = 0xffff;
- agp_bridge.dev->device = 0xffff;
- agp_bridge.dev->sysdata = agp->hose;
+ agp_bridge->dev->vendor = 0xffff;
+ agp_bridge->dev->device = 0xffff;
+ agp_bridge->dev->sysdata = agp->hose;
/*
* Fill in the rest of the agp_bridge struct
*/
- agp_bridge.masks = alpha_core_agp_masks;
- agp_bridge.aperture_sizes = aper_size;
- agp_bridge.current_size = aper_size; /* only one entry */
- agp_bridge.size_type = FIXED_APER_SIZE;
- agp_bridge.num_aperture_sizes = 1;
- agp_bridge.dev_private_data = agp;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = alpha_core_agp_configure;
- agp_bridge.fetch_size = alpha_core_agp_fetch_size;
- agp_bridge.cleanup = alpha_core_agp_cleanup;
- agp_bridge.tlb_flush = alpha_core_agp_tlbflush;
- agp_bridge.mask_memory = alpha_core_agp_mask_memory;
- agp_bridge.agp_enable = alpha_core_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = alpha_core_agp_nop;
- agp_bridge.free_gatt_table = alpha_core_agp_nop;
- agp_bridge.insert_memory = alpha_core_agp_insert_memory;
- agp_bridge.remove_memory = alpha_core_agp_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.mode = agp->capability.lw;
- agp_bridge.cant_use_aperture = 1;
- agp_bridge.vm_ops = &alpha_core_agp_vm_ops;
-
- alpha_core_agp_driver.dev = agp_bridge.dev;
+ agp_bridge->masks = alpha_core_agp_masks;
+ agp_bridge->aperture_sizes = aper_size;
+ agp_bridge->current_size = aper_size; /* only one entry */
+ agp_bridge->size_type = FIXED_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 1;
+ agp_bridge->dev_private_data = agp;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = alpha_core_agp_configure;
+ agp_bridge->fetch_size = alpha_core_agp_fetch_size;
+ agp_bridge->cleanup = alpha_core_agp_cleanup;
+ agp_bridge->tlb_flush = alpha_core_agp_tlbflush;
+ agp_bridge->mask_memory = alpha_core_agp_mask_memory;
+ agp_bridge->agp_enable = alpha_core_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = alpha_core_agp_nop;
+ agp_bridge->free_gatt_table = alpha_core_agp_nop;
+ agp_bridge->insert_memory = alpha_core_agp_insert_memory;
+ agp_bridge->remove_memory = alpha_core_agp_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->mode = agp->capability.lw;
+ agp_bridge->cant_use_aperture = 1;
+ agp_bridgevm_ops = &alpha_core_agp_vm_ops;
+
+ alpha_core_agp_driver.dev = agp_bridge->dev;
agp_register_driver(&alpha_core_agp_driver);
printk(KERN_INFO "Detected AGP on hose %d\n", agp->hose->index);
return 0;
{
int ret_val = -ENODEV;
if (alpha_mv.agp_info) {
- agp_bridge.type = ALPHA_CORE_AGP;
+ agp_bridge->type = ALPHA_CORE_AGP;
ret_val = alpha_core_agp_setup();
}
CACHE_FLUSH();
for(i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
- page_map->remapped[i] = agp_bridge.scratch_page;
+ page_map->remapped[i] = agp_bridge->scratch_page;
}
return 0;
#define GET_PAGE_DIR_OFF(addr) (addr >> 22)
#define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
- GET_PAGE_DIR_OFF(agp_bridge.gart_bus_addr))
+ GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
#define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
#define GET_GATT(addr) (amd_irongate_private.gatt_pages[\
GET_PAGE_DIR_IDX(addr)]->remapped)
u32 temp;
int i;
- value = A_SIZE_LVL2(agp_bridge.current_size);
+ value = A_SIZE_LVL2(agp_bridge->current_size);
retval = amd_create_page_map(&page_dir);
if (retval != 0) {
return retval;
return retval;
}
- agp_bridge.gatt_table_real = (u32 *)page_dir.real;
- agp_bridge.gatt_table = (u32 *)page_dir.remapped;
- agp_bridge.gatt_bus_addr = virt_to_phys(page_dir.real);
+ agp_bridge->gatt_table_real = (u32 *)page_dir.real;
+ agp_bridge->gatt_table = (u32 *)page_dir.remapped;
+ agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);
/* Get the address for the gart region.
* This is a bus address even on the alpha, b/c its
* used to program the agp master not the cpu
*/
- pci_read_config_dword(agp_bridge.dev, AMD_APBASE, &temp);
+ pci_read_config_dword(agp_bridge->dev, AMD_APBASE, &temp);
addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
- agp_bridge.gart_bus_addr = addr;
+ agp_bridge->gart_bus_addr = addr;
/* Calculate the agp offset */
for(i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) {
{
struct amd_page_map page_dir;
- page_dir.real = (unsigned long *)agp_bridge.gatt_table_real;
- page_dir.remapped = (unsigned long *)agp_bridge.gatt_table;
+ page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
+ page_dir.remapped = (unsigned long *)agp_bridge->gatt_table;
amd_free_gatt_pages();
amd_free_page_map(&page_dir);
u32 temp;
struct aper_size_info_lvl2 *values;
- pci_read_config_dword(agp_bridge.dev, AMD_APSIZE, &temp);
+ pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
temp = (temp & 0x0000000e);
- values = A_SIZE_LVL2(agp_bridge.aperture_sizes);
- for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+ values = A_SIZE_LVL2(agp_bridge->aperture_sizes);
+ for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if (temp == values[i].size_value) {
- agp_bridge.previous_size =
- agp_bridge.current_size = (void *) (values + i);
+ agp_bridge->previous_size =
+ agp_bridge->current_size = (void *) (values + i);
- agp_bridge.aperture_size_idx = i;
+ agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
u32 temp;
u16 enable_reg;
- current_size = A_SIZE_LVL2(agp_bridge.current_size);
+ current_size = A_SIZE_LVL2(agp_bridge->current_size);
/* Get the memory mapped registers */
- pci_read_config_dword(agp_bridge.dev, AMD_MMBASE, &temp);
+ pci_read_config_dword(agp_bridge->dev, AMD_MMBASE, &temp);
temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
amd_irongate_private.registers = (volatile u8 *) ioremap(temp, 4096);
/* Write out the address of the gatt table */
OUTREG32(amd_irongate_private.registers, AMD_ATTBASE,
- agp_bridge.gatt_bus_addr);
+ agp_bridge->gatt_bus_addr);
/* Write the Sync register */
- pci_write_config_byte(agp_bridge.dev, AMD_MODECNTL, 0x80);
+ pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL, 0x80);
/* Set indexing mode */
- pci_write_config_byte(agp_bridge.dev, AMD_MODECNTL2, 0x00);
+ pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL2, 0x00);
/* Write the enable register */
enable_reg = INREG16(amd_irongate_private.registers, AMD_GARTENABLE);
OUTREG16(amd_irongate_private.registers, AMD_GARTENABLE, enable_reg);
/* Write out the size register */
- pci_read_config_dword(agp_bridge.dev, AMD_APSIZE, &temp);
+ pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
temp = (((temp & ~(0x0000000e)) | current_size->size_value)
| 0x00000001);
- pci_write_config_dword(agp_bridge.dev, AMD_APSIZE, temp);
+ pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
/* Flush the tlb */
OUTREG32(amd_irongate_private.registers, AMD_TLBFLUSH, 0x00000001);
u32 temp;
u16 enable_reg;
- previous_size = A_SIZE_LVL2(agp_bridge.previous_size);
+ previous_size = A_SIZE_LVL2(agp_bridge->previous_size);
enable_reg = INREG16(amd_irongate_private.registers, AMD_GARTENABLE);
enable_reg = (enable_reg & ~(0x0004));
OUTREG16(amd_irongate_private.registers, AMD_GARTENABLE, enable_reg);
/* Write back the previous size and disable gart translation */
- pci_read_config_dword(agp_bridge.dev, AMD_APSIZE, &temp);
+ pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
temp = ((temp & ~(0x0000000f)) | previous_size->size_value);
- pci_write_config_dword(agp_bridge.dev, AMD_APSIZE, temp);
+ pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
iounmap((void *) amd_irongate_private.registers);
}
{
/* Only type 0 is supported by the irongate */
- return addr | agp_bridge.masks[0].mask;
+ return addr | agp_bridge->masks[0].mask;
}
static int amd_insert_memory(agp_memory * mem,
unsigned long *cur_gatt;
unsigned long addr;
- num_entries = A_SIZE_LVL2(agp_bridge.current_size)->num_entries;
+ num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
if (type != 0 || mem->type != 0) {
return -EINVAL;
j = pg_start;
while (j < (pg_start + mem->page_count)) {
- addr = (j * PAGE_SIZE) + agp_bridge.gart_bus_addr;
+ addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = GET_GATT(addr);
if (!PGE_EMPTY(cur_gatt[GET_GATT_OFF(addr)])) {
return -EBUSY;
}
for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
- addr = (j * PAGE_SIZE) + agp_bridge.gart_bus_addr;
+ addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = GET_GATT(addr);
cur_gatt[GET_GATT_OFF(addr)] =
- agp_bridge.mask_memory(mem->memory[i], mem->type);
+ agp_bridge->mask_memory(mem->memory[i], mem->type);
}
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return 0;
}
return -EINVAL;
}
for (i = pg_start; i < (mem->page_count + pg_start); i++) {
- addr = (i * PAGE_SIZE) + agp_bridge.gart_bus_addr;
+ addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = GET_GATT(addr);
cur_gatt[GET_GATT_OFF(addr)] =
- (unsigned long) agp_bridge.scratch_page;
+ (unsigned long) agp_bridge->scratch_page;
}
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return 0;
}
static int __init amd_irongate_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = amd_irongate_masks;
- agp_bridge.aperture_sizes = (void *) amd_irongate_sizes;
- agp_bridge.size_type = LVL2_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = (void *) &amd_irongate_private;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = amd_irongate_configure;
- agp_bridge.fetch_size = amd_irongate_fetch_size;
- agp_bridge.cleanup = amd_irongate_cleanup;
- agp_bridge.tlb_flush = amd_irongate_tlbflush;
- agp_bridge.mask_memory = amd_irongate_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = amd_create_gatt_table;
- agp_bridge.free_gatt_table = amd_free_gatt_table;
- agp_bridge.insert_memory = amd_insert_memory;
- agp_bridge.remove_memory = amd_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = amd_irongate_masks;
+ agp_bridge->aperture_sizes = (void *) amd_irongate_sizes;
+ agp_bridge->size_type = LVL2_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = (void *) &amd_irongate_private;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = amd_irongate_configure;
+ agp_bridge->fetch_size = amd_irongate_fetch_size;
+ agp_bridge->cleanup = amd_irongate_cleanup;
+ agp_bridge->tlb_flush = amd_irongate_tlbflush;
+ agp_bridge->mask_memory = amd_irongate_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = amd_create_gatt_table;
+ agp_bridge->free_gatt_table = amd_free_gatt_table;
+ agp_bridge->insert_memory = amd_insert_memory;
+ agp_bridge->remove_memory = amd_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
while (devs[j].chipset_name != NULL) {
if (pdev->device == devs[j].device_id) {
printk (KERN_INFO PFX "Detected AMD %s chipset\n", devs[j].chipset_name);
- agp_bridge.type = devs[j].chipset;
+ agp_bridge->type = devs[j].chipset;
if (devs[j].chipset_setup != NULL)
return devs[j].chipset_setup(pdev);
if (agp_try_unsupported) {
printk(KERN_WARNING PFX "Trying generic AMD routines"
" for device id: %04x\n", pdev->device);
- agp_bridge.type = AMD_GENERIC;
+ agp_bridge->type = AMD_GENERIC;
return amd_irongate_setup(pdev);
}
return -ENODEV;
if (agp_lookup_host_bridge(dev) != -ENODEV) {
- agp_bridge.dev = dev;
- agp_bridge.capndx = cap_ptr;
+ agp_bridge->dev = dev;
+ agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
- pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
+ pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
amd_k7_agp_driver.dev = dev;
agp_register_driver(&amd_k7_agp_driver);
return 0;
ret_val = pci_module_init(&agp_amdk7_pci_driver);
if (ret_val)
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
/* gatt table should be empty. */
while (j < (pg_start + mem->page_count)) {
- if (!PGE_EMPTY(agp_bridge.gatt_table[j]))
+ if (!PGE_EMPTY(agp_bridge->gatt_table[j]))
return -EBUSY;
j++;
}
}
for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
- addr = agp_bridge.mask_memory(mem->memory[i], mem->type);
+ addr = agp_bridge->mask_memory(mem->memory[i], mem->type);
tmp = addr;
BUG_ON(tmp & 0xffffff0000000ffc);
pte |=(tmp & 0x00000000fffff000);
pte |= 1<<1|1<<0;
- agp_bridge.gatt_table[j] = pte;
+ agp_bridge->gatt_table[j] = pte;
}
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return 0;
}
temp = (temp & 0xe);
values = A_SIZE_32(x86_64_aperture_sizes);
- for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+ for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if (temp == values[i].size_value) {
- agp_bridge.previous_size =
- agp_bridge.current_size = (void *) (values + i);
+ agp_bridge->previous_size =
+ agp_bridge->current_size = (void *) (values + i);
- agp_bridge.aperture_size_idx = i;
+ agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
int current_size;
int tmp, tmp2, i;
u64 aperbar;
- unsigned long gatt_bus = virt_to_phys(agp_bridge.gatt_table_real);
+ unsigned long gatt_bus = virt_to_phys(agp_bridge->gatt_table_real);
/* Configure AGP regs in each x86-64 host bridge. */
pci_for_each_dev(dev) {
if (dev->bus->number==0 &&
PCI_FUNC(dev->devfn)==3 &&
PCI_SLOT(dev->devfn)>=24 && PCI_SLOT(dev->devfn)<=31) {
- agp_bridge.gart_bus_addr = amd_x86_64_configure(dev,gatt_bus);
+ agp_bridge->gart_bus_addr = amd_x86_64_configure(dev,gatt_bus);
hammer = dev;
/*
/* Shadow x86-64 registers into 8151 registers. */
- dev = agp_bridge.dev;
+ dev = agp_bridge->dev;
if (!dev)
return -ENODEV;
static unsigned long amd_8151_mask_memory(unsigned long addr, int type)
{
- return addr | agp_bridge.masks[0].mask;
+ return addr | agp_bridge->masks[0].mask;
}
}
- pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &command);
+ pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &command);
command = agp_collect_device_status(mode, command);
command |= 0x100;
- pci_write_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_COMMAND, command);
+ pci_write_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_COMMAND, command);
agp_device_command(command, 1);
}
static int __init amd_8151_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = amd_8151_masks;
- agp_bridge.aperture_sizes = (void *) amd_8151_sizes;
- agp_bridge.size_type = U32_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = amd_8151_configure;
- agp_bridge.fetch_size = amd_x86_64_fetch_size;
- agp_bridge.cleanup = amd_8151_cleanup;
- agp_bridge.tlb_flush = amd_x86_64_tlbflush;
- agp_bridge.mask_memory = amd_8151_mask_memory;
- agp_bridge.agp_enable = agp_x86_64_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = x86_64_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = amd_8151_masks;
+ agp_bridge->aperture_sizes = (void *) amd_8151_sizes;
+ agp_bridge->size_type = U32_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = amd_8151_configure;
+ agp_bridge->fetch_size = amd_x86_64_fetch_size;
+ agp_bridge->cleanup = amd_8151_cleanup;
+ agp_bridge->tlb_flush = amd_x86_64_tlbflush;
+ agp_bridge->mask_memory = amd_8151_mask_memory;
+ agp_bridge->agp_enable = agp_x86_64_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = x86_64_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
if (cap_ptr == 0)
return -ENODEV;
- agp_bridge.dev = dev;
- agp_bridge.capndx = cap_ptr;
+ agp_bridge->dev = dev;
+ agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
- pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
+ pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
amd_8151_setup(dev);
amd_k8_agp_driver.dev = dev;
agp_register_driver(&amd_k8_agp_driver);
ret_val = pci_module_init(&agp_amdk8_pci_driver);
if (ret_val)
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
- agp_bridge.type = AMD_8151;
+ agp_bridge->type = AMD_8151;
return ret_val;
}
#define AGPGART_VERSION_MAJOR 0
#define AGPGART_VERSION_MINOR 100
-struct agp_bridge_data agp_bridge = { .type = NOT_SUPPORTED };
+struct agp_bridge_data agp_bridge_dummy = { .type = NOT_SUPPORTED };
+struct agp_bridge_data *agp_bridge = &agp_bridge_dummy;
int agp_backend_acquire(void)
{
- if (agp_bridge.type == NOT_SUPPORTED)
+ if (agp_bridge->type == NOT_SUPPORTED)
return -EINVAL;
- if (atomic_read(&agp_bridge.agp_in_use) != 0)
+ if (atomic_read(&agp_bridge->agp_in_use) != 0)
return -EBUSY;
- atomic_inc(&agp_bridge.agp_in_use);
+ atomic_inc(&agp_bridge->agp_in_use);
return 0;
}
void agp_backend_release(void)
{
- if (agp_bridge.type == NOT_SUPPORTED)
+ if (agp_bridge->type == NOT_SUPPORTED)
return;
- atomic_dec(&agp_bridge.agp_in_use);
+ atomic_dec(&agp_bridge->agp_in_use);
}
struct agp_max_table {
{
int size_value, rc, got_gatt=0, got_keylist=0;
- agp_bridge.max_memory_agp = agp_find_max();
- agp_bridge.version = &agp_current_version;
+ agp_bridge->max_memory_agp = agp_find_max();
+ agp_bridge->version = &agp_current_version;
- if (agp_bridge.needs_scratch_page == TRUE) {
+ if (agp_bridge->needs_scratch_page == TRUE) {
void *addr;
- addr = agp_bridge.agp_alloc_page();
+ addr = agp_bridge->agp_alloc_page();
if (addr == NULL) {
printk(KERN_ERR PFX "unable to get memory for scratch page.\n");
return -ENOMEM;
}
- agp_bridge.scratch_page_real = virt_to_phys(addr);
- agp_bridge.scratch_page =
- agp_bridge.mask_memory(agp_bridge.scratch_page_real, 0);
+ agp_bridge->scratch_page_real = virt_to_phys(addr);
+ agp_bridge->scratch_page =
+ agp_bridge->mask_memory(agp_bridge->scratch_page_real, 0);
}
- size_value = agp_bridge.fetch_size();
+ size_value = agp_bridge->fetch_size();
if (size_value == 0) {
printk(KERN_ERR PFX "unable to determine aperture size.\n");
rc = -EINVAL;
goto err_out;
}
- if (agp_bridge.create_gatt_table()) {
+ if (agp_bridge->create_gatt_table()) {
printk(KERN_ERR PFX "unable to get memory for graphics translation table.\n");
rc = -ENOMEM;
goto err_out;
}
got_gatt = 1;
- agp_bridge.key_list = vmalloc(PAGE_SIZE * 4);
- if (agp_bridge.key_list == NULL) {
+ agp_bridge->key_list = vmalloc(PAGE_SIZE * 4);
+ if (agp_bridge->key_list == NULL) {
printk(KERN_ERR PFX "error allocating memory for key lists.\n");
rc = -ENOMEM;
goto err_out;
got_keylist = 1;
/* FIXME vmalloc'd memory not guaranteed contiguous */
- memset(agp_bridge.key_list, 0, PAGE_SIZE * 4);
+ memset(agp_bridge->key_list, 0, PAGE_SIZE * 4);
- if (agp_bridge.configure()) {
+ if (agp_bridge->configure()) {
printk(KERN_ERR PFX "error configuring host chipset.\n");
rc = -EINVAL;
goto err_out;
}
printk(KERN_INFO PFX "AGP aperture is %dM @ 0x%lx\n",
- size_value, agp_bridge.gart_bus_addr);
+ size_value, agp_bridge->gart_bus_addr);
return 0;
err_out:
- if (agp_bridge.needs_scratch_page == TRUE) {
- agp_bridge.agp_destroy_page(phys_to_virt(agp_bridge.scratch_page_real));
+ if (agp_bridge->needs_scratch_page == TRUE) {
+ agp_bridge->agp_destroy_page(phys_to_virt(agp_bridge->scratch_page_real));
}
if (got_gatt)
- agp_bridge.free_gatt_table();
+ agp_bridge->free_gatt_table();
if (got_keylist)
- vfree(agp_bridge.key_list);
+ vfree(agp_bridge->key_list);
return rc;
}
/* cannot be __exit b/c as it could be called from __init code */
static void agp_backend_cleanup(void)
{
- if (agp_bridge.cleanup != NULL)
- agp_bridge.cleanup();
- if (agp_bridge.free_gatt_table != NULL)
- agp_bridge.free_gatt_table();
- if (agp_bridge.key_list)
- vfree(agp_bridge.key_list);
-
- if ((agp_bridge.agp_destroy_page!=NULL) &&
- (agp_bridge.needs_scratch_page == TRUE))
- agp_bridge.agp_destroy_page(phys_to_virt(agp_bridge.scratch_page_real));
+ if (agp_bridge->cleanup != NULL)
+ agp_bridge->cleanup();
+ if (agp_bridge->free_gatt_table != NULL)
+ agp_bridge->free_gatt_table();
+ if (agp_bridge->key_list)
+ vfree(agp_bridge->key_list);
+
+ if ((agp_bridge->agp_destroy_page!=NULL) &&
+ (agp_bridge->needs_scratch_page == TRUE))
+ agp_bridge->agp_destroy_page(phys_to_virt(agp_bridge->scratch_page_real));
}
static int agp_power(struct pm_dev *dev, pm_request_t rq, void *data)
switch(rq)
{
case PM_SUSPEND:
- return agp_bridge.suspend();
+ return agp_bridge->suspend();
case PM_RESUME:
- agp_bridge.resume();
+ agp_bridge->resume();
return 0;
}
return 0;
/* FIXME: What to do with this? */
inter_module_register("drm_agp", THIS_MODULE, &drm_agp);
- pm_register(PM_PCI_DEV, PM_PCI_ID(agp_bridge.dev), agp_power);
+ pm_register(PM_PCI_DEV, PM_PCI_ID(agp_bridge->dev), agp_power);
agp_count++;
return 0;
frontend_err:
agp_backend_cleanup();
err_out:
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
module_put(drv->owner);
drv->dev = NULL;
return ret_val;
if (drv->dev==NULL)
return -ENODEV;
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
pm_unregister_all(agp_power);
agp_frontend_cleanup();
agp_backend_cleanup();
already_initialised = 1;
memset(&agp_bridge, 0, sizeof(struct agp_bridge_data));
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
printk(KERN_INFO "Linux agpgart interface v%d.%d (c) Dave Jones\n",
AGPGART_VERSION_MAJOR, AGPGART_VERSION_MINOR);
struct agp_3_0_dev *dev;
};
- struct pci_dev *td = agp_bridge.dev, *dev;
+ struct pci_dev *td = agp_bridge->dev, *dev;
struct list_head *head = &dev_list->list, *pos;
struct agp_3_0_dev *cur;
struct isoch_data *master, target;
if((ret = agp_3_0_dev_list_sort(dev_list, ndevs)) != 0)
goto free_and_exit;
- pci_read_config_dword(td, agp_bridge.capndx + 0x0c, &tnistat);
- pci_read_config_dword(td, agp_bridge.capndx + 0x04, &tstatus);
+ pci_read_config_dword(td, agp_bridge->capndx + 0x0c, &tnistat);
+ pci_read_config_dword(td, agp_bridge->capndx + 0x04, &tstatus);
/* Extract power-on defaults from the target */
target.maxbw = (tnistat >> 16) & 0xff;
* in the target's NISTAT register, so we need to do this now
* to get an accurate value for ISOCH_N later.
*/
- pci_read_config_word(td, agp_bridge.capndx + 0x20, &tnicmd);
+ pci_read_config_word(td, agp_bridge->capndx + 0x20, &tnicmd);
tnicmd &= ~(0x3 << 6);
tnicmd |= target.y << 6;
- pci_write_config_word(td, agp_bridge.capndx + 0x20, tnicmd);
+ pci_write_config_word(td, agp_bridge->capndx + 0x20, tnicmd);
/* Reread the target's ISOCH_N */
- pci_read_config_dword(td, agp_bridge.capndx + 0x0c, &tnistat);
+ pci_read_config_dword(td, agp_bridge->capndx + 0x0c, &tnistat);
target.n = (tnistat >> 8) & 0xff;
/* Calculate the minimum ISOCH_N needed by each master */
u32 trq, mrq, rem;
unsigned int cdev = 0;
- pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx + 0x04, &tstatus);
+ pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + 0x04, &tstatus);
trq = (tstatus >> 24) & 0xff;
mrq = trq / ndevs;
*/
static int agp_3_0_node_enable(u32 mode, u32 minor)
{
- struct pci_dev *td = agp_bridge.dev, *dev;
+ struct pci_dev *td = agp_bridge->dev, *dev;
u8 bus_num, mcapndx;
u32 isoch, arqsz, cal_cycle, tmp, rate;
u32 tstatus, tcmd, mcmd, mstatus, ncapid;
}
/* Extract some power-on defaults from the target */
- pci_read_config_dword(td, agp_bridge.capndx + 0x04, &tstatus);
+ pci_read_config_dword(td, agp_bridge->capndx + 0x04, &tstatus);
isoch = (tstatus >> 17) & 0x1;
arqsz = (tstatus >> 13) & 0x7;
cal_cycle = (tstatus >> 10) & 0x7;
* Also set the AGP_ENABLE bit, effectively 'turning on' the
* target (this has to be done _before_ turning on the masters).
*/
- pci_read_config_dword(td, agp_bridge.capndx + 0x08, &tcmd);
+ pci_read_config_dword(td, agp_bridge->capndx + 0x08, &tcmd);
tcmd &= ~(0x7 << 10);
tcmd &= ~0x7;
tcmd |= 0x1 << 8;
tcmd |= rate;
- pci_write_config_dword(td, agp_bridge.capndx + 0x08, tcmd);
+ pci_write_config_dword(td, agp_bridge->capndx + 0x08, tcmd);
/*
* Set the target's advertised arqsz value, the minimum supported
{
u32 ncapid, major, minor, agp_3_0;
- pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx, &ncapid);
+ pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx, &ncapid);
major = (ncapid >> 20) & 0xf;
minor = (ncapid >> 16) & 0xf;
printk(KERN_INFO PFX "Found an AGP %d.%d compliant device.\n",major, minor);
if(major >= 3) {
- pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx + 0x4, &agp_3_0);
+ pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + 0x4, &agp_3_0);
/*
* Check to see if we are operating in 3.0 mode
*/
return;
if (key < MAXKEY)
- clear_bit(key, agp_bridge.key_list);
+ clear_bit(key, agp_bridge->key_list);
}
static int agp_get_key(void)
{
int bit;
- bit = find_first_zero_bit(agp_bridge.key_list, MAXKEY);
+ bit = find_first_zero_bit(agp_bridge->key_list, MAXKEY);
if (bit < MAXKEY) {
- set_bit(bit, agp_bridge.key_list);
+ set_bit(bit, agp_bridge->key_list);
return bit;
}
return -1;
{
size_t i;
- if ((agp_bridge.type == NOT_SUPPORTED) || (curr == NULL))
+ if ((agp_bridge->type == NOT_SUPPORTED) || (curr == NULL))
return;
if (curr->is_bound == TRUE)
agp_unbind_memory(curr);
if (curr->type != 0) {
- agp_bridge.free_by_type(curr);
+ agp_bridge->free_by_type(curr);
return;
}
if (curr->page_count != 0) {
for (i = 0; i < curr->page_count; i++) {
- agp_bridge.agp_destroy_page(phys_to_virt(curr->memory[i]));
+ agp_bridge->agp_destroy_page(phys_to_virt(curr->memory[i]));
}
}
agp_free_key(curr->key);
agp_memory *new;
size_t i;
- if (agp_bridge.type == NOT_SUPPORTED)
+ if (agp_bridge->type == NOT_SUPPORTED)
return NULL;
- if ((atomic_read(&agp_bridge.current_memory_agp) + page_count) > agp_bridge.max_memory_agp)
+ if ((atomic_read(&agp_bridge->current_memory_agp) + page_count) > agp_bridge->max_memory_agp)
return NULL;
if (type != 0) {
- new = agp_bridge.alloc_by_type(page_count, type);
+ new = agp_bridge->alloc_by_type(page_count, type);
return new;
}
return NULL;
for (i = 0; i < page_count; i++) {
- void *addr = agp_bridge.agp_alloc_page();
+ void *addr = agp_bridge->agp_alloc_page();
if (addr == NULL) {
agp_free_memory(new);
int current_size;
void *temp;
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
- switch (agp_bridge.size_type) {
+ switch (agp_bridge->size_type) {
case U8_APER_SIZE:
current_size = A_SIZE_8(temp)->size;
break;
int num_entries;
void *temp;
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
- switch (agp_bridge.size_type) {
+ switch (agp_bridge->size_type) {
case U8_APER_SIZE:
num_entries = A_SIZE_8(temp)->num_entries;
break;
int agp_copy_info(agp_kern_info * info)
{
memset(info, 0, sizeof(agp_kern_info));
- if (agp_bridge.type == NOT_SUPPORTED) {
- info->chipset = agp_bridge.type;
+ if (agp_bridge->type == NOT_SUPPORTED) {
+ info->chipset = agp_bridge->type;
return -EIO;
}
- info->version.major = agp_bridge.version->major;
- info->version.minor = agp_bridge.version->minor;
- info->device = agp_bridge.dev;
- info->chipset = agp_bridge.type;
- info->mode = agp_bridge.mode;
- info->aper_base = agp_bridge.gart_bus_addr;
+ info->version.major = agp_bridge->version->major;
+ info->version.minor = agp_bridge->version->minor;
+ info->device = agp_bridge->dev;
+ info->chipset = agp_bridge->type;
+ info->mode = agp_bridge->mode;
+ info->aper_base = agp_bridge->gart_bus_addr;
info->aper_size = agp_return_size();
- info->max_memory = agp_bridge.max_memory_agp;
- info->current_memory = atomic_read(&agp_bridge.current_memory_agp);
- info->cant_use_aperture = agp_bridge.cant_use_aperture;
- info->vm_ops = agp_bridge.vm_ops;
+ info->max_memory = agp_bridge->max_memory_agp;
+ info->current_memory = atomic_read(&agp_bridge->current_memory_agp);
+ info->cant_use_aperture = agp_bridge->cant_use_aperture;
+ info->vm_ops = agp_bridge->vm_ops;
info->page_mask = ~0UL;
return 0;
}
{
int ret_val;
- if ((agp_bridge.type == NOT_SUPPORTED) ||
+ if ((agp_bridge->type == NOT_SUPPORTED) ||
(curr == NULL) || (curr->is_bound == TRUE)) {
return -EINVAL;
}
CACHE_FLUSH();
curr->is_flushed = TRUE;
}
- ret_val = agp_bridge.insert_memory(curr, pg_start, curr->type);
+ ret_val = agp_bridge->insert_memory(curr, pg_start, curr->type);
if (ret_val != 0)
return ret_val;
{
int ret_val;
- if ((agp_bridge.type == NOT_SUPPORTED) || (curr == NULL))
+ if ((agp_bridge->type == NOT_SUPPORTED) || (curr == NULL))
return -EINVAL;
if (curr->is_bound != TRUE)
return -EINVAL;
- ret_val = agp_bridge.remove_memory(curr, curr->pg_start, curr->type);
+ ret_val = agp_bridge->remove_memory(curr, curr->pg_start, curr->type);
if (ret_val != 0)
return ret_val;
{
u32 command;
- pci_read_config_dword(agp_bridge.dev,
- agp_bridge.capndx + PCI_AGP_STATUS,
+ pci_read_config_dword(agp_bridge->dev,
+ agp_bridge->capndx + PCI_AGP_STATUS,
&command);
command = agp_collect_device_status(mode, command);
command |= 0x100;
- pci_write_config_dword(agp_bridge.dev,
- agp_bridge.capndx + PCI_AGP_COMMAND,
+ pci_write_config_dword(agp_bridge->dev,
+ agp_bridge->capndx + PCI_AGP_COMMAND,
command);
agp_device_command(command, 0);
struct page *page;
/* The generic routines can't handle 2 level gatt's */
- if (agp_bridge.size_type == LVL2_APER_SIZE)
+ if (agp_bridge->size_type == LVL2_APER_SIZE)
return -EINVAL;
table = NULL;
- i = agp_bridge.aperture_size_idx;
- temp = agp_bridge.current_size;
+ i = agp_bridge->aperture_size_idx;
+ temp = agp_bridge->current_size;
size = page_order = num_entries = 0;
- if (agp_bridge.size_type != FIXED_APER_SIZE) {
+ if (agp_bridge->size_type != FIXED_APER_SIZE) {
do {
- switch (agp_bridge.size_type) {
+ switch (agp_bridge->size_type) {
case U8_APER_SIZE:
size = A_SIZE_8(temp)->size;
page_order =
if (table == NULL) {
i++;
- switch (agp_bridge.size_type) {
+ switch (agp_bridge->size_type) {
case U8_APER_SIZE:
- agp_bridge.current_size = A_IDX8();
+ agp_bridge->current_size = A_IDX8();
break;
case U16_APER_SIZE:
- agp_bridge.current_size = A_IDX16();
+ agp_bridge->current_size = A_IDX16();
break;
case U32_APER_SIZE:
- agp_bridge.current_size = A_IDX32();
+ agp_bridge->current_size = A_IDX32();
break;
/* This case will never really
* happen.
case FIXED_APER_SIZE:
case LVL2_APER_SIZE:
default:
- agp_bridge.current_size =
- agp_bridge.current_size;
+ agp_bridge->current_size =
+ agp_bridge->current_size;
break;
}
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
} else {
- agp_bridge.aperture_size_idx = i;
+ agp_bridge->aperture_size_idx = i;
}
- } while ((table == NULL) && (i < agp_bridge.num_aperture_sizes));
+ } while ((table == NULL) && (i < agp_bridge->num_aperture_sizes));
} else {
size = ((struct aper_size_info_fixed *) temp)->size;
page_order = ((struct aper_size_info_fixed *) temp)->page_order;
for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
SetPageReserved(page);
- agp_bridge.gatt_table_real = (u32 *) table;
+ agp_bridge->gatt_table_real = (u32 *) table;
agp_gatt_table = (void *)table;
CACHE_FLUSH();
- agp_bridge.gatt_table = ioremap_nocache(virt_to_phys(table),
+ agp_bridge->gatt_table = ioremap_nocache(virt_to_phys(table),
(PAGE_SIZE * (1 << page_order)));
CACHE_FLUSH();
- if (agp_bridge.gatt_table == NULL) {
+ if (agp_bridge->gatt_table == NULL) {
for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
ClearPageReserved(page);
return -ENOMEM;
}
- agp_bridge.gatt_bus_addr = virt_to_phys(agp_bridge.gatt_table_real);
+ agp_bridge->gatt_bus_addr = virt_to_phys(agp_bridge->gatt_table_real);
/* AK: bogus, should encode addresses > 4GB */
for (i = 0; i < num_entries; i++)
- agp_bridge.gatt_table[i] = (unsigned long) agp_bridge.scratch_page;
+ agp_bridge->gatt_table[i] = (unsigned long) agp_bridge->scratch_page;
return 0;
}
void *temp;
struct page *page;
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
- switch (agp_bridge.size_type) {
+ switch (agp_bridge->size_type) {
case U8_APER_SIZE:
page_order = A_SIZE_8(temp)->page_order;
break;
* from the table.
*/
- iounmap(agp_bridge.gatt_table);
- table = (char *) agp_bridge.gatt_table_real;
+ iounmap(agp_bridge->gatt_table);
+ table = (char *) agp_bridge->gatt_table_real;
table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1);
for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
ClearPageReserved(page);
- free_pages((unsigned long) agp_bridge.gatt_table_real, page_order);
+ free_pages((unsigned long) agp_bridge->gatt_table_real, page_order);
return 0;
}
off_t j;
void *temp;
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
- switch (agp_bridge.size_type) {
+ switch (agp_bridge->size_type) {
case U8_APER_SIZE:
num_entries = A_SIZE_8(temp)->num_entries;
break;
j = pg_start;
while (j < (pg_start + mem->page_count)) {
- if (!PGE_EMPTY(agp_bridge.gatt_table[j])) {
+ if (!PGE_EMPTY(agp_bridge->gatt_table[j])) {
return -EBUSY;
}
j++;
}
for (i = 0, j = pg_start; i < mem->page_count; i++, j++)
- agp_bridge.gatt_table[j] =
- agp_bridge.mask_memory(mem->memory[i], mem->type);
+ agp_bridge->gatt_table[j] =
+ agp_bridge->mask_memory(mem->memory[i], mem->type);
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return 0;
}
/* AK: bogus, should encode addresses > 4GB */
for (i = pg_start; i < (mem->page_count + pg_start); i++) {
- agp_bridge.gatt_table[i] =
- (unsigned long) agp_bridge.scratch_page;
+ agp_bridge->gatt_table[i] =
+ (unsigned long) agp_bridge->scratch_page;
}
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return 0;
}
get_page(page);
SetPageLocked(page);
- atomic_inc(&agp_bridge.current_memory_agp);
+ atomic_inc(&agp_bridge->current_memory_agp);
return page_address(page);
}
put_page(page);
unlock_page(page);
free_page((unsigned long)addr);
- atomic_dec(&agp_bridge.current_memory_agp);
+ atomic_dec(&agp_bridge->current_memory_agp);
}
/* End Basic Page Allocation Routines */
void agp_enable(u32 mode)
{
- if (agp_bridge.type == NOT_SUPPORTED)
+ if (agp_bridge->type == NOT_SUPPORTED)
return;
- agp_bridge.agp_enable(mode);
+ agp_bridge->agp_enable(mode);
}
EXPORT_SYMBOL(agp_free_memory);
size = hp_private.gart_size / MB(1);
hp_zx1_sizes[0].size = size;
- agp_bridge.current_size = (void *) &hp_zx1_sizes[0];
+ agp_bridge->current_size = (void *) &hp_zx1_sizes[0];
return size;
}
{
struct _hp_private *hp = &hp_private;
- agp_bridge.gart_bus_addr = hp->gart_base;
- agp_bridge.capndx = pci_find_capability(agp_bridge.dev, PCI_CAP_ID_AGP);
- pci_read_config_dword(agp_bridge.dev,
- agp_bridge.capndx + PCI_AGP_STATUS, &agp_bridge.mode);
+ agp_bridge->gart_bus_addr = hp->gart_base;
+ agp_bridge->capndx = pci_find_capability(agp_bridge->dev, PCI_CAP_ID_AGP);
+ pci_read_config_dword(agp_bridge->dev,
+ agp_bridge->capndx + PCI_AGP_STATUS, &agp_bridge->mode);
if (hp->io_pdir_owner) {
OUTREG64(hp->registers, HP_ZX1_PDIR_BASE,
}
for (i = 0; i < hp->gatt_entries; i++) {
- hp->gatt[i] = (unsigned long) agp_bridge.scratch_page;
+ hp->gatt[i] = (unsigned long) agp_bridge->scratch_page;
}
return 0;
for (k = 0;
k < hp->io_pages_per_kpage;
k++, j++, paddr += hp->io_page_size) {
- hp->gatt[j] = agp_bridge.mask_memory(paddr, type);
+ hp->gatt[j] = agp_bridge->mask_memory(paddr, type);
}
}
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return 0;
}
io_pg_start = hp->io_pages_per_kpage * pg_start;
io_pg_count = hp->io_pages_per_kpage * mem->page_count;
for (i = io_pg_start; i < io_pg_count + io_pg_start; i++) {
- hp->gatt[i] = agp_bridge.scratch_page;
+ hp->gatt[i] = agp_bridge->scratch_page;
}
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return 0;
}
static int __init hp_zx1_setup (struct pci_dev *pdev __attribute__((unused)))
{
- agp_bridge.masks = hp_zx1_masks;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.size_type = FIXED_APER_SIZE;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = hp_zx1_configure;
- agp_bridge.fetch_size = hp_zx1_fetch_size;
- agp_bridge.cleanup = hp_zx1_cleanup;
- agp_bridge.tlb_flush = hp_zx1_tlbflush;
- agp_bridge.mask_memory = hp_zx1_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = hp_zx1_create_gatt_table;
- agp_bridge.free_gatt_table = hp_zx1_free_gatt_table;
- agp_bridge.insert_memory = hp_zx1_insert_memory;
- agp_bridge.remove_memory = hp_zx1_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.cant_use_aperture = 1;
+ agp_bridge->masks = hp_zx1_masks;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->size_type = FIXED_APER_SIZE;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = hp_zx1_configure;
+ agp_bridge->fetch_size = hp_zx1_fetch_size;
+ agp_bridge->cleanup = hp_zx1_cleanup;
+ agp_bridge->tlb_flush = hp_zx1_tlbflush;
+ agp_bridge->mask_memory = hp_zx1_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = hp_zx1_create_gatt_table;
+ agp_bridge->free_gatt_table = hp_zx1_free_gatt_table;
+ agp_bridge->insert_memory = hp_zx1_insert_memory;
+ agp_bridge->remove_memory = hp_zx1_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->cant_use_aperture = 1;
return hp_zx1_ioc_init();
}
static int __init agp_find_supported_device(struct pci_dev *dev)
{
- agp_bridge.dev = dev;
+ agp_bridge->dev = dev;
/* ZX1 LBAs can be either PCI or AGP bridges */
if (pci_find_capability(dev, PCI_CAP_ID_AGP)) {
printk(KERN_INFO PFX "Detected HP ZX1 AGP chipset at %s\n",
dev->slot_name);
- agp_bridge.type = HP_ZX1;
- agp_bridge.dev = dev;
+ agp_bridge->type = HP_ZX1;
+ agp_bridge->dev = dev;
return hp_zx1_setup(dev);
}
return -ENODEV;
ret_val = pci_module_init(&agp_hp_pci_driver);
if (ret_val)
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
struct aper_size_info_8 *values;
/* Determine the GART page size */
- pci_read_config_byte(agp_bridge.dev, INTEL_I460_GXBCTL, &temp);
+ pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &temp);
i460.io_page_shift = (temp & I460_4M_PS) ? 22 : 12;
pr_debug("i460_fetch_size: io_page_shift=%d\n", i460.io_page_shift);
return 0;
}
- values = A_SIZE_8(agp_bridge.aperture_sizes);
+ values = A_SIZE_8(agp_bridge->aperture_sizes);
- pci_read_config_byte(agp_bridge.dev, INTEL_I460_AGPSIZ, &temp);
+ pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp);
/* Exit now if the IO drivers for the GART SRAMS are turned off */
if (temp & I460_SRAM_IO_DISABLE) {
else
i460.dynamic_apbase = INTEL_I460_APBASE;
- for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+ for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
/*
* Dynamically calculate the proper num_entries and page_order values for
* the define aperture sizes. Take care not to shift off the end of
values[i].page_order = log2((sizeof(u32)*values[i].num_entries) >> PAGE_SHIFT);
}
- for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+ for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
/* Neglect control bits when matching up size_value */
if ((temp & I460_AGPSIZ_MASK) == values[i].size_value) {
- agp_bridge.previous_size = agp_bridge.current_size = (void *) (values + i);
- agp_bridge.aperture_size_idx = i;
+ agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
+ agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
{
u8 temp;
- pci_read_config_byte(agp_bridge.dev, INTEL_I460_AGPSIZ, &temp);
- pci_write_config_byte(agp_bridge.dev, INTEL_I460_AGPSIZ,
+ pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp);
+ pci_write_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ,
((temp & ~I460_AGPSIZ_MASK) | size_value));
}
{
struct aper_size_info_8 *previous_size;
- previous_size = A_SIZE_8(agp_bridge.previous_size);
+ previous_size = A_SIZE_8(agp_bridge->previous_size);
i460_write_agpsiz(previous_size->size_value);
if (I460_IO_PAGE_SHIFT > PAGE_SHIFT)
temp.large = 0;
- current_size = A_SIZE_8(agp_bridge.current_size);
+ current_size = A_SIZE_8(agp_bridge->current_size);
i460_write_agpsiz(current_size->size_value);
/*
* This has to be done since the AGP aperture can be above 4GB on
* 460 based systems.
*/
- pci_read_config_dword(agp_bridge.dev, i460.dynamic_apbase, &(temp.small[0]));
- pci_read_config_dword(agp_bridge.dev, i460.dynamic_apbase + 4, &(temp.small[1]));
+ pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase, &(temp.small[0]));
+ pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase + 4, &(temp.small[1]));
/* Clear BAR control bits */
- agp_bridge.gart_bus_addr = temp.large & ~((1UL << 3) - 1);
+ agp_bridge->gart_bus_addr = temp.large & ~((1UL << 3) - 1);
- pci_read_config_byte(agp_bridge.dev, INTEL_I460_GXBCTL, &scratch);
- pci_write_config_byte(agp_bridge.dev, INTEL_I460_GXBCTL,
+ pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &scratch);
+ pci_write_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL,
(scratch & 0x02) | I460_GXBCTL_OOG | I460_GXBCTL_BWC);
/*
/*
* Load up the fixed address of the GART SRAMS which hold our GATT table.
*/
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
page_order = A_SIZE_8(temp)->page_order;
num_entries = A_SIZE_8(temp)->num_entries;
i460.gatt = ioremap(INTEL_I460_ATTBASE, PAGE_SIZE << page_order);
/* These are no good, the should be removed from the agp_bridge strucure... */
- agp_bridge.gatt_table_real = NULL;
- agp_bridge.gatt_table = NULL;
- agp_bridge.gatt_bus_addr = 0;
+ agp_bridge->gatt_table_real = NULL;
+ agp_bridge->gatt_table = NULL;
+ agp_bridge->gatt_bus_addr = 0;
for (i = 0; i < num_entries; ++i)
WR_GATT(i, 0);
int num_entries, i;
void *temp;
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
num_entries = A_SIZE_8(temp)->num_entries;
io_pg_start = I460_IOPAGES_PER_KPAGE * pg_start;
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
num_entries = A_SIZE_8(temp)->num_entries;
if ((io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count) > num_entries) {
for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
paddr = mem->memory[i];
for (k = 0; k < I460_IOPAGES_PER_KPAGE; k++, j++, paddr += io_page_size)
- WR_GATT(j, agp_bridge.mask_memory(paddr, mem->type));
+ WR_GATT(j, agp_bridge->mask_memory(paddr, mem->type));
}
WR_FLUSH_GATT(j - 1);
return 0;
lp->paddr = virt_to_phys(lpage);
lp->refcount = 0;
- atomic_add(I460_KPAGES_PER_IOPAGE, &agp_bridge.current_memory_agp);
+ atomic_add(I460_KPAGES_PER_IOPAGE, &agp_bridge->current_memory_agp);
return 0;
}
lp->alloced_map = NULL;
free_pages((unsigned long) phys_to_virt(lp->paddr), I460_IO_PAGE_SHIFT - PAGE_SHIFT);
- atomic_sub(I460_KPAGES_PER_IOPAGE, &agp_bridge.current_memory_agp);
+ atomic_sub(I460_KPAGES_PER_IOPAGE, &agp_bridge->current_memory_agp);
}
static int i460_insert_memory_large_io_page (agp_memory * mem, off_t pg_start, int type)
struct lp_desc *start, *end, *lp;
void *temp;
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
num_entries = A_SIZE_8(temp)->num_entries;
/* Figure out what pg_start means in terms of our large GART pages */
if (i460_alloc_large_page(lp) < 0)
return -ENOMEM;
pg = lp - i460.lp_desc;
- WR_GATT(pg, agp_bridge.mask_memory(lp->paddr, 0));
+ WR_GATT(pg, agp_bridge->mask_memory(lp->paddr, 0));
WR_FLUSH_GATT(pg);
}
struct lp_desc *start, *end, *lp;
void *temp;
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
num_entries = A_SIZE_8(temp)->num_entries;
/* Figure out what pg_start means in terms of our large GART pages */
static unsigned long i460_mask_memory (unsigned long addr, int type)
{
/* Make sure the returned address is a valid GATT entry */
- return (agp_bridge.masks[0].mask
+ return (agp_bridge->masks[0].mask
| (((addr & ~((1 << I460_IO_PAGE_SHIFT) - 1)) & 0xffffff000) >> 12));
}
static int __init intel_i460_setup (struct pci_dev *pdev __attribute__((unused)))
{
- agp_bridge.masks = i460_masks;
- agp_bridge.aperture_sizes = (void *) i460_sizes;
- agp_bridge.size_type = U8_APER_SIZE;
- agp_bridge.num_aperture_sizes = 3;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = i460_configure;
- agp_bridge.fetch_size = i460_fetch_size;
- agp_bridge.cleanup = i460_cleanup;
- agp_bridge.tlb_flush = i460_tlb_flush;
- agp_bridge.mask_memory = i460_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = i460_create_gatt_table;
- agp_bridge.free_gatt_table = i460_free_gatt_table;
+ agp_bridge->masks = i460_masks;
+ agp_bridge->aperture_sizes = (void *) i460_sizes;
+ agp_bridge->size_type = U8_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 3;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = i460_configure;
+ agp_bridge->fetch_size = i460_fetch_size;
+ agp_bridge->cleanup = i460_cleanup;
+ agp_bridge->tlb_flush = i460_tlb_flush;
+ agp_bridge->mask_memory = i460_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = i460_create_gatt_table;
+ agp_bridge->free_gatt_table = i460_free_gatt_table;
#if I460_LARGE_IO_PAGES
- agp_bridge.insert_memory = i460_insert_memory;
- agp_bridge.remove_memory = i460_remove_memory;
- agp_bridge.agp_alloc_page = i460_alloc_page;
- agp_bridge.agp_destroy_page = i460_destroy_page;
+ agp_bridge->insert_memory = i460_insert_memory;
+ agp_bridge->remove_memory = i460_remove_memory;
+ agp_bridge->agp_alloc_page = i460_alloc_page;
+ agp_bridge->agp_destroy_page = i460_destroy_page;
#else
- agp_bridge.insert_memory = i460_insert_memory_small_io_page;
- agp_bridge.remove_memory = i460_remove_memory_small_io_page;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->insert_memory = i460_insert_memory_small_io_page;
+ agp_bridge->remove_memory = i460_remove_memory_small_io_page;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
#endif
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 1;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 1;
return 0;
}
if (cap_ptr == 0)
return -ENODEV;
- agp_bridge.dev = dev;
- agp_bridge.capndx = cap_ptr;
+ agp_bridge->dev = dev;
+ agp_bridge->capndx = cap_ptr;
intel_i460_setup(dev);
i460_agp_driver.dev = dev;
agp_register_driver(&i460_agp_driver);
ret_val = pci_module_init(&agp_intel_i460_pci_driver);
if (ret_val)
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
/*
* For AGP 3.0 APSIZE is now 16 bits
*/
- pci_read_config_word (agp_bridge.dev, INTEL_I7505_APSIZE, &tmp);
+ pci_read_config_word (agp_bridge->dev, INTEL_I7505_APSIZE, &tmp);
tmp = (tmp & 0xfff);
- values = A_SIZE_16(agp_bridge.aperture_sizes);
+ values = A_SIZE_16(agp_bridge->aperture_sizes);
- for (i=0; i < agp_bridge.num_aperture_sizes; i++) {
+ for (i=0; i < agp_bridge->num_aperture_sizes; i++) {
if (tmp == values[i].size_value) {
- agp_bridge.previous_size = agp_bridge.current_size =
+ agp_bridge->previous_size = agp_bridge->current_size =
(void *)(values + i);
- agp_bridge.aperture_size_idx = i;
+ agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
static void intel_7505_tlbflush(agp_memory *mem)
{
u32 temp;
- pci_read_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, &temp);
- pci_write_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, temp & ~(1 << 7));
- pci_read_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, &temp);
- pci_write_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, temp | (1 << 7));
+ pci_read_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, &temp);
+ pci_write_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, temp & ~(1 << 7));
+ pci_read_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, &temp);
+ pci_write_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, temp | (1 << 7));
}
static void intel_7505_cleanup(void)
{
aper_size_info_16 *previous_size;
- previous_size = A_SIZE_16(agp_bridge.previous_size);
- pci_write_config_byte(agp_bridge.dev, INTEL_I7505_APSIZE,
+ previous_size = A_SIZE_16(agp_bridge->previous_size);
+ pci_write_config_byte(agp_bridge->dev, INTEL_I7505_APSIZE,
previous_size->size_value);
}
u32 temp;
aper_size_info_16 *current_size;
- current_size = A_SIZE_16(agp_bridge.current_size);
+ current_size = A_SIZE_16(agp_bridge->current_size);
/* aperture size */
- pci_write_config_word(agp_bridge.dev, INTEL_I7505_APSIZE,
+ pci_write_config_word(agp_bridge->dev, INTEL_I7505_APSIZE,
current_size->size_value);
/* address to map to */
- pci_read_config_dword(agp_bridge.dev, INTEL_I7505_NAPBASELO, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev, INTEL_I7505_NAPBASELO, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase */
- pci_write_config_dword(agp_bridge.dev, INTEL_I7505_ATTBASE,
- agp_bridge.gatt_bus_addr);
+ pci_write_config_dword(agp_bridge->dev, INTEL_I7505_ATTBASE,
+ agp_bridge->gatt_bus_addr);
/* agpctrl */
- pci_write_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, 0x0000);
+ pci_write_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, 0x0000);
/* clear error registers */
- pci_write_config_byte(agp_bridge.dev, INTEL_I7505_ERRSTS, 0xff);
+ pci_write_config_byte(agp_bridge->dev, INTEL_I7505_ERRSTS, 0xff);
return 0;
}
static int __init intel_7505_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = intel_generic_masks;
- agp_bridge.aperture_sizes = (void *) intel_7505_sizes;
- agp_bridge.size_type = U16_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = intel_7505_configure;
- agp_bridge.fetch_size = intel_7505_fetch_size;
- agp_bridge.cleanup = intel_7505_cleanup;
- agp_bridge.tlb_flush = intel_7505_tlbflush;
- agp_bridge.mask_memory = intel_mask_memory;
- agp_bridge.agp_enable = i7505_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = intel_generic_masks;
+ agp_bridge->aperture_sizes = (void *) intel_7505_sizes;
+ agp_bridge->size_type = U16_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = intel_7505_configure;
+ agp_bridge->fetch_size = intel_7505_fetch_size;
+ agp_bridge->cleanup = intel_7505_cleanup;
+ agp_bridge->tlb_flush = intel_7505_tlbflush;
+ agp_bridge->mask_memory = intel_mask_memory;
+ agp_bridge->agp_enable = i7505_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
if (pdev->device == devs[j].device_id) {
printk (KERN_INFO PFX "Detected Intel %s chipset\n",
devs[j].chipset_name);
- agp_bridge.type = devs[j].chipset;
+ agp_bridge->type = devs[j].chipset;
if (devs[j].chipset_setup != NULL)
return devs[j].chipset_setup(pdev);
return -ENODEV;
if (agp_lookup_host_bridge(dev) != -ENODEV) {
- agp_bridge.dev = dev;
- agp_bridge.capndx = cap_ptr;
+ agp_bridge->dev = dev;
+ agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
- pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode)
+ pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode)
i7x05_agp_driver.dev = dev;
agp_register_driver(&i7x05_agp_driver);
return 0;
ret_val = pci_module_init(&agp_i7x05_pci_driver);
if (ret_val)
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
u32 smram_miscc;
struct aper_size_info_fixed *values;
- pci_read_config_dword(agp_bridge.dev, I810_SMRAM_MISCC, &smram_miscc);
- values = A_SIZE_FIX(agp_bridge.aperture_sizes);
+ pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
+ values = A_SIZE_FIX(agp_bridge->aperture_sizes);
if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
printk(KERN_WARNING PFX "i810 is disabled\n");
return 0;
}
if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
- agp_bridge.previous_size =
- agp_bridge.current_size = (void *) (values + 1);
- agp_bridge.aperture_size_idx = 1;
+ agp_bridge->previous_size =
+ agp_bridge->current_size = (void *) (values + 1);
+ agp_bridge->aperture_size_idx = 1;
return values[1].size;
} else {
- agp_bridge.previous_size =
- agp_bridge.current_size = (void *) (values);
- agp_bridge.aperture_size_idx = 0;
+ agp_bridge->previous_size =
+ agp_bridge->current_size = (void *) (values);
+ agp_bridge->aperture_size_idx = 0;
return values[0].size;
}
u32 temp;
int i;
- current_size = A_SIZE_FIX(agp_bridge.current_size);
+ current_size = A_SIZE_FIX(agp_bridge->current_size);
pci_read_config_dword(intel_i810_private.i810_dev, I810_MMADDR, &temp);
temp &= 0xfff80000;
intel_i810_private.num_dcache_entries = 1024;
}
pci_read_config_dword(intel_i810_private.i810_dev, I810_GMADDR, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
OUTREG32(intel_i810_private.registers, I810_PGETBL_CTL,
- agp_bridge.gatt_bus_addr | I810_PGETBL_ENABLED);
+ agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED);
CACHE_FLUSH();
- if (agp_bridge.needs_scratch_page == TRUE) {
+ if (agp_bridge->needs_scratch_page == TRUE) {
for (i = 0; i < current_size->num_entries; i++) {
OUTREG32(intel_i810_private.registers,
I810_PTE_BASE + (i * 4),
- agp_bridge.scratch_page);
+ agp_bridge->scratch_page);
}
}
return 0;
int i, j, num_entries;
void *temp;
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
num_entries = A_SIZE_FIX(temp)->num_entries;
if ((pg_start + mem->page_count) > num_entries) {
return -EINVAL;
}
for (j = pg_start; j < (pg_start + mem->page_count); j++) {
- if (!PGE_EMPTY(agp_bridge.gatt_table[j])) {
+ if (!PGE_EMPTY(agp_bridge->gatt_table[j])) {
return -EBUSY;
}
}
I810_PTE_VALID);
}
CACHE_FLUSH();
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return 0;
}
if((type == AGP_PHYS_MEMORY) && (mem->type == AGP_PHYS_MEMORY))
for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
OUTREG32(intel_i810_private.registers,
I810_PTE_BASE + (j * 4),
- agp_bridge.mask_memory(mem->memory[i], mem->type));
+ agp_bridge->mask_memory(mem->memory[i], mem->type));
}
CACHE_FLUSH();
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return 0;
}
for (i = pg_start; i < (mem->page_count + pg_start); i++) {
OUTREG32(intel_i810_private.registers,
I810_PTE_BASE + (i * 4),
- agp_bridge.scratch_page);
+ agp_bridge->scratch_page);
}
CACHE_FLUSH();
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return 0;
}
if (new == NULL)
return NULL;
- addr = agp_bridge.agp_alloc_page();
+ addr = agp_bridge->agp_alloc_page();
if (addr == NULL) {
/* Free this structure */
{
agp_free_key(curr->key);
if(curr->type == AGP_PHYS_MEMORY) {
- agp_bridge.agp_destroy_page(phys_to_virt(curr->memory[0]));
+ agp_bridge->agp_destroy_page(phys_to_virt(curr->memory[0]));
vfree(curr->memory);
}
kfree(curr);
static unsigned long intel_i810_mask_memory(unsigned long addr, int type)
{
/* Type checking must be done elsewhere */
- return addr | agp_bridge.masks[type].mask;
+ return addr | agp_bridge->masks[type].mask;
}
static int __init intel_i810_setup(struct pci_dev *i810_dev)
{
intel_i810_private.i810_dev = i810_dev;
- agp_bridge.masks = intel_i810_masks;
- agp_bridge.aperture_sizes = (void *) intel_i810_sizes;
- agp_bridge.size_type = FIXED_APER_SIZE;
- agp_bridge.num_aperture_sizes = 2;
- agp_bridge.dev_private_data = (void *) &intel_i810_private;
- agp_bridge.needs_scratch_page = TRUE;
- agp_bridge.configure = intel_i810_configure;
- agp_bridge.fetch_size = intel_i810_fetch_size;
- agp_bridge.cleanup = intel_i810_cleanup;
- agp_bridge.tlb_flush = intel_i810_tlbflush;
- agp_bridge.mask_memory = intel_i810_mask_memory;
- agp_bridge.agp_enable = intel_i810_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = intel_i810_insert_entries;
- agp_bridge.remove_memory = intel_i810_remove_entries;
- agp_bridge.alloc_by_type = intel_i810_alloc_by_type;
- agp_bridge.free_by_type = intel_i810_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = intel_i810_masks;
+ agp_bridge->aperture_sizes = (void *) intel_i810_sizes;
+ agp_bridge->size_type = FIXED_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 2;
+ agp_bridge->dev_private_data = (void *) &intel_i810_private;
+ agp_bridge->needs_scratch_page = TRUE;
+ agp_bridge->configure = intel_i810_configure;
+ agp_bridge->fetch_size = intel_i810_fetch_size;
+ agp_bridge->cleanup = intel_i810_cleanup;
+ agp_bridge->tlb_flush = intel_i810_tlbflush;
+ agp_bridge->mask_memory = intel_i810_mask_memory;
+ agp_bridge->agp_enable = intel_i810_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = intel_i810_insert_entries;
+ agp_bridge->remove_memory = intel_i810_remove_entries;
+ agp_bridge->alloc_by_type = intel_i810_alloc_by_type;
+ agp_bridge->free_by_type = intel_i810_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
u8 rdct;
static const int ddt[4] = { 0, 16, 32, 64 };
- pci_read_config_word(agp_bridge.dev,I830_GMCH_CTRL,&gmch_ctrl);
+ pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
case I830_GMCH_GMS_STOLEN_512:
int num_entries;
u32 temp;
- size = agp_bridge.current_size;
+ size = agp_bridge->current_size;
page_order = size->page_order;
num_entries = size->num_entries;
- agp_bridge.gatt_table_real = 0;
+ agp_bridge->gatt_table_real = 0;
pci_read_config_dword(intel_i830_private.i830_dev,I810_MMADDR,&temp);
temp &= 0xfff80000;
/* we have to call this as early as possible after the MMIO base address is known */
intel_i830_init_gtt_entries();
- agp_bridge.gatt_table = NULL;
+ agp_bridge->gatt_table = NULL;
- agp_bridge.gatt_bus_addr = temp;
+ agp_bridge->gatt_bus_addr = temp;
return(0);
}
u16 gmch_ctrl;
struct aper_size_info_fixed *values;
- pci_read_config_word(agp_bridge.dev,I830_GMCH_CTRL,&gmch_ctrl);
- values = A_SIZE_FIX(agp_bridge.aperture_sizes);
+ pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
+ values = A_SIZE_FIX(agp_bridge->aperture_sizes);
if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
- agp_bridge.previous_size = agp_bridge.current_size = (void *) values;
- agp_bridge.aperture_size_idx = 0;
+ agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
+ agp_bridge->aperture_size_idx = 0;
return(values[0].size);
} else {
- agp_bridge.previous_size = agp_bridge.current_size = (void *) values;
- agp_bridge.aperture_size_idx = 1;
+ agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
+ agp_bridge->aperture_size_idx = 1;
return(values[1].size);
}
u16 gmch_ctrl;
int i;
- current_size = A_SIZE_FIX(agp_bridge.current_size);
+ current_size = A_SIZE_FIX(agp_bridge->current_size);
pci_read_config_dword(intel_i830_private.i830_dev,I810_GMADDR,&temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
- pci_read_config_word(agp_bridge.dev,I830_GMCH_CTRL,&gmch_ctrl);
+ pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
gmch_ctrl |= I830_GMCH_ENABLED;
- pci_write_config_word(agp_bridge.dev,I830_GMCH_CTRL,gmch_ctrl);
+ pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
- OUTREG32(intel_i830_private.registers,I810_PGETBL_CTL,agp_bridge.gatt_bus_addr | I810_PGETBL_ENABLED);
+ OUTREG32(intel_i830_private.registers,I810_PGETBL_CTL,agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED);
CACHE_FLUSH();
- if (agp_bridge.needs_scratch_page == TRUE)
+ if (agp_bridge->needs_scratch_page == TRUE)
for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++)
- OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (i * 4),agp_bridge.scratch_page);
+ OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (i * 4),agp_bridge->scratch_page);
return (0);
}
int i,j,num_entries;
void *temp;
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
num_entries = A_SIZE_FIX(temp)->num_entries;
if (pg_start < intel_i830_private.gtt_entries) {
for (i = 0, j = pg_start; i < mem->page_count; i++, j++)
OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (j * 4),
- agp_bridge.mask_memory(mem->memory[i], mem->type));
+ agp_bridge->mask_memory(mem->memory[i], mem->type));
CACHE_FLUSH();
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return(0);
}
}
for (i = pg_start; i < (mem->page_count + pg_start); i++)
- OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (i * 4),agp_bridge.scratch_page);
+ OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (i * 4),agp_bridge->scratch_page);
CACHE_FLUSH();
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return (0);
}
if (nw == NULL) return(NULL);
- addr = agp_bridge.agp_alloc_page();
+ addr = agp_bridge->agp_alloc_page();
if (addr == NULL) {
/* free this structure */
agp_free_memory(nw);
{
intel_i830_private.i830_dev = i830_dev;
- agp_bridge.masks = intel_i810_masks;
- agp_bridge.aperture_sizes = (void *) intel_i830_sizes;
- agp_bridge.size_type = FIXED_APER_SIZE;
- agp_bridge.num_aperture_sizes = 2;
+ agp_bridge->masks = intel_i810_masks;
+ agp_bridge->aperture_sizes = (void *) intel_i830_sizes;
+ agp_bridge->size_type = FIXED_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 2;
- agp_bridge.dev_private_data = (void *) &intel_i830_private;
- agp_bridge.needs_scratch_page = TRUE;
+ agp_bridge->dev_private_data = (void *) &intel_i830_private;
+ agp_bridge->needs_scratch_page = TRUE;
- agp_bridge.configure = intel_i830_configure;
- agp_bridge.fetch_size = intel_i830_fetch_size;
- agp_bridge.cleanup = intel_i830_cleanup;
- agp_bridge.tlb_flush = intel_i810_tlbflush;
- agp_bridge.mask_memory = intel_i810_mask_memory;
- agp_bridge.agp_enable = intel_i810_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
+ agp_bridge->configure = intel_i830_configure;
+ agp_bridge->fetch_size = intel_i830_fetch_size;
+ agp_bridge->cleanup = intel_i830_cleanup;
+ agp_bridge->tlb_flush = intel_i810_tlbflush;
+ agp_bridge->mask_memory = intel_i810_mask_memory;
+ agp_bridge->agp_enable = intel_i810_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = intel_i830_create_gatt_table;
- agp_bridge.free_gatt_table = intel_i830_free_gatt_table;
+ agp_bridge->create_gatt_table = intel_i830_create_gatt_table;
+ agp_bridge->free_gatt_table = intel_i830_free_gatt_table;
- agp_bridge.insert_memory = intel_i830_insert_entries;
- agp_bridge.remove_memory = intel_i830_remove_entries;
- agp_bridge.alloc_by_type = intel_i830_alloc_by_type;
- agp_bridge.free_by_type = intel_i810_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->insert_memory = intel_i830_insert_entries;
+ agp_bridge->remove_memory = intel_i830_remove_entries;
+ agp_bridge->alloc_by_type = intel_i830_alloc_by_type;
+ agp_bridge->free_by_type = intel_i810_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return(0);
}
u16 temp;
struct aper_size_info_16 *values;
- pci_read_config_word(agp_bridge.dev, INTEL_APSIZE, &temp);
- values = A_SIZE_16(agp_bridge.aperture_sizes);
+ pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
+ values = A_SIZE_16(agp_bridge->aperture_sizes);
- for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+ for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if (temp == values[i].size_value) {
- agp_bridge.previous_size = agp_bridge.current_size = (void *) (values + i);
- agp_bridge.aperture_size_idx = i;
+ agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
+ agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
u8 temp;
struct aper_size_info_8 *values;
- pci_read_config_byte(agp_bridge.dev, INTEL_APSIZE, &temp);
+ pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
/* Intel 815 chipsets have a _weird_ APSIZE register with only
* one non-reserved bit, so mask the others out ... */
- if (agp_bridge.type == INTEL_I815)
+ if (agp_bridge->type == INTEL_I815)
temp &= (1 << 3);
- values = A_SIZE_8(agp_bridge.aperture_sizes);
+ values = A_SIZE_8(agp_bridge->aperture_sizes);
- for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+ for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if (temp == values[i].size_value) {
- agp_bridge.previous_size =
- agp_bridge.current_size = (void *) (values + i);
- agp_bridge.aperture_size_idx = i;
+ agp_bridge->previous_size =
+ agp_bridge->current_size = (void *) (values + i);
+ agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
static void intel_tlbflush(agp_memory * mem)
{
- pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x2200);
- pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x2280);
+ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
+ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
}
static void intel_8xx_tlbflush(agp_memory * mem)
{
u32 temp;
- pci_read_config_dword(agp_bridge.dev, INTEL_AGPCTRL, &temp);
- pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, temp & ~(1 << 7));
- pci_read_config_dword(agp_bridge.dev, INTEL_AGPCTRL, &temp);
- pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, temp | (1 << 7));
+ pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
+ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
+ pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
+ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
}
u16 temp;
struct aper_size_info_16 *previous_size;
- previous_size = A_SIZE_16(agp_bridge.previous_size);
- pci_read_config_word(agp_bridge.dev, INTEL_NBXCFG, &temp);
- pci_write_config_word(agp_bridge.dev, INTEL_NBXCFG, temp & ~(1 << 9));
- pci_write_config_word(agp_bridge.dev, INTEL_APSIZE, previous_size->size_value);
+ previous_size = A_SIZE_16(agp_bridge->previous_size);
+ pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
+ pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
+ pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
}
u16 temp;
struct aper_size_info_8 *previous_size;
- previous_size = A_SIZE_8(agp_bridge.previous_size);
- pci_read_config_word(agp_bridge.dev, INTEL_NBXCFG, &temp);
- pci_write_config_word(agp_bridge.dev, INTEL_NBXCFG, temp & ~(1 << 9));
- pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, previous_size->size_value);
+ previous_size = A_SIZE_8(agp_bridge->previous_size);
+ pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
+ pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
+ pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
}
u16 temp2;
struct aper_size_info_16 *current_size;
- current_size = A_SIZE_16(agp_bridge.current_size);
+ current_size = A_SIZE_16(agp_bridge->current_size);
/* aperture size */
- pci_write_config_word(agp_bridge.dev, INTEL_APSIZE, current_size->size_value);
+ pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
/* address to map to */
- pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture base */
- pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr);
+ pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
/* agpctrl */
- pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x2280);
+ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
/* paccfg/nbxcfg */
- pci_read_config_word(agp_bridge.dev, INTEL_NBXCFG, &temp2);
- pci_write_config_word(agp_bridge.dev, INTEL_NBXCFG,
+ pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
+ pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
(temp2 & ~(1 << 10)) | (1 << 9));
/* clear any possible error conditions */
- pci_write_config_byte(agp_bridge.dev, INTEL_ERRSTS + 1, 7);
+ pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
return 0;
}
u8 temp2;
struct aper_size_info_8 *current_size;
- current_size = A_SIZE_8(agp_bridge.current_size);
+ current_size = A_SIZE_8(agp_bridge->current_size);
/* aperture size */
- pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE,
+ pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
current_size->size_value);
/* address to map to */
- pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture base */
/* the Intel 815 chipset spec. says that bits 29-31 in the
* ATTBASE register are reserved -> try not to write them */
- if (agp_bridge.gatt_bus_addr & INTEL_815_ATTBASE_MASK)
+ if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK)
panic("gatt bus addr too high");
- pci_read_config_dword(agp_bridge.dev, INTEL_ATTBASE, &addr);
+ pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
addr &= INTEL_815_ATTBASE_MASK;
- addr |= agp_bridge.gatt_bus_addr;
- pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, addr);
+ addr |= agp_bridge->gatt_bus_addr;
+ pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
/* agpctrl */
- pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000);
+ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
/* apcont */
- pci_read_config_byte(agp_bridge.dev, INTEL_815_APCONT, &temp2);
- pci_write_config_byte(agp_bridge.dev, INTEL_815_APCONT, temp2 | (1 << 1));
+ pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
+ pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
/* clear any possible error conditions */
/* Oddness : this chipset seems to have no ERRSTS register ! */
u8 temp;
struct aper_size_info_8 *previous_size;
- previous_size = A_SIZE_8(agp_bridge.previous_size);
- pci_read_config_byte(agp_bridge.dev, INTEL_I820_RDCR, &temp);
- pci_write_config_byte(agp_bridge.dev, INTEL_I820_RDCR,
+ previous_size = A_SIZE_8(agp_bridge->previous_size);
+ pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
+ pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
temp & ~(1 << 1));
- pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE,
+ pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
previous_size->size_value);
}
u8 temp2;
struct aper_size_info_8 *current_size;
- current_size = A_SIZE_8(agp_bridge.current_size);
+ current_size = A_SIZE_8(agp_bridge->current_size);
/* aperture size */
- pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, current_size->size_value);
+ pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
/* address to map to */
- pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture base */
- pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr);
+ pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
/* agpctrl */
- pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000);
+ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
/* global enable aperture access */
/* This flag is not accessed through MCHCFG register as in */
/* i850 chipset. */
- pci_read_config_byte(agp_bridge.dev, INTEL_I820_RDCR, &temp2);
- pci_write_config_byte(agp_bridge.dev, INTEL_I820_RDCR, temp2 | (1 << 1));
+ pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
+ pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
/* clear any possible AGP-related error conditions */
- pci_write_config_word(agp_bridge.dev, INTEL_I820_ERRSTS, 0x001c);
+ pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
return 0;
}
u16 temp2;
struct aper_size_info_8 *current_size;
- current_size = A_SIZE_8(agp_bridge.current_size);
+ current_size = A_SIZE_8(agp_bridge->current_size);
/* aperture size */
- pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, current_size->size_value);
+ pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
/* address to map to */
- pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture base */
- pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr);
+ pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
/* agpctrl */
- pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000);
+ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
/* mcgcfg */
- pci_read_config_word(agp_bridge.dev, INTEL_I840_MCHCFG, &temp2);
- pci_write_config_word(agp_bridge.dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
+ pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
+ pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
/* clear any possible error conditions */
- pci_write_config_word(agp_bridge.dev, INTEL_I840_ERRSTS, 0xc000);
+ pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
return 0;
}
u8 temp2;
struct aper_size_info_8 *current_size;
- current_size = A_SIZE_8(agp_bridge.current_size);
+ current_size = A_SIZE_8(agp_bridge->current_size);
/* aperture size */
- pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, current_size->size_value);
+ pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
/* address to map to */
- pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture base */
- pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr);
+ pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
/* agpctrl */
- pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000);
+ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
/* agpm */
- pci_read_config_byte(agp_bridge.dev, INTEL_I845_AGPM, &temp2);
- pci_write_config_byte(agp_bridge.dev, INTEL_I845_AGPM, temp2 | (1 << 1));
+ pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
+ pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
/* clear any possible error conditions */
- pci_write_config_word(agp_bridge.dev, INTEL_I845_ERRSTS, 0x001c);
+ pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
return 0;
}
u16 temp2;
struct aper_size_info_8 *current_size;
- current_size = A_SIZE_8(agp_bridge.current_size);
+ current_size = A_SIZE_8(agp_bridge->current_size);
/* aperture size */
- pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, current_size->size_value);
+ pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
/* address to map to */
- pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture base */
- pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr);
+ pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
/* agpctrl */
- pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000);
+ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
/* mcgcfg */
- pci_read_config_word(agp_bridge.dev, INTEL_I850_MCHCFG, &temp2);
- pci_write_config_word(agp_bridge.dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
+ pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
+ pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
/* clear any possible AGP-related error conditions */
- pci_write_config_word(agp_bridge.dev, INTEL_I850_ERRSTS, 0x001c);
+ pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
return 0;
}
u16 temp2;
struct aper_size_info_8 *current_size;
- current_size = A_SIZE_8(agp_bridge.current_size);
+ current_size = A_SIZE_8(agp_bridge->current_size);
/* aperture size */
- pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, current_size->size_value);
+ pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
/* address to map to */
- pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture base */
- pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr);
+ pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
/* agpctrl */
- pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000);
+ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
/* mcgcfg */
- pci_read_config_word(agp_bridge.dev, INTEL_I860_MCHCFG, &temp2);
- pci_write_config_word(agp_bridge.dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
+ pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
+ pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
/* clear any possible AGP-related error conditions */
- pci_write_config_word(agp_bridge.dev, INTEL_I860_ERRSTS, 0xf700);
+ pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
return 0;
}
u16 temp2;
struct aper_size_info_8 *current_size;
- current_size = A_SIZE_8(agp_bridge.current_size);
+ current_size = A_SIZE_8(agp_bridge->current_size);
/* aperture size */
- pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, current_size->size_value);
+ pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
/* address to map to */
- pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture base */
- pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr);
+ pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
/* agpctrl */
- pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000);
+ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
/* gmch */
- pci_read_config_word(agp_bridge.dev, INTEL_NBXCFG, &temp2);
- pci_write_config_word(agp_bridge.dev, INTEL_NBXCFG, temp2 | (1 << 9));
+ pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
+ pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
/* clear any possible AGP-related error conditions */
- pci_write_config_word(agp_bridge.dev, INTEL_I830_ERRSTS, 0x1c);
+ pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
return 0;
}
static unsigned long intel_mask_memory(unsigned long addr, int type)
{
/* Memory type is ignored */
- return addr | agp_bridge.masks[0].mask;
+ return addr | agp_bridge->masks[0].mask;
}
static void intel_resume(void)
static int __init intel_generic_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = intel_generic_masks;
- agp_bridge.aperture_sizes = (void *) intel_generic_sizes;
- agp_bridge.size_type = U16_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = intel_configure;
- agp_bridge.fetch_size = intel_fetch_size;
- agp_bridge.cleanup = intel_cleanup;
- agp_bridge.tlb_flush = intel_tlbflush;
- agp_bridge.mask_memory = intel_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = intel_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = intel_generic_masks;
+ agp_bridge->aperture_sizes = (void *) intel_generic_sizes;
+ agp_bridge->size_type = U16_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = intel_configure;
+ agp_bridge->fetch_size = intel_fetch_size;
+ agp_bridge->cleanup = intel_cleanup;
+ agp_bridge->tlb_flush = intel_tlbflush;
+ agp_bridge->mask_memory = intel_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = intel_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
static int __init intel_815_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = intel_generic_masks;
- agp_bridge.aperture_sizes = (void *) intel_815_sizes;
- agp_bridge.size_type = U8_APER_SIZE;
- agp_bridge.num_aperture_sizes = 2;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = intel_815_configure;
- agp_bridge.fetch_size = intel_8xx_fetch_size;
- agp_bridge.cleanup = intel_8xx_cleanup;
- agp_bridge.tlb_flush = intel_8xx_tlbflush;
- agp_bridge.mask_memory = intel_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = intel_generic_masks;
+ agp_bridge->aperture_sizes = (void *) intel_815_sizes;
+ agp_bridge->size_type = U8_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 2;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = intel_815_configure;
+ agp_bridge->fetch_size = intel_8xx_fetch_size;
+ agp_bridge->cleanup = intel_8xx_cleanup;
+ agp_bridge->tlb_flush = intel_8xx_tlbflush;
+ agp_bridge->mask_memory = intel_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
static int __init intel_820_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = intel_generic_masks;
- agp_bridge.aperture_sizes = (void *) intel_8xx_sizes;
- agp_bridge.size_type = U8_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = intel_820_configure;
- agp_bridge.fetch_size = intel_8xx_fetch_size;
- agp_bridge.cleanup = intel_820_cleanup;
- agp_bridge.tlb_flush = intel_820_tlbflush;
- agp_bridge.mask_memory = intel_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = intel_generic_masks;
+ agp_bridge->aperture_sizes = (void *) intel_8xx_sizes;
+ agp_bridge->size_type = U8_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = intel_820_configure;
+ agp_bridge->fetch_size = intel_8xx_fetch_size;
+ agp_bridge->cleanup = intel_820_cleanup;
+ agp_bridge->tlb_flush = intel_820_tlbflush;
+ agp_bridge->mask_memory = intel_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
static int __init intel_830mp_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = intel_generic_masks;
- agp_bridge.aperture_sizes = (void *) intel_830mp_sizes;
- agp_bridge.size_type = U8_APER_SIZE;
- agp_bridge.num_aperture_sizes = 4;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = intel_830mp_configure;
- agp_bridge.fetch_size = intel_8xx_fetch_size;
- agp_bridge.cleanup = intel_8xx_cleanup;
- agp_bridge.tlb_flush = intel_8xx_tlbflush;
- agp_bridge.mask_memory = intel_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = intel_generic_masks;
+ agp_bridge->aperture_sizes = (void *) intel_830mp_sizes;
+ agp_bridge->size_type = U8_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 4;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = intel_830mp_configure;
+ agp_bridge->fetch_size = intel_8xx_fetch_size;
+ agp_bridge->cleanup = intel_8xx_cleanup;
+ agp_bridge->tlb_flush = intel_8xx_tlbflush;
+ agp_bridge->mask_memory = intel_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
static int __init intel_840_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = intel_generic_masks;
- agp_bridge.aperture_sizes = (void *) intel_8xx_sizes;
- agp_bridge.size_type = U8_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = intel_840_configure;
- agp_bridge.fetch_size = intel_8xx_fetch_size;
- agp_bridge.cleanup = intel_8xx_cleanup;
- agp_bridge.tlb_flush = intel_8xx_tlbflush;
- agp_bridge.mask_memory = intel_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = intel_generic_masks;
+ agp_bridge->aperture_sizes = (void *) intel_8xx_sizes;
+ agp_bridge->size_type = U8_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = intel_840_configure;
+ agp_bridge->fetch_size = intel_8xx_fetch_size;
+ agp_bridge->cleanup = intel_8xx_cleanup;
+ agp_bridge->tlb_flush = intel_8xx_tlbflush;
+ agp_bridge->mask_memory = intel_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
static int __init intel_845_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = intel_generic_masks;
- agp_bridge.aperture_sizes = (void *) intel_8xx_sizes;
- agp_bridge.size_type = U8_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = intel_845_configure;
- agp_bridge.fetch_size = intel_8xx_fetch_size;
- agp_bridge.cleanup = intel_8xx_cleanup;
- agp_bridge.tlb_flush = intel_8xx_tlbflush;
- agp_bridge.mask_memory = intel_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = intel_845_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = intel_generic_masks;
+ agp_bridge->aperture_sizes = (void *) intel_8xx_sizes;
+ agp_bridge->size_type = U8_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = intel_845_configure;
+ agp_bridge->fetch_size = intel_8xx_fetch_size;
+ agp_bridge->cleanup = intel_8xx_cleanup;
+ agp_bridge->tlb_flush = intel_8xx_tlbflush;
+ agp_bridge->mask_memory = intel_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = intel_845_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
static int __init intel_850_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = intel_generic_masks;
- agp_bridge.aperture_sizes = (void *) intel_8xx_sizes;
- agp_bridge.size_type = U8_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = intel_850_configure;
- agp_bridge.fetch_size = intel_8xx_fetch_size;
- agp_bridge.cleanup = intel_8xx_cleanup;
- agp_bridge.tlb_flush = intel_8xx_tlbflush;
- agp_bridge.mask_memory = intel_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = intel_generic_masks;
+ agp_bridge->aperture_sizes = (void *) intel_8xx_sizes;
+ agp_bridge->size_type = U8_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = intel_850_configure;
+ agp_bridge->fetch_size = intel_8xx_fetch_size;
+ agp_bridge->cleanup = intel_8xx_cleanup;
+ agp_bridge->tlb_flush = intel_8xx_tlbflush;
+ agp_bridge->mask_memory = intel_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
static int __init intel_860_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = intel_generic_masks;
- agp_bridge.aperture_sizes = (void *) intel_8xx_sizes;
- agp_bridge.size_type = U8_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = intel_860_configure;
- agp_bridge.fetch_size = intel_8xx_fetch_size;
- agp_bridge.cleanup = intel_8xx_cleanup;
- agp_bridge.tlb_flush = intel_8xx_tlbflush;
- agp_bridge.mask_memory = intel_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = intel_generic_masks;
+ agp_bridge->aperture_sizes = (void *) intel_8xx_sizes;
+ agp_bridge->size_type = U8_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = intel_860_configure;
+ agp_bridge->fetch_size = intel_8xx_fetch_size;
+ agp_bridge->cleanup = intel_8xx_cleanup;
+ agp_bridge->tlb_flush = intel_8xx_tlbflush;
+ agp_bridge->mask_memory = intel_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
if (pdev->device == devs[j].device_id) {
printk (KERN_INFO PFX "Detected Intel %s chipset\n",
devs[j].chipset_name);
- agp_bridge.type = devs[j].chipset;
+ agp_bridge->type = devs[j].chipset;
if (devs[j].chipset_setup != NULL)
return devs[j].chipset_setup(pdev);
if (agp_try_unsupported) {
printk(KERN_WARNING PFX "Trying generic Intel routines"
" for device id: %04x\n", pdev->device);
- agp_bridge.type = INTEL_GENERIC;
+ agp_bridge->type = INTEL_GENERIC;
return intel_generic_setup(pdev);
}
struct pci_dev *i810_dev;
u8 cap_ptr = 0;
- agp_bridge.dev = dev;
+ agp_bridge->dev = dev;
/* This shit needs moving into tables/init-routines. */
switch (dev->device) {
return -ENODEV;
}
printk(KERN_INFO PFX "Detected an Intel i810 Chipset.\n");
- agp_bridge.type = INTEL_I810;
+ agp_bridge->type = INTEL_I810;
return intel_i810_setup (i810_dev);
case PCI_DEVICE_ID_INTEL_82810_MC3:
return -ENODEV;
}
printk(KERN_INFO PFX "Detected an Intel i810 DC100 Chipset.\n");
- agp_bridge.type = INTEL_I810;
+ agp_bridge->type = INTEL_I810;
return intel_i810_setup(i810_dev);
case PCI_DEVICE_ID_INTEL_82810E_MC:
return -ENODEV;
}
printk(KERN_INFO PFX "Detected an Intel i810 E Chipset.\n");
- agp_bridge.type = INTEL_I810;
+ agp_bridge->type = INTEL_I810;
return intel_i810_setup(i810_dev);
case PCI_DEVICE_ID_INTEL_82815_MC:
break;
}
printk(KERN_INFO PFX "agpgart: Detected an Intel i815 Chipset.\n");
- agp_bridge.type = INTEL_I810;
+ agp_bridge->type = INTEL_I810;
return intel_i810_setup(i810_dev);
case PCI_DEVICE_ID_INTEL_82845G_HB:
* We probably have a I845MP chipset with an external graphics
* card. It will be initialized later
*/
- agp_bridge.type = INTEL_I845_G;
+ agp_bridge->type = INTEL_I845_G;
break;
}
printk(KERN_INFO PFX "Detected an Intel 845G Chipset.\n");
- agp_bridge.type = INTEL_I810;
+ agp_bridge->type = INTEL_I810;
return intel_i830_setup(i810_dev);
case PCI_DEVICE_ID_INTEL_82830_HB:
if (i810_dev == NULL) {
/* Intel 830MP with external graphic card */
/* It will be initialized later */
- agp_bridge.type = INTEL_I830_M;
+ agp_bridge->type = INTEL_I830_M;
break;
}
printk(KERN_INFO PFX "Detected an Intel 830M Chipset.\n");
- agp_bridge.type = INTEL_I810;
+ agp_bridge->type = INTEL_I810;
return intel_i830_setup(i810_dev);
default:
cap_ptr = pci_find_capability(dev, PCI_CAP_ID_AGP);
if (cap_ptr == 0)
return -ENODEV;
- agp_bridge.capndx = cap_ptr;
+ agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
- pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
+ pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
/* probe for known chipsets */
return agp_lookup_host_bridge(dev);
ret_val = pci_module_init(&agp_intel_pci_driver);
if (ret_val)
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
int i;
struct aper_size_info_8 *values;
- pci_read_config_byte(agp_bridge.dev, SIS_APSIZE, &temp_size);
- values = A_SIZE_8(agp_bridge.aperture_sizes);
- for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+ pci_read_config_byte(agp_bridge->dev, SIS_APSIZE, &temp_size);
+ values = A_SIZE_8(agp_bridge->aperture_sizes);
+ for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if ((temp_size == values[i].size_value) ||
((temp_size & ~(0x03)) ==
(values[i].size_value & ~(0x03)))) {
- agp_bridge.previous_size =
- agp_bridge.current_size = (void *) (values + i);
+ agp_bridge->previous_size =
+ agp_bridge->current_size = (void *) (values + i);
- agp_bridge.aperture_size_idx = i;
+ agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
static void sis_tlbflush(agp_memory * mem)
{
- pci_write_config_byte(agp_bridge.dev, SIS_TLBFLUSH, 0x02);
+ pci_write_config_byte(agp_bridge->dev, SIS_TLBFLUSH, 0x02);
}
static int sis_configure(void)
u32 temp;
struct aper_size_info_8 *current_size;
- current_size = A_SIZE_8(agp_bridge.current_size);
- pci_write_config_byte(agp_bridge.dev, SIS_TLBCNTRL, 0x05);
- pci_read_config_dword(agp_bridge.dev, SIS_APBASE, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
- pci_write_config_dword(agp_bridge.dev, SIS_ATTBASE,
- agp_bridge.gatt_bus_addr);
- pci_write_config_byte(agp_bridge.dev, SIS_APSIZE,
+ current_size = A_SIZE_8(agp_bridge->current_size);
+ pci_write_config_byte(agp_bridge->dev, SIS_TLBCNTRL, 0x05);
+ pci_read_config_dword(agp_bridge->dev, SIS_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_write_config_dword(agp_bridge->dev, SIS_ATTBASE,
+ agp_bridge->gatt_bus_addr);
+ pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,
current_size->size_value);
return 0;
}
{
struct aper_size_info_8 *previous_size;
- previous_size = A_SIZE_8(agp_bridge.previous_size);
- pci_write_config_byte(agp_bridge.dev, SIS_APSIZE,
+ previous_size = A_SIZE_8(agp_bridge->previous_size);
+ pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,
(previous_size->size_value & ~(0x03)));
}
{
/* Memory type is ignored */
- return addr | agp_bridge.masks[0].mask;
+ return addr | agp_bridge->masks[0].mask;
}
static struct aper_size_info_8 sis_generic_sizes[7] =
static int __init sis_generic_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = sis_generic_masks;
- agp_bridge.aperture_sizes = (void *) sis_generic_sizes;
- agp_bridge.size_type = U8_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = sis_configure;
- agp_bridge.fetch_size = sis_fetch_size;
- agp_bridge.cleanup = sis_cleanup;
- agp_bridge.tlb_flush = sis_tlbflush;
- agp_bridge.mask_memory = sis_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = sis_generic_masks;
+ agp_bridge->aperture_sizes = (void *) sis_generic_sizes;
+ agp_bridge->size_type = U8_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = sis_configure;
+ agp_bridge->fetch_size = sis_fetch_size;
+ agp_bridge->cleanup = sis_cleanup;
+ agp_bridge->tlb_flush = sis_tlbflush;
+ agp_bridge->mask_memory = sis_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
if (pdev->device == devs[j].device_id) {
printk (KERN_INFO PFX "Detected SiS %s chipset\n",
devs[j].chipset_name);
- agp_bridge.type = devs[j].chipset;
+ agp_bridge->type = devs[j].chipset;
if (devs[j].chipset_setup != NULL)
return devs[j].chipset_setup(pdev);
if (agp_try_unsupported) {
printk(KERN_WARNING PFX "Trying generic SiS routines"
" for device id: %04x\n", pdev->device);
- agp_bridge.type = SIS_GENERIC;
+ agp_bridge->type = SIS_GENERIC;
return sis_generic_setup(pdev);
}
/* probe for known chipsets */
if (agp_lookup_host_bridge(dev) != -ENODEV) {
- agp_bridge.dev = dev;
- agp_bridge.capndx = cap_ptr;
+ agp_bridge->dev = dev;
+ agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
- pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
+ pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
sis_agp_driver.dev = dev;
agp_register_driver(&sis_agp_driver);
return 0;
ret_val = pci_module_init(&agp_sis_pci_driver);
if (ret_val)
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
CACHE_FLUSH();
for(i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
- page_map->remapped[i] = agp_bridge.scratch_page;
+ page_map->remapped[i] = agp_bridge->scratch_page;
}
return 0;
#ifndef GET_PAGE_DIR_IDX
#define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
- GET_PAGE_DIR_OFF(agp_bridge.gart_bus_addr))
+ GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
#endif
#ifndef GET_GATT_OFF
u32 temp;
int i;
- value = A_SIZE_LVL2(agp_bridge.current_size);
+ value = A_SIZE_LVL2(agp_bridge->current_size);
retval = serverworks_create_page_map(&page_dir);
if (retval != 0) {
return retval;
}
/* Create a fake scratch directory */
for(i = 0; i < 1024; i++) {
- serverworks_private.scratch_dir.remapped[i] = (unsigned long) agp_bridge.scratch_page;
+ serverworks_private.scratch_dir.remapped[i] = (unsigned long) agp_bridge->scratch_page;
page_dir.remapped[i] =
virt_to_phys(serverworks_private.scratch_dir.real);
page_dir.remapped[i] |= 0x00000001;
return retval;
}
- agp_bridge.gatt_table_real = (u32 *)page_dir.real;
- agp_bridge.gatt_table = (u32 *)page_dir.remapped;
- agp_bridge.gatt_bus_addr = virt_to_phys(page_dir.real);
+ agp_bridge->gatt_table_real = (u32 *)page_dir.real;
+ agp_bridge->gatt_table = (u32 *)page_dir.remapped;
+ agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);
/* Get the address for the gart region.
* This is a bus address even on the alpha, b/c its
* used to program the agp master not the cpu
*/
- pci_read_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs,&temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* Calculate the agp offset */
{
struct serverworks_page_map page_dir;
- page_dir.real = (unsigned long *)agp_bridge.gatt_table_real;
- page_dir.remapped = (unsigned long *)agp_bridge.gatt_table;
+ page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
+ page_dir.remapped = (unsigned long *)agp_bridge->gatt_table;
serverworks_free_gatt_pages();
serverworks_free_page_map(&page_dir);
u32 temp2;
struct aper_size_info_lvl2 *values;
- values = A_SIZE_LVL2(agp_bridge.aperture_sizes);
- pci_read_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs,&temp);
- pci_write_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs,
+ values = A_SIZE_LVL2(agp_bridge->aperture_sizes);
+ pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
+ pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,
SVWRKS_SIZE_MASK);
- pci_read_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs,&temp2);
- pci_write_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs,temp);
+ pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp2);
+ pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,temp);
temp2 &= SVWRKS_SIZE_MASK;
- for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+ for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if (temp2 == values[i].size_value) {
- agp_bridge.previous_size =
- agp_bridge.current_size = (void *) (values + i);
+ agp_bridge->previous_size =
+ agp_bridge->current_size = (void *) (values + i);
- agp_bridge.aperture_size_idx = i;
+ agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
u8 enable_reg;
u16 cap_reg;
- current_size = A_SIZE_LVL2(agp_bridge.current_size);
+ current_size = A_SIZE_LVL2(agp_bridge->current_size);
/* Get the memory mapped registers */
- pci_read_config_dword(agp_bridge.dev, serverworks_private.mm_addr_ofs, &temp);
+ pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs, &temp);
temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
serverworks_private.registers = (volatile u8 *) ioremap(temp, 4096);
OUTREG8(serverworks_private.registers, SVWRKS_GART_CACHE, 0x0a);
OUTREG32(serverworks_private.registers, SVWRKS_GATTBASE,
- agp_bridge.gatt_bus_addr);
+ agp_bridge->gatt_bus_addr);
cap_reg = INREG16(serverworks_private.registers, SVWRKS_COMMAND);
cap_reg &= ~0x0007;
enable_reg |= 0x1; /* Agp Enable bit */
pci_write_config_byte(serverworks_private.svrwrks_dev,
SVWRKS_AGP_ENABLE, enable_reg);
- agp_bridge.tlb_flush(NULL);
+ agp_bridge->tlb_flush(NULL);
- agp_bridge.capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP);
+ agp_bridge->capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP);
/* Fill in the mode register */
pci_read_config_dword(serverworks_private.svrwrks_dev,
- agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
+ agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
- pci_read_config_byte(agp_bridge.dev, SVWRKS_CACHING, &enable_reg);
+ pci_read_config_byte(agp_bridge->dev, SVWRKS_CACHING, &enable_reg);
enable_reg &= ~0x3;
- pci_write_config_byte(agp_bridge.dev, SVWRKS_CACHING, enable_reg);
+ pci_write_config_byte(agp_bridge->dev, SVWRKS_CACHING, enable_reg);
- pci_read_config_byte(agp_bridge.dev, SVWRKS_FEATURE, &enable_reg);
+ pci_read_config_byte(agp_bridge->dev, SVWRKS_FEATURE, &enable_reg);
enable_reg |= (1<<6);
- pci_write_config_byte(agp_bridge.dev,SVWRKS_FEATURE, enable_reg);
+ pci_write_config_byte(agp_bridge->dev,SVWRKS_FEATURE, enable_reg);
return 0;
}
{
/* Only type 0 is supported by the serverworks chipsets */
- return addr | agp_bridge.masks[0].mask;
+ return addr | agp_bridge->masks[0].mask;
}
static int serverworks_insert_memory(agp_memory * mem,
unsigned long *cur_gatt;
unsigned long addr;
- num_entries = A_SIZE_LVL2(agp_bridge.current_size)->num_entries;
+ num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
if (type != 0 || mem->type != 0) {
return -EINVAL;
j = pg_start;
while (j < (pg_start + mem->page_count)) {
- addr = (j * PAGE_SIZE) + agp_bridge.gart_bus_addr;
+ addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = SVRWRKS_GET_GATT(addr);
if (!PGE_EMPTY(cur_gatt[GET_GATT_OFF(addr)])) {
return -EBUSY;
}
for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
- addr = (j * PAGE_SIZE) + agp_bridge.gart_bus_addr;
+ addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = SVRWRKS_GET_GATT(addr);
cur_gatt[GET_GATT_OFF(addr)] =
- agp_bridge.mask_memory(mem->memory[i], mem->type);
+ agp_bridge->mask_memory(mem->memory[i], mem->type);
}
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return 0;
}
}
CACHE_FLUSH();
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
for (i = pg_start; i < (mem->page_count + pg_start); i++) {
- addr = (i * PAGE_SIZE) + agp_bridge.gart_bus_addr;
+ addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = SVRWRKS_GET_GATT(addr);
cur_gatt[GET_GATT_OFF(addr)] =
- (unsigned long) agp_bridge.scratch_page;
+ (unsigned long) agp_bridge->scratch_page;
}
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return 0;
}
u32 command;
pci_read_config_dword(serverworks_private.svrwrks_dev,
- agp_bridge.capndx + PCI_AGP_STATUS,
+ agp_bridge->capndx + PCI_AGP_STATUS,
&command);
command = agp_collect_device_status(mode, command);
command |= 0x100;
pci_write_config_dword(serverworks_private.svrwrks_dev,
- agp_bridge.capndx + PCI_AGP_COMMAND,
+ agp_bridge->capndx + PCI_AGP_COMMAND,
command);
agp_device_command(command, 0);
serverworks_private.svrwrks_dev = pdev;
- agp_bridge.masks = serverworks_masks;
- agp_bridge.aperture_sizes = (void *) serverworks_sizes;
- agp_bridge.size_type = LVL2_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = (void *) &serverworks_private;
- agp_bridge.needs_scratch_page = TRUE;
- agp_bridge.configure = serverworks_configure;
- agp_bridge.fetch_size = serverworks_fetch_size;
- agp_bridge.cleanup = serverworks_cleanup;
- agp_bridge.tlb_flush = serverworks_tlbflush;
- agp_bridge.mask_memory = serverworks_mask_memory;
- agp_bridge.agp_enable = serverworks_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = serverworks_create_gatt_table;
- agp_bridge.free_gatt_table = serverworks_free_gatt_table;
- agp_bridge.insert_memory = serverworks_insert_memory;
- agp_bridge.remove_memory = serverworks_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
-
- pci_read_config_dword(agp_bridge.dev,
+ agp_bridge->masks = serverworks_masks;
+ agp_bridge->aperture_sizes = (void *) serverworks_sizes;
+ agp_bridge->size_type = LVL2_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = (void *) &serverworks_private;
+ agp_bridge->needs_scratch_page = TRUE;
+ agp_bridge->configure = serverworks_configure;
+ agp_bridge->fetch_size = serverworks_fetch_size;
+ agp_bridge->cleanup = serverworks_cleanup;
+ agp_bridge->tlb_flush = serverworks_tlbflush;
+ agp_bridge->mask_memory = serverworks_mask_memory;
+ agp_bridge->agp_enable = serverworks_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = serverworks_create_gatt_table;
+ agp_bridge->free_gatt_table = serverworks_free_gatt_table;
+ agp_bridge->insert_memory = serverworks_insert_memory;
+ agp_bridge->remove_memory = serverworks_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
+
+ pci_read_config_dword(agp_bridge->dev,
SVWRKS_APSIZE,
&temp);
serverworks_private.gart_addr_ofs = 0x10;
if(temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
- pci_read_config_dword(agp_bridge.dev,
+ pci_read_config_dword(agp_bridge->dev,
SVWRKS_APSIZE + 4,
&temp2);
if(temp2 != 0) {
serverworks_private.mm_addr_ofs = 0x14;
}
- pci_read_config_dword(agp_bridge.dev,
+ pci_read_config_dword(agp_bridge->dev,
serverworks_private.mm_addr_ofs,
&temp);
if(temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
- pci_read_config_dword(agp_bridge.dev,
+ pci_read_config_dword(agp_bridge->dev,
serverworks_private.mm_addr_ofs + 4,
&temp2);
if(temp2 != 0) {
return -ENODEV;
}
- agp_bridge.dev = dev;
+ agp_bridge->dev = dev;
switch (dev->device) {
case PCI_DEVICE_ID_SERVERWORKS_HE:
- agp_bridge.type = SVWRKS_HE;
+ agp_bridge->type = SVWRKS_HE;
return serverworks_setup(bridge_dev);
case PCI_DEVICE_ID_SERVERWORKS_LE:
case 0x0007:
- agp_bridge.type = SVWRKS_LE;
+ agp_bridge->type = SVWRKS_LE;
return serverworks_setup(bridge_dev);
default:
if(agp_try_unsupported) {
- agp_bridge.type = SVWRKS_GENERIC;
+ agp_bridge->type = SVWRKS_GENERIC;
return serverworks_setup(bridge_dev);
}
break;
ret_val = pci_module_init(&agp_serverworks_pci_driver);
if (ret_val)
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
u8 temp;
struct aper_size_info_8 *values;
- values = A_SIZE_8(agp_bridge.aperture_sizes);
- pci_read_config_byte(agp_bridge.dev, VIA_APSIZE, &temp);
- for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+ values = A_SIZE_8(agp_bridge->aperture_sizes);
+ pci_read_config_byte(agp_bridge->dev, VIA_APSIZE, &temp);
+ for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if (temp == values[i].size_value) {
- agp_bridge.previous_size =
- agp_bridge.current_size = (void *) (values + i);
- agp_bridge.aperture_size_idx = i;
+ agp_bridge->previous_size =
+ agp_bridge->current_size = (void *) (values + i);
+ agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
u32 temp;
struct aper_size_info_8 *current_size;
- current_size = A_SIZE_8(agp_bridge.current_size);
+ current_size = A_SIZE_8(agp_bridge->current_size);
/* aperture size */
- pci_write_config_byte(agp_bridge.dev, VIA_APSIZE,
+ pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
current_size->size_value);
/* address to map too */
- pci_read_config_dword(agp_bridge.dev, VIA_APBASE, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev, VIA_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* GART control register */
- pci_write_config_dword(agp_bridge.dev, VIA_GARTCTRL, 0x0000000f);
+ pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f);
/* attbase - aperture GATT base */
- pci_write_config_dword(agp_bridge.dev, VIA_ATTBASE,
- (agp_bridge.gatt_bus_addr & 0xfffff000) | 3);
+ pci_write_config_dword(agp_bridge->dev, VIA_ATTBASE,
+ (agp_bridge->gatt_bus_addr & 0xfffff000) | 3);
return 0;
}
{
struct aper_size_info_8 *previous_size;
- previous_size = A_SIZE_8(agp_bridge.previous_size);
- pci_write_config_byte(agp_bridge.dev, VIA_APSIZE,
+ previous_size = A_SIZE_8(agp_bridge->previous_size);
+ pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
previous_size->size_value);
/* Do not disable by writing 0 to VIA_ATTBASE, it screws things up
* during reinitialization.
static void via_tlbflush(agp_memory * mem)
{
- pci_write_config_dword(agp_bridge.dev, VIA_GARTCTRL, 0x0000008f);
- pci_write_config_dword(agp_bridge.dev, VIA_GARTCTRL, 0x0000000f);
+ pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000008f);
+ pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f);
}
static unsigned long via_mask_memory(unsigned long addr, int type)
{
/* Memory type is ignored */
- return addr | agp_bridge.masks[0].mask;
+ return addr | agp_bridge->masks[0].mask;
}
static struct aper_size_info_8 via_generic_sizes[7] =
}
}
- agp_bridge.masks = via_generic_masks;
- agp_bridge.aperture_sizes = (void *) via_generic_sizes;
- agp_bridge.size_type = U8_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = via_configure;
- agp_bridge.fetch_size = via_fetch_size;
- agp_bridge.cleanup = via_cleanup;
- agp_bridge.tlb_flush = via_tlbflush;
- agp_bridge.mask_memory = via_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = via_generic_masks;
+ agp_bridge->aperture_sizes = (void *) via_generic_sizes;
+ agp_bridge->size_type = U8_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = via_configure;
+ agp_bridge->fetch_size = via_fetch_size;
+ agp_bridge->cleanup = via_cleanup;
+ agp_bridge->tlb_flush = via_tlbflush;
+ agp_bridge->mask_memory = via_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
while (devs[j].chipset_name != NULL) {
if (pdev->device == devs[j].device_id) {
printk (KERN_INFO PFX "Detected VIA %s chipset\n", devs[j].chipset_name);
- agp_bridge.type = devs[j].chipset;
+ agp_bridge->type = devs[j].chipset;
if (devs[j].chipset_setup != NULL)
return devs[j].chipset_setup(pdev);
if (agp_try_unsupported) {
printk(KERN_WARNING PFX "Trying generic VIA routines"
" for device id: %04x\n", pdev->device);
- agp_bridge.type = VIA_GENERIC;
+ agp_bridge->type = VIA_GENERIC;
return via_generic_setup(pdev);
}
/* probe for known chipsets */
if (agp_lookup_host_bridge (dev) != -ENODEV) {
- agp_bridge.dev = dev;
- agp_bridge.capndx = cap_ptr;
+ agp_bridge->dev = dev;
+ agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
- pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
+ pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
via_agp_driver.dev = dev;
agp_register_driver(&via_agp_driver);
return 0;
ret_val = pci_module_init(&agp_via_pci_driver);
if (ret_val)
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
u16 temp;
struct aper_size_info_16 *values;
- values = A_SIZE_16(agp_bridge.aperture_sizes);
- pci_read_config_word(agp_bridge.dev, VIA_AGP3_APSIZE, &temp);
+ values = A_SIZE_16(agp_bridge->aperture_sizes);
+ pci_read_config_word(agp_bridge->dev, VIA_AGP3_APSIZE, &temp);
temp &= 0xfff;
- for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+ for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if (temp == values[i].size_value) {
- agp_bridge.previous_size =
- agp_bridge.current_size = (void *) (values + i);
- agp_bridge.aperture_size_idx = i;
+ agp_bridge->previous_size =
+ agp_bridge->current_size = (void *) (values + i);
+ agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
u32 temp;
struct aper_size_info_16 *current_size;
- current_size = A_SIZE_16(agp_bridge.current_size);
+ current_size = A_SIZE_16(agp_bridge->current_size);
/* address to map too */
- pci_read_config_dword(agp_bridge.dev, VIA_APBASE, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev, VIA_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture GATT base */
- pci_write_config_dword(agp_bridge.dev, VIA_AGP3_ATTBASE,
- agp_bridge.gatt_bus_addr & 0xfffff000);
+ pci_write_config_dword(agp_bridge->dev, VIA_AGP3_ATTBASE,
+ agp_bridge->gatt_bus_addr & 0xfffff000);
return 0;
}
{
struct aper_size_info_16 *previous_size;
- previous_size = A_SIZE_16(agp_bridge.previous_size);
- pci_write_config_byte(agp_bridge.dev, VIA_APSIZE, previous_size->size_value);
+ previous_size = A_SIZE_16(agp_bridge->previous_size);
+ pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, previous_size->size_value);
}
static void via_tlbflush(agp_memory * mem)
{
u32 temp;
- pci_read_config_dword(agp_bridge.dev, VIA_AGP3_GARTCTRL, &temp);
- pci_write_config_dword(agp_bridge.dev, VIA_AGP3_GARTCTRL, temp & ~(1<<7));
- pci_write_config_dword(agp_bridge.dev, VIA_AGP3_GARTCTRL, temp);
+ pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp);
+ pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp & ~(1<<7));
+ pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp);
}
static unsigned long via_mask_memory(unsigned long addr, int type)
{
/* Memory type is ignored */
- return addr | agp_bridge.masks[0].mask;
+ return addr | agp_bridge->masks[0].mask;
}
static struct aper_size_info_16 via_generic_sizes[11] =
printk (KERN_INFO PFX "Detected VIA KT400 AGP3 chipset\n");
- agp_bridge.dev = dev;
- agp_bridge.type = VIA_APOLLO_KT400_3;
- agp_bridge.capndx = cap_ptr;
- agp_bridge.masks = via_generic_masks;
- agp_bridge.aperture_sizes = (void *) via_generic_sizes;
- agp_bridge.size_type = U8_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.agp_enable = via_kt400_enable;
- agp_bridge.configure = via_configure;
- agp_bridge.fetch_size = via_fetch_size;
- agp_bridge.cleanup = via_cleanup;
- agp_bridge.tlb_flush = via_tlbflush;
- agp_bridge.mask_memory = via_mask_memory;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->dev = dev;
+ agp_bridge->type = VIA_APOLLO_KT400_3;
+ agp_bridge->capndx = cap_ptr;
+ agp_bridge->masks = via_generic_masks;
+ agp_bridge->aperture_sizes = (void *) via_generic_sizes;
+ agp_bridge->size_type = U8_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->agp_enable = via_kt400_enable;
+ agp_bridge->configure = via_configure;
+ agp_bridge->fetch_size = via_fetch_size;
+ agp_bridge->cleanup = via_cleanup;
+ agp_bridge->tlb_flush = via_tlbflush;
+ agp_bridge->mask_memory = via_mask_memory;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
/* Fill in the mode register */
- pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
+ pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
via_kt400_agp_driver.dev = dev;
agp_register_driver(&via_kt400_agp_driver);
ret_val = pci_module_init(&agp_via_pci_driver);
if (ret_val)
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
projects / linux / commitdiff