[PATCH] update PCI quirks

ALi Magik requires workarounds for TV chips
IDE controllers require proper handling in legacy mode
PXB must be disabled on C0 450NX or the IDE will corrupt memory
VIA northbridge devices require the interrupt line is written
NEC_CBUS_2/3 require ISA DMA workarounds

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 2c47ab894c5781f31e728faebd2d26495f4a6996..a34fd7e03181d9d73f186f188a8b16ba886d1090 100644 (file)
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -167,6 +167,22 @@ static void __devinit quirk_vsfx(struct pci_dev *dev)
        }
 }
 
+/*
+ *     Ali Magik requires workarounds to be used by the drivers
+ *     that DMA to AGP space. Latency must be set to 0xA and triton
+ *     workaround applied too
+ *     [Info kindly provided by ALi]
+ */    
+ 
+static void __init quirk_alimagik(struct pci_dev *dev)
+{
+       if((pci_pci_problems&PCIPCI_ALIMAGIK)==0)
+       {
+               printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
+               pci_pci_problems|=PCIPCI_ALIMAGIK|PCIPCI_TRITON;
+       }
+}
+
 
 /*
  *     Natoma has some interesting boundary conditions with Zoran stuff
@@ -219,7 +235,7 @@ static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, unsi
 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
 {
        printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
-       /* Mae rhaid in i beidio a edrych ar y lleoliad I/O hyn */
+       /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
        request_region(0x3b0, 0x0C, "RadeonIGP");
        request_region(0x3d3, 0x01, "RadeonIGP");
 }
@@ -535,6 +551,92 @@ static void __init quirk_mediagx_master(struct pci_dev *dev)
        }
 }
 
+/*
+ * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
+ * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
+ * secondary channels respectively). If the device reports Compatible mode
+ * but does use BAR0-3 for address decoding, we assume that firmware has
+ * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
+ * Exceptions (if they exist) must be handled in chip/architecture specific
+ * fixups.
+ *
+ * Note: for non x86 people. You may need an arch specific quirk to handle
+ * moving IDE devices to native mode as well. Some plug in card devices power
+ * up in compatible mode and assume the BIOS will adjust them.
+ *
+ * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
+ * we do now ? We don't want is pci_enable_device to come along
+ * and assign new resources. Both approaches work for that.
+ */ 
+
+static void __devinit quirk_ide_bases(struct pci_dev *dev)
+{
+       struct resource *res;
+       int first_bar = 2, last_bar = 0;
+
+       if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
+               return;
+
+       res = &dev->resource[0];
+
+       /* primary channel: ProgIf bit 0, BAR0, BAR1 */
+       if (!(dev->class & 1) && (res[0].flags || res[1].flags)) { 
+               res[0].start = res[0].end = res[0].flags = 0;
+               res[1].start = res[1].end = res[1].flags = 0;
+               first_bar = 0;
+               last_bar = 1;
+       }
+
+       /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
+       if (!(dev->class & 4) && (res[2].flags || res[3].flags)) { 
+               res[2].start = res[2].end = res[2].flags = 0;
+               res[3].start = res[3].end = res[3].flags = 0;
+               last_bar = 3;
+       }
+
+       if (!last_bar)
+               return;
+
+       printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
+              first_bar, last_bar, dev->slot_name);
+}
+
+/*
+ *     Ensure C0 rev restreaming is off. This is normally done by
+ *     the BIOS but in the odd case it is not the results are corruption
+ *     hence the presence of a Linux check
+ */
+ 
+static void __init quirk_disable_pxb(struct pci_dev *pdev)
+{
+       u16 config;
+       u8 rev;
+       
+       pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
+       if(rev != 0x04)         /* Only C0 requires this */
+               return;
+       pci_read_config_word(pdev, 0x40, &config);
+       if(config & (1<<6))
+       {
+               config &= ~(1<<6);
+               pci_write_config_word(pdev, 0x40, config);
+               printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
+       }
+}
+
+/*
+ *     VIA northbridges care about PCI_INTERRUPT_LINE
+ */
+ 
+int interrupt_line_quirk;
+
+static void __init quirk_via_bridge(struct pci_dev *pdev)
+{
+       if(pdev->devfn == 0)
+               interrupt_line_quirk = 1;
+}
+       
+
 /* This was originally an Alpha specific thing, but it really fits here.
  * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
  */
@@ -559,7 +661,10 @@ static struct pci_fixup pci_fixups[] __devinitdata = {
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C586_0,     quirk_isa_dma_hangs },
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C596,       quirk_isa_dma_hangs },
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82371SB_0,  quirk_isa_dma_hangs },
+       { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82454NX,    quirk_disable_pxb },
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_NEC,      PCI_DEVICE_ID_NEC_CBUS_1,       quirk_isa_dma_hangs },
+       { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_NEC,      PCI_DEVICE_ID_NEC_CBUS_2,       quirk_isa_dma_hangs },
+       { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_NEC,      PCI_DEVICE_ID_NEC_CBUS_3,       quirk_isa_dma_hangs },
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_S3,       PCI_DEVICE_ID_S3_868,           quirk_s3_64M },
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_S3,       PCI_DEVICE_ID_S3_968,           quirk_s3_64M },
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82437,      quirk_triton }, 
@@ -574,6 +679,8 @@ static struct pci_fixup pci_fixups[] __devinitdata = {
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443BX_2,  quirk_natoma },
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_5597,          quirk_nopcipci },
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_496,           quirk_nopcipci },
+       { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_AL,       PCI_DEVICE_ID_AL_M1647,         quirk_alimagik },
+       { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_AL,       PCI_DEVICE_ID_AL_M1651,         quirk_alimagik },
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8363_0,       quirk_vialatency },
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8371_1,       quirk_vialatency },
        { PCI_FIXUP_FINAL,      PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8361, quirk_vialatency },
@@ -586,6 +693,8 @@ static struct pci_fixup pci_fixups[] __devinitdata = {
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_AL,       PCI_DEVICE_ID_AL_M7101,         quirk_ali7101_acpi },
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82371SB_2,  quirk_piix3_usb },
        { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82371AB_2,  quirk_piix3_usb },
+       { PCI_FIXUP_HEADER,     PCI_ANY_ID,             PCI_ANY_ID,                     quirk_ide_bases },
+       { PCI_FIXUP_HEADER,     PCI_VENDOR_ID_VIA,      PCI_ANY_ID,                     quirk_via_bridge },
        { PCI_FIXUP_FINAL,      PCI_ANY_ID,             PCI_ANY_ID,                     quirk_cardbus_legacy },
 
 #ifdef CONFIG_X86_IO_APIC