[ARM PATCH] 1513/1: iq80310 fix missing header

Patch from Eli Carter

# Tue Apr 22 10:26:15 CDT 2003 ejc@rnd-linux-c84
# e42-fix-missing-iop-header
#
# Add in the missing iop310-irq.h header file.
#
# Diffed against linux-2.5.59-rmk1-ec0
# Applies cleanly to 2.5.67-rmk1, 2.5.68-rmk1
#
#  include/asm-arm/arch-iop3xx/iop310-irqs.h |   80 ++++++++++++++++++++++++++++++
#  1 files changed, 80 insertions(+)
#

diff --git a/include/asm-arm/arch-iop3xx/iop310-irqs.h b/include/asm-arm/arch-iop3xx/iop310-irqs.h
new file mode 100644 (file)
index 0000000..f468a28
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/iop310-irqs.h
@@ -0,0 +1,80 @@
+/*
+ * linux/include/asm-arm/arch-iop310/irqs.h
+ *
+ * Author:     Nicolas Pitre
+ * Copyright:  (C) 2001 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * 06/13/01: Added 80310 on-chip interrupt sources <dsaxena@mvista.com>
+ *
+ */
+#include <linux/config.h>
+
+/*
+ * XS80200 specific IRQs
+ */
+#define IRQ_XS80200_BCU                0       /* Bus Control Unit */
+#define IRQ_XS80200_PMU                1       /* Performance Monitoring Unit */
+#define IRQ_XS80200_EXTIRQ     2       /* external IRQ signal */
+#define IRQ_XS80200_EXTFIQ     3       /* external IRQ signal */
+
+#define NR_XS80200_IRQS                4
+
+#define XSCALE_PMU_IRQ         IRQ_XS80200_PMU
+
+/*
+ * IOP80310 chipset interrupts
+ */
+#define IOP310_IRQ_OFS         NR_XS80200_IRQS
+#define IOP310_IRQ(x)          (IOP310_IRQ_OFS + (x))
+
+/*
+ * On FIQ1ISR register
+ */
+#define IRQ_IOP310_DMA0                IOP310_IRQ(0)   /* DMA Channel 0 */
+#define IRQ_IOP310_DMA1                IOP310_IRQ(1)   /* DMA Channel 1 */
+#define IRQ_IOP310_DMA2                IOP310_IRQ(2)   /* DMA Channel 2 */
+#define IRQ_IOP310_PMON                IOP310_IRQ(3)   /* Bus performance Unit */
+#define IRQ_IOP310_AAU         IOP310_IRQ(4)   /* Application Accelator Unit */
+
+/*
+ * On FIQ2ISR register
+ */
+#define IRQ_IOP310_I2C         IOP310_IRQ(5)   /* I2C unit */
+#define IRQ_IOP310_MU          IOP310_IRQ(6)   /* messaging unit */
+
+#define NR_IOP310_IRQS         (IOP310_IRQ(6) + 1)
+
+#define NR_IRQS                        NR_IOP310_IRQS
+
+
+/*
+ * Interrupts available on the Cyclone IQ80310 board
+ */
+#ifdef CONFIG_ARCH_IQ80310
+
+#define IQ80310_IRQ_OFS                NR_IOP310_IRQS
+#define IQ80310_IRQ(y)         ((IQ80310_IRQ_OFS) + (y))
+
+#define IRQ_IQ80310_TIMER      IQ80310_IRQ(0)  /* Timer Interrupt */
+#define IRQ_IQ80310_I82559     IQ80310_IRQ(1)  /* I82559 Ethernet Interrupt */
+#define IRQ_IQ80310_UART1      IQ80310_IRQ(2)  /* UART1 Interrupt */
+#define IRQ_IQ80310_UART2      IQ80310_IRQ(3)  /* UART2 Interrupt */
+#define IRQ_IQ80310_INTD       IQ80310_IRQ(4)  /* PCI INTD */
+
+
+/*
+ * ONLY AVAILABLE ON REV F OR NEWER BOARDS!
+ */
+#define        IRQ_IQ80310_INTA        IQ80310_IRQ(5)  /* PCI INTA */
+#define        IRQ_IQ80310_INTB        IQ80310_IRQ(6)  /* PCI INTB */
+#define        IRQ_IQ80310_INTC        IQ80310_IRQ(7)  /* PCI INTC */
+
+#undef NR_IRQS
+#define NR_IRQS                        (IQ80310_IRQ(7) + 1)
+
+#endif // CONFIG_ARCH_IQ80310
+