]> git.hungrycats.org Git - linux/commitdiff
ASoC: fsl_easrc: sort the register default table
authorPeter Ujfalusi <peter.ujfalusi@linux.intel.com>
Wed, 5 Aug 2026 12:27:28 +0000 (15:27 +0300)
committerMark Brown <broonie@kernel.org>
Fri, 7 Aug 2026 14:53:41 +0000 (15:53 +0100)
reg_defaults must be sorted by ascending register address, as
regcache_lookup_reg() locates entries in it with bsearch().  See commit
fd80df352ba1 ("regcache: Add support for sorting defaults arrays").

The four REG_EASRC_RRL() entries are listed as a block before the four
REG_EASRC_RRH() ones, but the two registers of a context alternate in
the address map (RRL(n) at 0x110 + 8 * n, RRH(n) at 0x114 + 8 * n).
This leaves REG_EASRC_RRL(1), REG_EASRC_RRL(2) and REG_EASRC_RRL(3)
unreachable.  regcache_reg_needs_sync() then cannot compare them against
their default and reports that a sync is needed, so they are written to
the device on every regcache_sync() even when they were never touched.

Sort the table by register address.

Fixes: 955ac624058f ("ASoC: fsl_easrc: Add EASRC ASoC CPU DAI drivers")
Cc: stable@vger.kernel.org
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://patch.msgid.link/20260805122728.12362-3-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/fsl/fsl_easrc.c

index 8535ef844ce031cb190179d20946eff3b0edc60f..6ccba3706b58d6833e8e0b5a0e5c21373e9334aa 100644 (file)
@@ -1711,12 +1711,12 @@ static const struct reg_default fsl_easrc_reg_defaults[] = {
        {REG_EASRC_SFS(2),      0x00000000},
        {REG_EASRC_SFS(3),      0x00000000},
        {REG_EASRC_RRL(0),      0x00000000},
-       {REG_EASRC_RRL(1),      0x00000000},
-       {REG_EASRC_RRL(2),      0x00000000},
-       {REG_EASRC_RRL(3),      0x00000000},
        {REG_EASRC_RRH(0),      0x00000000},
+       {REG_EASRC_RRL(1),      0x00000000},
        {REG_EASRC_RRH(1),      0x00000000},
+       {REG_EASRC_RRL(2),      0x00000000},
        {REG_EASRC_RRH(2),      0x00000000},
+       {REG_EASRC_RRL(3),      0x00000000},
        {REG_EASRC_RRH(3),      0x00000000},
        {REG_EASRC_RUC(0),      0x00000000},
        {REG_EASRC_RUC(1),      0x00000000},