]> git.hungrycats.org Git - linux/commitdiff
MIPS: Octeon: Remove udelay() causing huge IRQ latency
authorAlexander Sverdlin <alexander.sverdlin@nokia.com>
Wed, 18 Mar 2015 13:05:21 +0000 (14:05 +0100)
committerWilly Tarreau <w@1wt.eu>
Fri, 18 Sep 2015 11:52:06 +0000 (13:52 +0200)
commit 73bf3c2a500b2db8ac966469591196bf55afb409 upstream.

udelay() in PCI/PCIe read/write callbacks cause 30ms IRQ latency on Octeon
platforms because these operations are called from PCI_OP_READ() and
PCI_OP_WRITE() under raw_spin_lock_irqsave().

Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com>
Cc: linux-mips@linux-mips.org
Cc: David Daney <ddaney@cavium.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Jiri Kosina <jkosina@suse.cz>
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: Masanari Iida <standby24x7@gmail.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Mathias <mathias.rulf@nokia.com>
Patchwork: https://patchwork.linux-mips.org/patch/9576/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[bwh: Backported to 3.2: adjust context]
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
(cherry picked from commit 53493d44a771a3155ee12b6ac668fb2543d21a7a)

Signed-off-by: Willy Tarreau <w@1wt.eu>
arch/mips/include/asm/octeon/pci-octeon.h
arch/mips/pci/pci-octeon.c
arch/mips/pci/pcie-octeon.c

index 6ac5d3e3398eaff20144dafc5190910eb8f4ef13..5eda9f0acdfc833559eb5a3529ef96e81783f76f 100644 (file)
@@ -11,9 +11,6 @@
 
 #include <linux/pci.h>
 
-/* Some PCI cards require delays when accessing config space. */
-#define PCI_CONFIG_SPACE_DELAY 10000
-
 /*
  * pcibios_map_irq() is defined inside pci-octeon.c. All it does is
  * call the Octeon specific version pointed to by this variable. This
index 9cb0c807f564bdc00ac7e0f3f4e6ee43d4c1d730..dae7ff7e7bc6c3379bc4b2f53c8e33620d6a11f1 100644 (file)
@@ -274,9 +274,6 @@ static int octeon_read_config(struct pci_bus *bus, unsigned int devfn,
        pci_addr.s.func = devfn & 0x7;
        pci_addr.s.reg = reg;
 
-#if PCI_CONFIG_SPACE_DELAY
-       udelay(PCI_CONFIG_SPACE_DELAY);
-#endif
        switch (size) {
        case 4:
                *val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64));
@@ -311,9 +308,6 @@ static int octeon_write_config(struct pci_bus *bus, unsigned int devfn,
        pci_addr.s.func = devfn & 0x7;
        pci_addr.s.reg = reg;
 
-#if PCI_CONFIG_SPACE_DELAY
-       udelay(PCI_CONFIG_SPACE_DELAY);
-#endif
        switch (size) {
        case 4:
                cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val));
index 6aa5c542d52dff2a72670722ad882ef79418594e..97813f3ad259dd34ed220438d83765b64a15aab4 100644 (file)
@@ -1192,9 +1192,6 @@ static inline int octeon_pcie_write_config(int pcie_port, struct pci_bus *bus,
                                        devfn & 0x7, reg, val);
                return PCIBIOS_SUCCESSFUL;
        }
-#if PCI_CONFIG_SPACE_DELAY
-       udelay(PCI_CONFIG_SPACE_DELAY);
-#endif
        return PCIBIOS_FUNC_NOT_SUPPORTED;
 }