DO_DEFAULT_RTC,
DO_CIA_IO,
DO_CIA_BUS,
- machine_check: cia_machine_check,
- max_isa_dma_address: ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS,
- min_io_address: EISA_DEFAULT_IO_BASE,
- min_mem_address: CIA_DEFAULT_MEM_BASE,
-
- nr_irqs: 48,
- device_interrupt: alcor_device_interrupt,
-
- init_arch: cia_init_arch,
- init_irq: alcor_init_irq,
- init_rtc: common_init_rtc,
- init_pci: cia_init_pci,
- kill_arch: alcor_kill_arch,
- pci_map_irq: alcor_map_irq,
- pci_swizzle: common_swizzle,
-
- sys: { cia: {
- gru_int_req_bits: ALCOR_GRU_INT_REQ_BITS
+ .machine_check = cia_machine_check,
- .max_dma_address = ALPHA_ALCOR_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = EISA_DEFAULT_IO_BASE,
+ .min_mem_address = CIA_DEFAULT_MEM_BASE,
+
+ .nr_irqs = 48,
+ .device_interrupt = alcor_device_interrupt,
+
+ .init_arch = cia_init_arch,
+ .init_irq = alcor_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = cia_init_pci,
+ .kill_arch = alcor_kill_arch,
+ .pci_map_irq = alcor_map_irq,
+ .pci_swizzle = common_swizzle,
+
+ .sys = { .cia = {
+ .gru_int_req_bits = ALCOR_GRU_INT_REQ_BITS
}}
};
ALIAS_MV(alcor)
DO_DEFAULT_RTC,
DO_CIA_IO,
DO_CIA_BUS,
- machine_check: cia_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: EISA_DEFAULT_IO_BASE,
- min_mem_address: CIA_DEFAULT_MEM_BASE,
-
- nr_irqs: 48,
- device_interrupt: alcor_device_interrupt,
-
- init_arch: cia_init_arch,
- init_irq: alcor_init_irq,
- init_rtc: common_init_rtc,
- init_pci: cia_init_pci,
- kill_arch: alcor_kill_arch,
- pci_map_irq: alcor_map_irq,
- pci_swizzle: common_swizzle,
-
- sys: { cia: {
- gru_int_req_bits: XLT_GRU_INT_REQ_BITS
+ .machine_check = cia_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = EISA_DEFAULT_IO_BASE,
+ .min_mem_address = CIA_DEFAULT_MEM_BASE,
+
+ .nr_irqs = 48,
+ .device_interrupt = alcor_device_interrupt,
+
+ .init_arch = cia_init_arch,
+ .init_irq = alcor_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = cia_init_pci,
+ .kill_arch = alcor_kill_arch,
+ .pci_map_irq = alcor_map_irq,
+ .pci_swizzle = common_swizzle,
+
+ .sys = { .cia = {
+ .gru_int_req_bits = XLT_GRU_INT_REQ_BITS
}}
};
ALIAS_MV(xlt)
DO_DEFAULT_RTC,
DO_APECS_IO,
DO_APECS_BUS,
- machine_check: apecs_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: APECS_AND_LCA_DEFAULT_MEM_BASE,
-
- nr_irqs: 35,
- device_interrupt: cabriolet_device_interrupt,
-
- init_arch: apecs_init_arch,
- init_irq: cabriolet_init_irq,
- init_rtc: common_init_rtc,
- init_pci: cabriolet_init_pci,
- kill_arch: NULL,
- pci_map_irq: cabriolet_map_irq,
- pci_swizzle: common_swizzle,
+ .machine_check = apecs_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
+
+ .nr_irqs = 35,
+ .device_interrupt = cabriolet_device_interrupt,
+
+ .init_arch = apecs_init_arch,
+ .init_irq = cabriolet_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = cabriolet_init_pci,
+ .kill_arch = NULL,
+ .pci_map_irq = cabriolet_map_irq,
+ .pci_swizzle = common_swizzle,
};
#ifndef CONFIG_ALPHA_EB64P
ALIAS_MV(cabriolet)
DO_DEFAULT_RTC,
DO_CIA_IO,
DO_CIA_BUS,
- machine_check: cia_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: CIA_DEFAULT_MEM_BASE,
-
- nr_irqs: 35,
- device_interrupt: cabriolet_device_interrupt,
-
- init_arch: cia_init_arch,
- init_irq: cabriolet_init_irq,
- init_rtc: common_init_rtc,
- init_pci: cia_cab_init_pci,
- pci_map_irq: cabriolet_map_irq,
- pci_swizzle: common_swizzle,
+ .machine_check = cia_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = CIA_DEFAULT_MEM_BASE,
+
+ .nr_irqs = 35,
+ .device_interrupt = cabriolet_device_interrupt,
+
+ .init_arch = cia_init_arch,
+ .init_irq = cabriolet_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = cia_cab_init_pci,
+ .pci_map_irq = cabriolet_map_irq,
+ .pci_swizzle = common_swizzle,
};
ALIAS_MV(eb164)
#endif
DO_DEFAULT_RTC,
DO_LCA_IO,
DO_LCA_BUS,
- machine_check: lca_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: APECS_AND_LCA_DEFAULT_MEM_BASE,
-
- nr_irqs: 35,
- device_interrupt: cabriolet_device_interrupt,
-
- init_arch: lca_init_arch,
- init_irq: cabriolet_init_irq,
- init_rtc: common_init_rtc,
- init_pci: cabriolet_init_pci,
- pci_map_irq: eb66p_map_irq,
- pci_swizzle: common_swizzle,
+ .machine_check = lca_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
+
+ .nr_irqs = 35,
+ .device_interrupt = cabriolet_device_interrupt,
+
+ .init_arch = lca_init_arch,
+ .init_irq = cabriolet_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = cabriolet_init_pci,
+ .pci_map_irq = eb66p_map_irq,
+ .pci_swizzle = common_swizzle,
};
ALIAS_MV(eb66p)
#endif
DO_DEFAULT_RTC,
DO_PYXIS_IO,
DO_CIA_BUS,
- machine_check: cia_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: DEFAULT_MEM_BASE,
- pci_dac_offset: PYXIS_DAC_OFFSET,
-
- nr_irqs: 35,
- device_interrupt: cabriolet_device_interrupt,
-
- init_arch: pyxis_init_arch,
- init_irq: cabriolet_init_irq,
- init_rtc: common_init_rtc,
- init_pci: alphapc164_init_pci,
- pci_map_irq: alphapc164_map_irq,
- pci_swizzle: common_swizzle,
+ .machine_check = cia_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = DEFAULT_MEM_BASE,
+ .pci_dac_offset = PYXIS_DAC_OFFSET,
+
+ .nr_irqs = 35,
+ .device_interrupt = cabriolet_device_interrupt,
+
+ .init_arch = pyxis_init_arch,
+ .init_irq = cabriolet_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = alphapc164_init_pci,
+ .pci_map_irq = alphapc164_map_irq,
+ .pci_swizzle = common_swizzle,
};
ALIAS_MV(lx164)
#endif
DO_DEFAULT_RTC,
DO_CIA_IO,
DO_CIA_BUS,
- machine_check: cia_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: CIA_DEFAULT_MEM_BASE,
-
- nr_irqs: 35,
- device_interrupt: pc164_device_interrupt,
-
- init_arch: cia_init_arch,
- init_irq: pc164_init_irq,
- init_rtc: common_init_rtc,
- init_pci: alphapc164_init_pci,
- pci_map_irq: alphapc164_map_irq,
- pci_swizzle: common_swizzle,
+ .machine_check = cia_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = CIA_DEFAULT_MEM_BASE,
+
+ .nr_irqs = 35,
+ .device_interrupt = pc164_device_interrupt,
+
+ .init_arch = cia_init_arch,
+ .init_irq = pc164_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = alphapc164_init_pci,
+ .pci_map_irq = alphapc164_map_irq,
+ .pci_swizzle = common_swizzle,
};
ALIAS_MV(pc164)
#endif
DO_DEFAULT_RTC,
DO_TSUNAMI_IO,
DO_TSUNAMI_BUS,
- machine_check: tsunami_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: DEFAULT_MEM_BASE,
- pci_dac_offset: TSUNAMI_DAC_OFFSET,
-
- nr_irqs: 64,
- device_interrupt: dp264_device_interrupt,
-
- init_arch: tsunami_init_arch,
- init_irq: dp264_init_irq,
- init_rtc: common_init_rtc,
- init_pci: dp264_init_pci,
- kill_arch: tsunami_kill_arch,
- pci_map_irq: dp264_map_irq,
- pci_swizzle: common_swizzle,
+ .machine_check = tsunami_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = DEFAULT_MEM_BASE,
+ .pci_dac_offset = TSUNAMI_DAC_OFFSET,
+
+ .nr_irqs = 64,
+ .device_interrupt = dp264_device_interrupt,
+
+ .init_arch = tsunami_init_arch,
+ .init_irq = dp264_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = dp264_init_pci,
+ .kill_arch = tsunami_kill_arch,
+ .pci_map_irq = dp264_map_irq,
+ .pci_swizzle = common_swizzle,
};
ALIAS_MV(dp264)
DO_DEFAULT_RTC,
DO_TSUNAMI_IO,
DO_TSUNAMI_BUS,
- machine_check: tsunami_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: DEFAULT_MEM_BASE,
- pci_dac_offset: TSUNAMI_DAC_OFFSET,
-
- nr_irqs: 64,
- device_interrupt: dp264_device_interrupt,
-
- init_arch: tsunami_init_arch,
- init_irq: dp264_init_irq,
- init_rtc: common_init_rtc,
- init_pci: monet_init_pci,
- kill_arch: tsunami_kill_arch,
- pci_map_irq: monet_map_irq,
- pci_swizzle: monet_swizzle,
+ .machine_check = tsunami_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = DEFAULT_MEM_BASE,
+ .pci_dac_offset = TSUNAMI_DAC_OFFSET,
+
+ .nr_irqs = 64,
+ .device_interrupt = dp264_device_interrupt,
+
+ .init_arch = tsunami_init_arch,
+ .init_irq = dp264_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = monet_init_pci,
+ .kill_arch = tsunami_kill_arch,
+ .pci_map_irq = monet_map_irq,
+ .pci_swizzle = monet_swizzle,
};
struct alpha_machine_vector webbrick_mv __initmv = {
DO_DEFAULT_RTC,
DO_TSUNAMI_IO,
DO_TSUNAMI_BUS,
- machine_check: tsunami_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: DEFAULT_MEM_BASE,
- pci_dac_offset: TSUNAMI_DAC_OFFSET,
-
- nr_irqs: 64,
- device_interrupt: dp264_device_interrupt,
-
- init_arch: webbrick_init_arch,
- init_irq: dp264_init_irq,
- init_rtc: common_init_rtc,
- init_pci: common_init_pci,
- kill_arch: tsunami_kill_arch,
- pci_map_irq: webbrick_map_irq,
- pci_swizzle: common_swizzle,
+ .machine_check = tsunami_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = DEFAULT_MEM_BASE,
+ .pci_dac_offset = TSUNAMI_DAC_OFFSET,
+
+ .nr_irqs = 64,
+ .device_interrupt = dp264_device_interrupt,
+
+ .init_arch = webbrick_init_arch,
+ .init_irq = dp264_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = common_init_pci,
+ .kill_arch = tsunami_kill_arch,
+ .pci_map_irq = webbrick_map_irq,
+ .pci_swizzle = common_swizzle,
};
struct alpha_machine_vector clipper_mv __initmv = {
DO_DEFAULT_RTC,
DO_TSUNAMI_IO,
DO_TSUNAMI_BUS,
- machine_check: tsunami_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: DEFAULT_MEM_BASE,
- pci_dac_offset: TSUNAMI_DAC_OFFSET,
-
- nr_irqs: 64,
- device_interrupt: dp264_device_interrupt,
-
- init_arch: tsunami_init_arch,
- init_irq: clipper_init_irq,
- init_rtc: common_init_rtc,
- init_pci: common_init_pci,
- kill_arch: tsunami_kill_arch,
- pci_map_irq: clipper_map_irq,
- pci_swizzle: common_swizzle,
+ .machine_check = tsunami_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = DEFAULT_MEM_BASE,
+ .pci_dac_offset = TSUNAMI_DAC_OFFSET,
+
+ .nr_irqs = 64,
+ .device_interrupt = dp264_device_interrupt,
+
+ .init_arch = tsunami_init_arch,
+ .init_irq = clipper_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = common_init_pci,
+ .kill_arch = tsunami_kill_arch,
+ .pci_map_irq = clipper_map_irq,
+ .pci_swizzle = common_swizzle,
};
/* Sharks strongly resemble Clipper, at least as far
DO_DEFAULT_RTC,
DO_TSUNAMI_IO,
DO_TSUNAMI_BUS,
- machine_check: tsunami_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: DEFAULT_MEM_BASE,
- pci_dac_offset: TSUNAMI_DAC_OFFSET,
-
- nr_irqs: 64,
- device_interrupt: dp264_device_interrupt,
-
- init_arch: tsunami_init_arch,
- init_irq: clipper_init_irq,
- init_rtc: common_init_rtc,
- init_pci: common_init_pci,
- kill_arch: tsunami_kill_arch,
- pci_map_irq: clipper_map_irq,
- pci_swizzle: common_swizzle,
+ .machine_check = tsunami_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = DEFAULT_MEM_BASE,
+ .pci_dac_offset = TSUNAMI_DAC_OFFSET,
+
+ .nr_irqs = 64,
+ .device_interrupt = dp264_device_interrupt,
+
+ .init_arch = tsunami_init_arch,
+ .init_irq = clipper_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = common_init_pci,
+ .kill_arch = tsunami_kill_arch,
+ .pci_map_irq = clipper_map_irq,
+ .pci_swizzle = common_swizzle,
};
/* No alpha_mv alias for webbrick/monet/clipper, since we compile them
DO_DEFAULT_RTC,
DO_APECS_IO,
DO_APECS_BUS,
- machine_check: apecs_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: APECS_AND_LCA_DEFAULT_MEM_BASE,
-
- nr_irqs: 32,
- device_interrupt: eb64p_device_interrupt,
-
- init_arch: apecs_init_arch,
- init_irq: eb64p_init_irq,
- init_rtc: common_init_rtc,
- init_pci: common_init_pci,
- kill_arch: NULL,
- pci_map_irq: eb64p_map_irq,
- pci_swizzle: common_swizzle,
+ .machine_check = apecs_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
+
+ .nr_irqs = 32,
+ .device_interrupt = eb64p_device_interrupt,
+
+ .init_arch = apecs_init_arch,
+ .init_irq = eb64p_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = common_init_pci,
+ .kill_arch = NULL,
+ .pci_map_irq = eb64p_map_irq,
+ .pci_swizzle = common_swizzle,
};
ALIAS_MV(eb64p)
#endif
DO_DEFAULT_RTC,
DO_LCA_IO,
DO_LCA_BUS,
- machine_check: lca_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: APECS_AND_LCA_DEFAULT_MEM_BASE,
-
- nr_irqs: 32,
- device_interrupt: eb64p_device_interrupt,
-
- init_arch: lca_init_arch,
- init_irq: eb64p_init_irq,
- init_rtc: common_init_rtc,
- init_pci: common_init_pci,
- pci_map_irq: eb64p_map_irq,
- pci_swizzle: common_swizzle,
+ .machine_check = lca_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
+
+ .nr_irqs = 32,
+ .device_interrupt = eb64p_device_interrupt,
+
+ .init_arch = lca_init_arch,
+ .init_irq = eb64p_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = common_init_pci,
+ .pci_map_irq = eb64p_map_irq,
+ .pci_swizzle = common_swizzle,
};
ALIAS_MV(eb66)
#endif
DO_DEFAULT_RTC,
DO_TSUNAMI_IO,
DO_TSUNAMI_BUS,
- machine_check: tsunami_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: DEFAULT_MEM_BASE,
- pci_dac_offset: TSUNAMI_DAC_OFFSET,
-
- nr_irqs: 128,
- device_interrupt: eiger_device_interrupt,
-
- init_arch: tsunami_init_arch,
- init_irq: eiger_init_irq,
- init_rtc: common_init_rtc,
- init_pci: common_init_pci,
- kill_arch: tsunami_kill_arch,
- pci_map_irq: eiger_map_irq,
- pci_swizzle: eiger_swizzle,
+ .machine_check = tsunami_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = DEFAULT_MEM_BASE,
+ .pci_dac_offset = TSUNAMI_DAC_OFFSET,
+
+ .nr_irqs = 128,
+ .device_interrupt = eiger_device_interrupt,
+
+ .init_arch = tsunami_init_arch,
+ .init_irq = eiger_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = common_init_pci,
+ .kill_arch = tsunami_kill_arch,
+ .pci_map_irq = eiger_map_irq,
+ .pci_swizzle = eiger_swizzle,
};
ALIAS_MV(eiger)
DO_EV4_MMU,
IO_LITE(JENSEN,jensen),
BUS(jensen),
- machine_check: jensen_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- rtc_port: 0x170,
-
- nr_irqs: 16,
- device_interrupt: jensen_device_interrupt,
-
- init_arch: jensen_init_arch,
- init_irq: jensen_init_irq,
- init_rtc: common_init_rtc,
- init_pci: NULL,
- kill_arch: NULL,
+ .machine_check = jensen_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .rtc_port = 0x170,
+
+ .nr_irqs = 16,
+ .device_interrupt = jensen_device_interrupt,
+
+ .init_arch = jensen_init_arch,
+ .init_irq = jensen_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = NULL,
+ .kill_arch = NULL,
};
ALIAS_MV(jensen)
DO_DEFAULT_RTC,
DO_PYXIS_IO,
DO_CIA_BUS,
- machine_check: cia_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: DEFAULT_MEM_BASE,
- pci_dac_offset: PYXIS_DAC_OFFSET,
+ .machine_check = cia_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = DEFAULT_MEM_BASE,
+ .pci_dac_offset = PYXIS_DAC_OFFSET,
- nr_irqs: 48,
- device_interrupt: pyxis_device_interrupt,
+ .nr_irqs = 48,
+ .device_interrupt = pyxis_device_interrupt,
- init_arch: pyxis_init_arch,
- init_irq: miata_init_irq,
- init_rtc: common_init_rtc,
- init_pci: miata_init_pci,
- kill_arch: miata_kill_arch,
- pci_map_irq: miata_map_irq,
- pci_swizzle: miata_swizzle,
+ .init_arch = pyxis_init_arch,
+ .init_irq = miata_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = miata_init_pci,
+ .kill_arch = miata_kill_arch,
+ .pci_map_irq = miata_map_irq,
+ .pci_swizzle = miata_swizzle,
};
ALIAS_MV(miata)
DO_DEFAULT_RTC,
DO_APECS_IO,
DO_APECS_BUS,
- machine_check: mikasa_apecs_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: APECS_AND_LCA_DEFAULT_MEM_BASE,
-
- nr_irqs: 32,
- device_interrupt: mikasa_device_interrupt,
-
- init_arch: apecs_init_arch,
- init_irq: mikasa_init_irq,
- init_rtc: common_init_rtc,
- init_pci: common_init_pci,
- kill_arch: NULL,
- pci_map_irq: mikasa_map_irq,
- pci_swizzle: common_swizzle,
+ .machine_check = mikasa_apecs_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
+
+ .nr_irqs = 32,
+ .device_interrupt = mikasa_device_interrupt,
+
+ .init_arch = apecs_init_arch,
+ .init_irq = mikasa_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = common_init_pci,
+ .kill_arch = NULL,
+ .pci_map_irq = mikasa_map_irq,
+ .pci_swizzle = common_swizzle,
};
ALIAS_MV(mikasa)
#endif
DO_DEFAULT_RTC,
DO_CIA_IO,
DO_CIA_BUS,
- machine_check: cia_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: CIA_DEFAULT_MEM_BASE,
-
- nr_irqs: 32,
- device_interrupt: mikasa_device_interrupt,
-
- init_arch: cia_init_arch,
- init_irq: mikasa_init_irq,
- init_rtc: common_init_rtc,
- init_pci: cia_init_pci,
- pci_map_irq: mikasa_map_irq,
- pci_swizzle: common_swizzle,
+ .machine_check = cia_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = CIA_DEFAULT_MEM_BASE,
+
+ .nr_irqs = 32,
+ .device_interrupt = mikasa_device_interrupt,
+
+ .init_arch = cia_init_arch,
+ .init_irq = mikasa_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = cia_init_pci,
+ .pci_map_irq = mikasa_map_irq,
+ .pci_swizzle = common_swizzle,
};
ALIAS_MV(mikasa_primo)
#endif
DO_DEFAULT_RTC,
DO_IRONGATE_IO,
DO_IRONGATE_BUS,
- machine_check: nautilus_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: IRONGATE_DEFAULT_MEM_BASE,
-
- nr_irqs: 16,
- device_interrupt: isa_device_interrupt,
-
- init_arch: irongate_init_arch,
- init_irq: nautilus_init_irq,
- init_rtc: common_init_rtc,
- init_pci: common_init_pci,
- kill_arch: nautilus_kill_arch,
- pci_map_irq: nautilus_map_irq,
- pci_swizzle: common_swizzle,
+ .machine_check = nautilus_machine_check,
- .max_dma_address = ALPHA_NAUTILUS_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = IRONGATE_DEFAULT_MEM_BASE,
+
+ .nr_irqs = 16,
+ .device_interrupt = isa_device_interrupt,
+
+ .init_arch = irongate_init_arch,
+ .init_irq = nautilus_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = common_init_pci,
+ .kill_arch = nautilus_kill_arch,
+ .pci_map_irq = nautilus_map_irq,
+ .pci_swizzle = common_swizzle,
};
ALIAS_MV(nautilus)
DO_DEFAULT_RTC,
DO_APECS_IO,
DO_APECS_BUS,
- machine_check: noritake_apecs_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: EISA_DEFAULT_IO_BASE,
- min_mem_address: APECS_AND_LCA_DEFAULT_MEM_BASE,
-
- nr_irqs: 48,
- device_interrupt: noritake_device_interrupt,
-
- init_arch: apecs_init_arch,
- init_irq: noritake_init_irq,
- init_rtc: common_init_rtc,
- init_pci: common_init_pci,
- kill_arch: NULL,
- pci_map_irq: noritake_map_irq,
- pci_swizzle: noritake_swizzle,
+ .machine_check = noritake_apecs_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = EISA_DEFAULT_IO_BASE,
+ .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
+
+ .nr_irqs = 48,
+ .device_interrupt = noritake_device_interrupt,
+
+ .init_arch = apecs_init_arch,
+ .init_irq = noritake_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = common_init_pci,
+ .kill_arch = NULL,
+ .pci_map_irq = noritake_map_irq,
+ .pci_swizzle = noritake_swizzle,
};
ALIAS_MV(noritake)
#endif
DO_DEFAULT_RTC,
DO_CIA_IO,
DO_CIA_BUS,
- machine_check: cia_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: EISA_DEFAULT_IO_BASE,
- min_mem_address: CIA_DEFAULT_MEM_BASE,
-
- nr_irqs: 48,
- device_interrupt: noritake_device_interrupt,
-
- init_arch: cia_init_arch,
- init_irq: noritake_init_irq,
- init_rtc: common_init_rtc,
- init_pci: cia_init_pci,
- pci_map_irq: noritake_map_irq,
- pci_swizzle: noritake_swizzle,
+ .machine_check = cia_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = EISA_DEFAULT_IO_BASE,
+ .min_mem_address = CIA_DEFAULT_MEM_BASE,
+
+ .nr_irqs = 48,
+ .device_interrupt = noritake_device_interrupt,
+
+ .init_arch = cia_init_arch,
+ .init_irq = noritake_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = cia_init_pci,
+ .pci_map_irq = noritake_map_irq,
+ .pci_swizzle = noritake_swizzle,
};
ALIAS_MV(noritake_primo)
#endif
DO_DEFAULT_RTC,
DO_MCPCIA_IO,
DO_MCPCIA_BUS,
- machine_check: mcpcia_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: MCPCIA_DEFAULT_MEM_BASE,
- pci_dac_offset: MCPCIA_DAC_OFFSET,
-
- nr_irqs: 128,
- device_interrupt: rawhide_srm_device_interrupt,
-
- init_arch: mcpcia_init_arch,
- init_irq: rawhide_init_irq,
- init_rtc: common_init_rtc,
- init_pci: common_init_pci,
- kill_arch: NULL,
- pci_map_irq: rawhide_map_irq,
- pci_swizzle: common_swizzle,
+ .machine_check = mcpcia_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = MCPCIA_DEFAULT_MEM_BASE,
+ .pci_dac_offset = MCPCIA_DAC_OFFSET,
+
+ .nr_irqs = 128,
+ .device_interrupt = rawhide_srm_device_interrupt,
+
+ .init_arch = mcpcia_init_arch,
+ .init_irq = rawhide_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = common_init_pci,
+ .kill_arch = NULL,
+ .pci_map_irq = rawhide_map_irq,
+ .pci_swizzle = common_swizzle,
};
ALIAS_MV(rawhide)
DO_DEFAULT_RTC,
DO_PYXIS_IO,
DO_CIA_BUS,
- machine_check: cia_machine_check,
- max_isa_dma_address: ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: DEFAULT_MEM_BASE,
- pci_dac_offset: PYXIS_DAC_OFFSET,
-
- nr_irqs: 48,
- device_interrupt: pyxis_device_interrupt,
-
- init_arch: pyxis_init_arch,
- init_irq: ruffian_init_irq,
- init_rtc: ruffian_init_rtc,
- init_pci: cia_init_pci,
- kill_arch: ruffian_kill_arch,
- pci_map_irq: ruffian_map_irq,
- pci_swizzle: ruffian_swizzle,
+ .machine_check = cia_machine_check,
- .max_dma_address = ALPHA_RUFFIAN_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = DEFAULT_MEM_BASE,
+ .pci_dac_offset = PYXIS_DAC_OFFSET,
+
+ .nr_irqs = 48,
+ .device_interrupt = pyxis_device_interrupt,
+
+ .init_arch = pyxis_init_arch,
+ .init_irq = ruffian_init_irq,
+ .init_rtc = ruffian_init_rtc,
+ .init_pci = cia_init_pci,
+ .kill_arch = ruffian_kill_arch,
+ .pci_map_irq = ruffian_map_irq,
+ .pci_swizzle = ruffian_swizzle,
};
ALIAS_MV(ruffian)
DO_DEFAULT_RTC,
DO_POLARIS_IO,
DO_POLARIS_BUS,
- machine_check: polaris_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: DEFAULT_MEM_BASE,
-
- nr_irqs: 40,
- device_interrupt: rx164_device_interrupt,
-
- init_arch: polaris_init_arch,
- init_irq: rx164_init_irq,
- init_rtc: common_init_rtc,
- init_pci: common_init_pci,
- kill_arch: NULL,
- pci_map_irq: rx164_map_irq,
- pci_swizzle: common_swizzle,
+ .machine_check = polaris_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = DEFAULT_MEM_BASE,
+
+ .nr_irqs = 40,
+ .device_interrupt = rx164_device_interrupt,
+
+ .init_arch = polaris_init_arch,
+ .init_irq = rx164_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = common_init_pci,
+ .kill_arch = NULL,
+ .pci_map_irq = rx164_map_irq,
+ .pci_swizzle = common_swizzle,
};
ALIAS_MV(rx164)
DO_DEFAULT_RTC,
DO_T2_IO,
DO_T2_BUS,
- machine_check: t2_machine_check,
- max_isa_dma_address: ALPHA_SABLE_MAX_ISA_DMA_ADDRESS,
- min_io_address: EISA_DEFAULT_IO_BASE,
- min_mem_address: T2_DEFAULT_MEM_BASE,
-
- nr_irqs: 40,
- device_interrupt: sable_srm_device_interrupt,
-
- init_arch: t2_init_arch,
- init_irq: sable_init_irq,
- init_rtc: common_init_rtc,
- init_pci: common_init_pci,
- kill_arch: NULL,
- pci_map_irq: sable_map_irq,
- pci_swizzle: common_swizzle,
-
- sys: { t2: {
- gamma_bias: 0
+ .machine_check = t2_machine_check,
- .max_dma_address = ALPHA_SABLE_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_SABLE_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = EISA_DEFAULT_IO_BASE,
+ .min_mem_address = T2_DEFAULT_MEM_BASE,
+
+ .nr_irqs = 40,
+ .device_interrupt = sable_srm_device_interrupt,
+
+ .init_arch = t2_init_arch,
+ .init_irq = sable_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = common_init_pci,
+ .kill_arch = NULL,
+ .pci_map_irq = sable_map_irq,
+ .pci_swizzle = common_swizzle,
+
+ .sys = { .t2 = {
+ .gamma_bias = 0
} }
};
ALIAS_MV(sable)
DO_DEFAULT_RTC,
DO_T2_IO,
DO_T2_BUS,
- machine_check: t2_machine_check,
- max_isa_dma_address: ALPHA_SABLE_MAX_ISA_DMA_ADDRESS,
- min_io_address: EISA_DEFAULT_IO_BASE,
- min_mem_address: T2_DEFAULT_MEM_BASE,
-
- nr_irqs: 40,
- device_interrupt: sable_srm_device_interrupt,
-
- init_arch: t2_init_arch,
- init_irq: sable_init_irq,
- init_rtc: common_init_rtc,
- init_pci: common_init_pci,
- pci_map_irq: sable_map_irq,
- pci_swizzle: common_swizzle,
-
- sys: { t2: {
- gamma_bias: _GAMMA_BIAS
+ .machine_check = t2_machine_check,
- .max_dma_address = ALPHA_SABLE_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_SABLE_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = EISA_DEFAULT_IO_BASE,
+ .min_mem_address = T2_DEFAULT_MEM_BASE,
+
+ .nr_irqs = 40,
+ .device_interrupt = sable_srm_device_interrupt,
+
+ .init_arch = t2_init_arch,
+ .init_irq = sable_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = common_init_pci,
+ .pci_map_irq = sable_map_irq,
+ .pci_swizzle = common_swizzle,
+
+ .sys = { .t2 = {
+ .gamma_bias = _GAMMA_BIAS
} }
};
ALIAS_MV(sable_gamma)
DO_DEFAULT_RTC,
DO_LCA_IO,
DO_LCA_BUS,
- machine_check: lca_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: APECS_AND_LCA_DEFAULT_MEM_BASE,
-
- nr_irqs: 16,
- device_interrupt: isa_device_interrupt,
-
- init_arch: alphabook1_init_arch,
- init_irq: sio_init_irq,
- init_rtc: common_init_rtc,
- init_pci: alphabook1_init_pci,
- kill_arch: NULL,
- pci_map_irq: noname_map_irq,
- pci_swizzle: common_swizzle,
-
- sys: { sio: {
+ .machine_check = lca_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
+
+ .nr_irqs = 16,
+ .device_interrupt = isa_device_interrupt,
+
+ .init_arch = alphabook1_init_arch,
+ .init_irq = sio_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = alphabook1_init_pci,
+ .kill_arch = NULL,
+ .pci_map_irq = noname_map_irq,
+ .pci_swizzle = common_swizzle,
+
+ .sys = { .sio = {
/* NCR810 SCSI is 14, PCMCIA controller is 15. */
- route_tab: 0x0e0f0a0a,
+ .route_tab = 0x0e0f0a0a,
}}
};
ALIAS_MV(alphabook1)
DO_DEFAULT_RTC,
DO_APECS_IO,
DO_APECS_BUS,
- machine_check: apecs_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: APECS_AND_LCA_DEFAULT_MEM_BASE,
-
- nr_irqs: 16,
- device_interrupt: isa_device_interrupt,
-
- init_arch: apecs_init_arch,
- init_irq: sio_init_irq,
- init_rtc: common_init_rtc,
- init_pci: noname_init_pci,
- pci_map_irq: noname_map_irq,
- pci_swizzle: common_swizzle,
-
- sys: { sio: {
- route_tab: 0x0b0a0e0f,
+ .machine_check = apecs_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
+
+ .nr_irqs = 16,
+ .device_interrupt = isa_device_interrupt,
+
+ .init_arch = apecs_init_arch,
+ .init_irq = sio_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = noname_init_pci,
+ .pci_map_irq = noname_map_irq,
+ .pci_swizzle = common_swizzle,
+
+ .sys = { .sio = {
+ .route_tab = 0x0b0a0e0f,
}}
};
ALIAS_MV(avanti)
DO_DEFAULT_RTC,
DO_LCA_IO,
DO_LCA_BUS,
- machine_check: lca_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: APECS_AND_LCA_DEFAULT_MEM_BASE,
-
- nr_irqs: 16,
- device_interrupt: srm_device_interrupt,
-
- init_arch: lca_init_arch,
- init_irq: sio_init_irq,
- init_rtc: common_init_rtc,
- init_pci: noname_init_pci,
- pci_map_irq: noname_map_irq,
- pci_swizzle: common_swizzle,
-
- sys: { sio: {
+ .machine_check = lca_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
+
+ .nr_irqs = 16,
+ .device_interrupt = srm_device_interrupt,
+
+ .init_arch = lca_init_arch,
+ .init_irq = sio_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = noname_init_pci,
+ .pci_map_irq = noname_map_irq,
+ .pci_swizzle = common_swizzle,
+
+ .sys = { .sio = {
/* For UDB, the only available PCI slot must not map to IRQ 9,
since that's the builtin MSS sound chip. That PCI slot
will map to PIRQ1 (for INTA at least), so we give it IRQ 15
DO_DEFAULT_RTC,
DO_LCA_IO,
DO_LCA_BUS,
- machine_check: lca_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: APECS_AND_LCA_DEFAULT_MEM_BASE,
-
- nr_irqs: 16,
- device_interrupt: srm_device_interrupt,
-
- init_arch: lca_init_arch,
- init_irq: sio_init_irq,
- init_rtc: common_init_rtc,
- init_pci: noname_init_pci,
- pci_map_irq: p2k_map_irq,
- pci_swizzle: common_swizzle,
-
- sys: { sio: {
- route_tab: 0x0b0a090f,
+ .machine_check = lca_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
+
+ .nr_irqs = 16,
+ .device_interrupt = srm_device_interrupt,
+
+ .init_arch = lca_init_arch,
+ .init_irq = sio_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = noname_init_pci,
+ .pci_map_irq = p2k_map_irq,
+ .pci_swizzle = common_swizzle,
+
+ .sys = { .sio = {
+ .route_tab = 0x0b0a090f,
}}
};
ALIAS_MV(p2k)
DO_DEFAULT_RTC,
DO_APECS_IO,
BUS(apecs),
- machine_check: apecs_machine_check,
- max_isa_dma_address: ALPHA_XL_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: XL_DEFAULT_MEM_BASE,
-
- nr_irqs: 16,
- device_interrupt: isa_device_interrupt,
-
- init_arch: apecs_init_arch,
- init_irq: sio_init_irq,
- init_rtc: common_init_rtc,
- init_pci: noname_init_pci,
- pci_map_irq: noname_map_irq,
- pci_swizzle: common_swizzle,
-
- sys: { sio: {
- route_tab: 0x0b0a090f,
+ .machine_check = apecs_machine_check,
- .max_dma_address = ALPHA_XL_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_XL_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = XL_DEFAULT_MEM_BASE,
+
+ .nr_irqs = 16,
+ .device_interrupt = isa_device_interrupt,
+
+ .init_arch = apecs_init_arch,
+ .init_irq = sio_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = noname_init_pci,
+ .pci_map_irq = noname_map_irq,
+ .pci_swizzle = common_swizzle,
+
+ .sys = { .sio = {
+ .route_tab = 0x0b0a090f,
}}
};
ALIAS_MV(xl)
DO_DEFAULT_RTC,
DO_PYXIS_IO,
DO_CIA_BUS,
- machine_check: cia_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: DEFAULT_MEM_BASE,
- pci_dac_offset: PYXIS_DAC_OFFSET,
-
- nr_irqs: 48,
- device_interrupt: pyxis_device_interrupt,
-
- init_arch: sx164_init_arch,
- init_irq: sx164_init_irq,
- init_rtc: common_init_rtc,
- init_pci: sx164_init_pci,
- kill_arch: NULL,
- pci_map_irq: sx164_map_irq,
- pci_swizzle: common_swizzle,
+ .machine_check = cia_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = DEFAULT_MEM_BASE,
+ .pci_dac_offset = PYXIS_DAC_OFFSET,
+
+ .nr_irqs = 48,
+ .device_interrupt = pyxis_device_interrupt,
+
+ .init_arch = sx164_init_arch,
+ .init_irq = sx164_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = sx164_init_pci,
+ .kill_arch = NULL,
+ .pci_map_irq = sx164_map_irq,
+ .pci_swizzle = common_swizzle,
};
ALIAS_MV(sx164)
DO_DEFAULT_RTC,
DO_CIA_IO,
DO_CIA_BUS,
- machine_check: cia_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: CIA_DEFAULT_MEM_BASE,
-
- nr_irqs: 128,
- device_interrupt: takara_device_interrupt,
-
- init_arch: cia_init_arch,
- init_irq: takara_init_irq,
- init_rtc: common_init_rtc,
- init_pci: takara_init_pci,
- kill_arch: NULL,
- pci_map_irq: takara_map_irq,
- pci_swizzle: takara_swizzle,
+ .machine_check = cia_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = CIA_DEFAULT_MEM_BASE,
+
+ .nr_irqs = 128,
+ .device_interrupt = takara_device_interrupt,
+
+ .init_arch = cia_init_arch,
+ .init_irq = takara_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = takara_init_pci,
+ .kill_arch = NULL,
+ .pci_map_irq = takara_map_irq,
+ .pci_swizzle = takara_swizzle,
};
ALIAS_MV(takara)
DO_DEFAULT_RTC,
DO_TITAN_IO,
DO_TITAN_BUS,
- machine_check: privateer_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: DEFAULT_MEM_BASE,
- pci_dac_offset: TITAN_DAC_OFFSET,
-
- nr_irqs: 80, /* 64 + 16 */
- device_interrupt: privateer_device_interrupt,
-
- init_arch: titan_init_arch,
- init_irq: privateer_init_irq,
- init_rtc: common_init_rtc,
- init_pci: privateer_init_pci,
- kill_arch: titan_kill_arch,
- pci_map_irq: privateer_map_irq,
- pci_swizzle: common_swizzle,
+ .machine_check = privateer_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = DEFAULT_MEM_BASE,
+ .pci_dac_offset = TITAN_DAC_OFFSET,
+
+ .nr_irqs = 80, /* 64 + 16 */
+ .device_interrupt = privateer_device_interrupt,
+
+ .init_arch = titan_init_arch,
+ .init_irq = privateer_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = privateer_init_pci,
+ .kill_arch = titan_kill_arch,
+ .pci_map_irq = privateer_map_irq,
+ .pci_swizzle = common_swizzle,
};
ALIAS_MV(privateer)
DO_DEFAULT_RTC,
DO_WILDFIRE_IO,
DO_WILDFIRE_BUS,
- machine_check: wildfire_machine_check,
- max_isa_dma_address: ALPHA_MAX_ISA_DMA_ADDRESS,
- min_io_address: DEFAULT_IO_BASE,
- min_mem_address: DEFAULT_MEM_BASE,
-
- nr_irqs: WILDFIRE_NR_IRQS,
- device_interrupt: wildfire_device_interrupt,
-
- init_arch: wildfire_init_arch,
- init_irq: wildfire_init_irq,
- init_rtc: common_init_rtc,
- init_pci: common_init_pci,
- kill_arch: wildfire_kill_arch,
- pci_map_irq: wildfire_map_irq,
- pci_swizzle: common_swizzle,
+ .machine_check = wildfire_machine_check,
- .max_dma_address = ALPHA_MAX_DMA_ADDRESS,
++ .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
+ .min_io_address = DEFAULT_IO_BASE,
+ .min_mem_address = DEFAULT_MEM_BASE,
+
+ .nr_irqs = WILDFIRE_NR_IRQS,
+ .device_interrupt = wildfire_device_interrupt,
+
+ .init_arch = wildfire_init_arch,
+ .init_irq = wildfire_init_irq,
+ .init_rtc = common_init_rtc,
+ .init_pci = common_init_pci,
+ .kill_arch = wildfire_kill_arch,
+ .pci_map_irq = wildfire_map_irq,
+ .pci_swizzle = common_swizzle,
};
ALIAS_MV(wildfire)