handler to allow for better optimisation.
#include <linux/config.h>
#include "entry-header.S"
#include <asm/thread_info.h>
+#include <asm/glue.h>
#ifdef IOC_BASE
/*
* This routine must not corrupt r9
*/
-#ifdef MULTI_CPU
+#ifdef MULTI_ABORT
ldr r4, .LCprocfns @ pass r0, r3 to
mov lr, pc @ processor code
ldr pc, [r4] @ call processor specific code
#else
- bl cpu_data_abort
+ bl CPU_ABORT_HANDLER
#endif
msr cpsr_c, r9
mov r2, sp
.LCirq: .word __temp_irq
.LCund: .word __temp_und
.LCabt: .word __temp_abt
-#ifdef MULTI_CPU
+#ifdef MULTI_ABORT
.LCprocfns: .word SYMBOL_NAME(processor)
#endif
.LCfp: .word SYMBOL_NAME(fp_enter)
alignment_trap r7, r7, __temp_abt
zero_fp
mov r0, r2 @ remove once everyones in sync
-#ifdef MULTI_CPU
+#ifdef MULTI_ABORT
ldr r4, .LCprocfns @ pass r0, r3 to
mov lr, pc @ processor code
ldr pc, [r4] @ call processor specific code
#else
- bl cpu_data_abort
+ bl CPU_ABORT_HANDLER
#endif
set_cpsr_c r2, #MODE_SVC @ Enable interrupts
mov r2, sp
#include <linux/linkage.h>
#include <asm/assembler.h>
/*
- * Function: armv4_early_abort
+ * Function: v4_early_abort
*
* Params : r2 = address of aborted instruction
* : r3 = saved SPSR
* picture. Unfortunately, this does happen. We live with it.
*/
.align 5
-ENTRY(armv4_early_abort)
+ENTRY(v4_early_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
ldr r3, [r2] @ read aborted ARM instruction
#include <linux/linkage.h>
#include <asm/assembler.h>
/*
- * Function: armv4t_early_abort
+ * Function: v4t_early_abort
*
* Params : r2 = address of aborted instruction
* : r3 = saved SPSR
* picture. Unfortunately, this does happen. We live with it.
*/
.align 5
-ENTRY(armv4t_early_abort)
+ENTRY(v4t_early_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
tst r3, #PSR_T_BIT
#include <linux/linkage.h>
#include <asm/assembler.h>
/*
- * Function: armv5ej_early_abort
+ * Function: v5ej_early_abort
*
* Params : r2 = address of aborted instruction
* : r3 = saved SPSR
* picture. Unfortunately, this does happen. We live with it.
*/
.align 5
-ENTRY(armv5ej_early_abort)
+ENTRY(v5ej_early_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
tst r3, #PSR_J_BIT
#include <linux/linkage.h>
#include <asm/assembler.h>
/*
- * Function: armv4t_late_abort
+ * Function: v4t_late_abort
*
* Params : r2 = address of aborted instruction
* : r3 = saved SPSR
* abort here if the I-TLB and D-TLB aren't seeing the same
* picture. Unfortunately, this does happen. We live with it.
*/
-ENTRY(armv4t_late_abort)
+ENTRY(v4t_late_abort)
tst r3, #PSR_T_BIT @ check for thumb mode
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
*/
.type arm1020_processor_functions, #object
arm1020_processor_functions:
- .word armv4t_early_abort
+ .word v4t_early_abort
.word cpu_arm1020_check_bugs
.word cpu_arm1020_proc_init
.word cpu_arm1020_proc_fin
*/
.type arm720_processor_functions, #object
ENTRY(arm720_processor_functions)
- .word armv4t_late_abort
+ .word v4t_late_abort
.word cpu_arm720_check_bugs
.word cpu_arm720_proc_init
.word cpu_arm720_proc_fin
*/
.type arm920_processor_functions, #object
arm920_processor_functions:
- .word armv4t_early_abort
+ .word v4t_early_abort
.word cpu_arm920_check_bugs
.word cpu_arm920_proc_init
.word cpu_arm920_proc_fin
*/
.type arm922_processor_functions, #object
arm922_processor_functions:
- .word armv4t_early_abort
+ .word v4t_early_abort
.word cpu_arm922_check_bugs
.word cpu_arm922_proc_init
.word cpu_arm922_proc_fin
*/
.type arm926_processor_functions, #object
arm926_processor_functions:
- .word armv5ej_early_abort
+ .word v5ej_early_abort
.word cpu_arm926_check_bugs
.word cpu_arm926_proc_init
.word cpu_arm926_proc_fin
.type sa110_processor_functions, #object
ENTRY(sa110_processor_functions)
- .word armv4_early_abort
+ .word v4_early_abort
.word cpu_sa110_check_bugs
.word cpu_sa110_proc_init
.word cpu_sa110_proc_fin
.type xscale_processor_functions, #object
ENTRY(xscale_processor_functions)
- .word armv4t_early_abort
+ .word v4t_early_abort
.word cpu_xscale_check_bugs
.word cpu_xscale_proc_init
.word cpu_xscale_proc_fin
extern const struct processor arm7_processor_functions;
extern const struct processor sa110_processor_functions;
-#define cpu_data_abort(pc) processor._data_abort(pc)
#define cpu_check_bugs() processor._check_bugs()
#define cpu_proc_init() processor._proc_init()
#define cpu_proc_fin() processor._proc_fin()
* function pointers for this lot. Otherwise, we can optimise the
* table away.
*/
-#define cpu_data_abort __cpu_fn(CPU_ABRT,_abort)
#define cpu_check_bugs __cpu_fn(CPU_NAME,_check_bugs)
#define cpu_proc_init __cpu_fn(CPU_NAME,_proc_init)
#define cpu_proc_fin __cpu_fn(CPU_NAME,_proc_fin)
#endif
#define __glue(name,fn) ____glue(name,fn)
-/*
- * Select MMU TLB handling.
- */
+
/*
- * ARMv3 MMU
+ * MMU TLB Model
+ * =============
+ *
+ * We have the following to choose from:
+ * v3 - ARMv3
+ * v4 - ARMv4 without write buffer
+ * v4wb - ARMv4 with write buffer without I TLB flush entry instruction
+ * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
*/
#undef _TLB
+#undef MULTI_TLB
+
#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
# ifdef _TLB
# define MULTI_TLB 1
# endif
#endif
-/*
- * ARMv4 MMU without write buffer
- */
#if defined(CONFIG_CPU_ARM720T)
# ifdef _TLB
# define MULTI_TLB 1
# endif
#endif
-/*
- * ARMv4 MMU with write buffer, with invalidate I TLB entry instruction
- */
#if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
defined(CONFIG_CPU_ARM926T) || defined(CONFIG_CPU_ARM1020) || \
defined(CONFIG_CPU_XSCALE)
# endif
#endif
-/*
- * ARMv4 MMU with write buffer, without invalidate I TLB entry instruction
- */
#if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100)
# ifdef _TLB
# define MULTI_TLB 1
# endif
#endif
+#ifndef _TLB
+#error Unknown TLB model
+#endif
+
+
+
+/*
+ * Data Abort Model
+ * ================
+ *
+ * We have the following to choose from:
+ * arm6 - ARM6 style
+ * arm7 - ARM7 style
+ * v4_early - ARMv4 without Thumb early abort handler
+ * v4t_late - ARMv4 with Thumb late abort handler
+ * v4t_early - ARMv4 with Thumb early abort handler
+ * v5ej_early - ARMv5 with Thumb and Java early abort handler
+ */
+#undef CPU_ABORT_HANDLER
+#undef MULTI_ABORT
+
+#if defined(CONFIG_CPU_ARM610)
+# ifdef CPU_ABORT_HANDLER
+# define MULTI_ABORT 1
+# else
+# define CPU_ABORT_HANDLER cpu_arm6_data_abort
+# endif
+#endif
+
+#if defined(CONFIG_CPU_ARM710)
+# ifdef CPU_ABORT_HANDLER
+# define MULTI_ABORT 1
+# else
+# define CPU_ABORT_HANDLER cpu_arm7_data_abort
+# endif
+#endif
+
+#if defined(CONFIG_CPU_ARM720T)
+# ifdef CPU_ABORT_HANDLER
+# define MULTI_ABORT 1
+# else
+# define CPU_ABORT_HANDLER v4t_late_abort
+# endif
+#endif
+
+#if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100)
+# ifdef CPU_ABORT_HANDLER
+# define MULTI_ABORT 1
+# else
+# define CPU_ABORT_HANDLER v4_early_abort
+# endif
+#endif
+
+#if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
+ defined(CONFIG_CPU_ARM1020) || defined(CONFIG_CPU_XSCALE)
+# ifdef CPU_ABORT_HANDLER
+# define MULTI_ABORT 1
+# else
+# define CPU_ABORT_HANDLER v4t_early_abort
+# endif
+#endif
+
+#if defined(CONFIG_CPU_ARM926T)
+# ifdef CPU_ABORT_HANDLER
+# define MULTI_ABORT 1
+# else
+# define CPU_ABORT_HANDLER v5ej_early_abort
+# endif
+#endif
+
+#ifndef CPU_ABORT_HANDLER
+#error Unknown data abort handler type
+#endif
+
#endif
/*
* CPU_NAME - the prefix for CPU related functions
- * CPU_ABRT - the prefix for the CPU abort decoding function
* MMU_ARCH - the prefix for copy_user_page/clear_user_page
*/
# define MULTI_CPU
# else
# define CPU_NAME cpu_arm6
-# define CPU_ABRT cpu_arm6
# define MMU_ARCH armv3
# endif
# endif
# define MULTI_CPU
# else
# define CPU_NAME cpu_arm7
-# define CPU_ABRT cpu_arm7
# define MMU_ARCH armv3
# endif
# endif
# define MULTI_CPU
# else
# define CPU_NAME cpu_arm720
-# define CPU_ABRT armv4t_late
# define MMU_ARCH armv4
# endif
# endif
# define MULTI_CPU
# else
# define CPU_NAME cpu_arm920
-# define CPU_ABRT armv4t_early
# define MMU_ARCH armv4
# endif
# endif
# define MULTI_CPU
# else
# define CPU_NAME cpu_arm922
-# define CPU_ABRT armv4t_early
# define MMU_ARCH armv4
# endif
# endif
# define MULTI_CPU
# else
# define CPU_NAME cpu_arm926
-# define CPU_ABRT armv5ej_early
# define MMU_ARCH armv4
# endif
# endif
# define MULTI_CPU
# else
# define CPU_NAME cpu_sa110
-# define CPU_ABRT armv4_early
# define MMU_ARCH armv4
# endif
# endif
# define MULTI_CPU
# else
# define CPU_NAME cpu_sa1100
-# define CPU_ABRT armv4_early
# define MMU_ARCH armv4_mc
# endif
# endif
# define MULTI_CPU
# else
# define CPU_NAME cpu_arm1020
-# define CPU_ABRT armv4t_early
# define MMU_ARCH armv4
# endif
# endif
# define MULTI_CPU
# else
# define CPU_NAME cpu_xscale
-# define CPU_ABRT armv4t_early
# define MMU_ARCH armv5te
# endif
# endif