drm/xe/guc_ads: allocate UM queues in VRAM on dGFX

commit f342810a141f8a7e8b3786a6e4b6c0695a078a74 upstream.

On iGPU, the UM queue BO is allocated in system memory. On dGFX, the BO
was previously created in system memory and later reallocated in
xe_guc_realloc_post_hwconfig().  Allocate the UM queue BO directly in
VRAM on dGFX, where it is ultimately required.

Fixes: 9c57bc08652a ("drm/xe/lnl: Drop force_probe requirement")
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: <stable@vger.kernel.org> # v6.12+
Signed-off-by: Jia Yao <jia.yao@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patch.msgid.link/20260804165057.129529-3-jia.yao@intel.com
(cherry picked from commit f342810a141f8a7e8b3786a6e4b6c0695a078a74)
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index cc5741f751b93d2cbd9842070b326aa162e955ba..ae0c88da422b2bd2da41cbb5a865595e519d172b 100644 (file)
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -700,12 +700,6 @@ static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc)
        if (ret)
                return ret;
 
-       if (guc->ads.um_queue_bo) {
-               ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.um_queue_bo);
-               if (ret)
-                       return ret;
-       }
-
        return 0;
 }
 

diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 86e6651c0036323fa82ac31848c7adfe99341c2f..4f48356ae622b80269d1f243e7b59620dbb8e841 100644 (file)
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -392,15 +392,17 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
                /*
                 * Allocate a separate BO for the HW fault ring (UM queues).
                 *
-                * Round the size up to the next power of two so that
+                * Round the size up to the next power of two so that on iGPU
                 * (system memory, no IOMMU) the TTM pool issues a single
                 * alloc_pages(order=N) call, maximising the chance of getting
                 * a physically contiguous block.  GuC requires contiguous DPA.
                 */
-               size_t um_size = roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
+               size_t um_size = IS_DGFX(xe) ?
+                                GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX :
+                                roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
                                                    GUC_UM_HW_QUEUE_MAX);
 
-               u32 um_flags = XE_BO_FLAG_SYSTEM |
+               u32 um_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) |
                               XE_BO_FLAG_GGTT |
                               XE_BO_FLAG_GGTT_INVALIDATE |
                               XE_BO_FLAG_PINNED_NORESTORE;