--- /dev/null
+/* include/asm-arm/arch-lh7a40x/constants.h
+ *
+ * Copyright (C) 2004 Coastal Environmental Systems
+ * Copyright (C) 2004 Logic Product Development
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_CONSTANTS_H
+#define __ASM_ARCH_CONSTANTS_H
+
+#include <linux/config.h>
+
+/* Addressing constants */
+
+ /* SoC CPU IO addressing */
+#define IO_PHYS (0x80000000)
+#define IO_VIRT (0xf8000000)
+#define IO_SIZE (0x0000B000)
+
+#ifdef CONFIG_MACH_KEV7A400
+# define CPLD_PHYS (0x20000000)
+# define CPLD_VIRT (0xf2000000)
+# define CPLD_SIZE PAGE_SIZE
+#endif
+
+#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
+
+# define IOBARRIER_PHYS 0xc0000000 /* Start of SDRAM */
+/*# define IOBARRIER_PHYS 0x00000000 */ /* Start of flash */
+# define IOBARRIER_VIRT 0xf0000000
+# define IOBARRIER_SIZE PAGE_SIZE
+
+# define CF_PHYS 0x60200000
+# define CF_VIRT 0xf6020000
+# define CF_SIZE (8*1024)
+
+ /* The IO mappings for the LPD CPLD are, unfortunately, sparse. */
+# define CPLDX_PHYS(x) (0x70000000 | ((x) << 20))
+# define CPLDX_VIRT(x) (0xf7000000 | ((x) << 16))
+# define CPLD00_PHYS CPLDX_PHYS (0x00) /* Wired LAN */
+# define CPLD00_VIRT CPLDX_VIRT (0x00)
+# define CPLD00_SIZE PAGE_SIZE
+# define CPLD02_PHYS CPLDX_PHYS (0x02)
+# define CPLD02_VIRT CPLDX_VIRT (0x02)
+# define CPLD02_SIZE PAGE_SIZE
+# define CPLD06_PHYS CPLDX_PHYS (0x06)
+# define CPLD06_VIRT CPLDX_VIRT (0x06)
+# define CPLD06_SIZE PAGE_SIZE
+# define CPLD08_PHYS CPLDX_PHYS (0x08)
+# define CPLD08_VIRT CPLDX_VIRT (0x08)
+# define CPLD08_SIZE PAGE_SIZE
+# define CPLD0C_PHYS CPLDX_PHYS (0x0c)
+# define CPLD0C_VIRT CPLDX_VIRT (0x0c)
+# define CPLD0C_SIZE PAGE_SIZE
+# define CPLD0E_PHYS CPLDX_PHYS (0x0e)
+# define CPLD0E_VIRT CPLDX_VIRT (0x0e)
+# define CPLD0E_SIZE PAGE_SIZE
+# define CPLD10_PHYS CPLDX_PHYS (0x10)
+# define CPLD10_VIRT CPLDX_VIRT (0x10)
+# define CPLD10_SIZE PAGE_SIZE
+# define CPLD12_PHYS CPLDX_PHYS (0x12)
+# define CPLD12_VIRT CPLDX_VIRT (0x12)
+# define CPLD12_SIZE PAGE_SIZE
+# define CPLD14_PHYS CPLDX_PHYS (0x14)
+# define CPLD14_VIRT CPLDX_VIRT (0x14)
+# define CPLD14_SIZE PAGE_SIZE
+# define CPLD16_PHYS CPLDX_PHYS (0x16)
+# define CPLD16_VIRT CPLDX_VIRT (0x16)
+# define CPLD16_SIZE PAGE_SIZE
+# define CPLD18_PHYS CPLDX_PHYS (0x18)
+# define CPLD18_VIRT CPLDX_VIRT (0x18)
+# define CPLD18_SIZE PAGE_SIZE
+# define CPLD1A_PHYS CPLDX_PHYS (0x1a)
+# define CPLD1A_VIRT CPLDX_VIRT (0x1a)
+# define CPLD1A_SIZE PAGE_SIZE
+#endif
+
+ /* Timing constants */
+
+#define XTAL_IN 14745600 /* 14.7456 MHz crystal */
+#define PLL_CLOCK (XTAL_IN * 21) /* 309 MHz PLL clock */
+#define MAX_HCLK_KHZ 100000 /* HCLK max limit ~100MHz */
+
+#endif /* __ASM_ARCH_CONSTANTS_H */
--- /dev/null
+/* include/asm-arm/arch-lh7a40x/dma.h
+ *
+ * Copyright (C) 2003 Coastal Environmental Systems
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#define MAX_DMA_ADDRESS 0xffffffff
+#define MAX_DMA_CHANNELS 0 /* All DMA is internal to CPU */
+
+#endif /* _ASM_ARCH_DMA_H */
--- /dev/null
+/* include/asm-arm/arch-lh7a40x/hardware.h
+ *
+ * Copyright (C) 2004 Coastal Environmental Systems
+ *
+ * [ Substantially cribbed from include/asm-arm/arch-pxa/hardware.h ]
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/mach-types.h>
+
+#define io_p2v(x) (0xf0000000 | (((x) & 0xfff00000) >> 4) | ((x) & 0x0000ffff))
+#define io_v2p(x) ( (((x) & 0x0fff0000) << 4) | ((x) & 0x0000ffff))
+
+#ifdef __ASSEMBLY__
+
+# define __REG(x) io_p2v(x)
+# define __PREG(x) io_v2p(x)
+
+#else
+
+# if 0
+# define __REG(x) (*((volatile u32 *)io_p2v(x)))
+# else
+/*
+ * This __REG() version gives the same results as the one above, except
+ * that we are fooling gcc somehow so it generates far better and smaller
+ * assembly code for access to contigous registers. It's a shame that gcc
+ * doesn't guess this by itself.
+ */
+#include <asm/types.h>
+typedef struct { volatile u32 offset[4096]; } __regbase;
+# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
+# define __REG(x) __REGP(io_p2v(x))
+typedef struct { volatile u16 offset[4096]; } __regbase16;
+# define __REGP16(x) ((__regbase16 *)((x)&~4095))->offset[((x)&4095)>>2]
+# define __REG16(x) __REGP16(io_p2v(x))
+typedef struct { volatile u8 offset[4096]; } __regbase8;
+# define __REGP8(x) ((__regbase8 *)((x)&~4095))->offset[((x)&4095)>>2]
+# define __REG8(x) __REGP8(io_p2v(x))
+#endif
+
+/* Let's kick gcc's ass again... */
+# define __REG2(x,y) \
+ ( __builtin_constant_p(y) ? (__REG((x) + (y))) \
+ : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
+
+# define __PREG(x) (io_v2p((u32)&(x)))
+
+#endif
+
+#include "registers.h"
+
+#endif /* _ASM_ARCH_HARDWARE_H */
--- /dev/null
+/* include/asm-arm/arch-lh7a40x/ide.h
+ *
+ * Copyright (C) 2004 Logic Product Development
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_IDE_H
+#define __ASM_ARCH_IDE_H
+
+#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
+
+/* This implementation of ide.h only applies to the LPD CardEngines.
+ * Thankfully, there is less to do for the KEV.
+ */
+
+#include <linux/config.h>
+#include <asm/irq.h>
+#include <asm/hardware.h>
+#include <asm/arch/registers.h>
+
+#define IDE_REG_LINE (1<<12) /* A12 drives !REG */
+#define IDE_ALT_LINE (1<<11) /* Unused A11 allows non-overlapping regions */
+#define IDE_CONTROLREG_OFFSET (0xe)
+
+void lpd7a40x_hwif_ioops (struct hwif_s* hwif);
+
+static __inline__ void ide_init_hwif_ports (hw_regs_t *hw, int data_port,
+ int ctrl_port, int *irq)
+{
+ ide_ioreg_t reg;
+ int i;
+ int regincr = 1;
+
+ memset (hw, 0, sizeof (*hw));
+
+ reg = (ide_ioreg_t) data_port;
+
+ for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
+ hw->io_ports[i] = reg;
+ reg += regincr;
+ }
+
+ hw->io_ports[IDE_CONTROL_OFFSET] = (ide_ioreg_t) ctrl_port;
+
+ if (irq)
+ *irq = IDE_NO_IRQ;
+}
+
+static __inline__ void ide_init_default_hwifs (void)
+{
+ hw_regs_t hw;
+ struct hwif_s* hwif;
+
+ ide_init_hwif_ports (&hw,
+ CF_VIRT + IDE_REG_LINE,
+ CF_VIRT + IDE_REG_LINE + IDE_ALT_LINE
+ + IDE_CONTROLREG_OFFSET,
+ NULL);
+
+ ide_register_hw (&hw, &hwif);
+ lpd7a40x_hwif_ioops (hwif); /* Override IO routines */
+}
+
+#else
+
+static __inline__ void ide_init_hwif_ports (hw_regs_t *hw, int data_port,
+ int ctrl_port, int *irq) {}
+static __inline__ void ide_init_default_hwifs (void) {}
+
+#endif
+
+#endif
--- /dev/null
+/* include/asm-arm/arch-lh7a40x/io.h
+ *
+ * Copyright (C) 2004 Coastal Environmental Systems
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/* No ISA or PCI bus on this machine. */
+#define __io(a) (a)
+#define __mem_pci(a) ((unsigned long)(a))
+#define __mem_isa(a) ((unsigned long)(a))
+
+#endif /* __ASM_ARCH_IO_H */
--- /dev/null
+/* include/asm-arm/arch-lh7a40x/irq.h
+ *
+ * Copyright (C) 2004 Logic Product Development
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+void __init lh7a40x_init_board_irq (void);
--- /dev/null
+/* include/asm-arm/arch-lh7a40x/irqs.h
+ *
+ * Copyright (C) 2004 Coastal Environmental Systems
+ * Copyright (C) 2004 Logic Product Development
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+/* It is to be seen whether or not we can build a kernel for more than
+ * one board. For the time being, these macros assume that we cannot.
+ * Thus, it is OK to ifdef machine/board specific IRQ assignments.
+ */
+
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#include <linux/config.h>
+
+#define FIQ_START 80
+
+#if defined (CONFIG_ARCH_LH7A400)
+
+ /* FIQs */
+
+# define IRQ_GPIO0FIQ 0 /* GPIO External FIQ Interrupt on F0 */
+# define IRQ_BLINT 1 /* Battery Low */
+# define IRQ_WEINT 2 /* Watchdog Timer, WDT overflow */
+# define IRQ_MCINT 3 /* Media Change, MEDCHG pin rising */
+
+ /* IRQs */
+
+# define IRQ_CSINT 4 /* Audio Codec (ACI) */
+# define IRQ_GPIO1INTR 5 /* GPIO External IRQ Interrupt on F1 */
+# define IRQ_GPIO2INTR 6 /* GPIO External IRQ Interrupt on F2 */
+# define IRQ_GPIO3INTR 7 /* GPIO External IRQ Interrupt on F3 */
+# define IRQ_T1UI 8 /* Timer 1 underflow */
+# define IRQ_T2UI 9 /* Timer 2 underflow */
+# define IRQ_RTCMI 10
+# define IRQ_TINTR 11 /* Clock State Controller 64 Hz tick (CSC) */
+# define IRQ_UART1INTR 12
+# define IRQ_UART2INTR 13
+# define IRQ_LCDINTR 14
+# define IRQ_SSIEOT 15 /* Synchronous Serial Interface (SSI) */
+# define IRQ_UART3INTR 16
+# define IRQ_SCIINTR 17 /* Smart Card Interface (SCI) */
+# define IRQ_AACINTR 18 /* Advanced Audio Codec (AAC) */
+# define IRQ_MMCINTR 19 /* Multimedia Card (MMC) */
+# define IRQ_USBINTR 20
+# define IRQ_DMAINTR 21
+# define IRQ_T3UI 22 /* Timer 3 underflow */
+# define IRQ_GPIO4INTR 23 /* GPIO External IRQ Interrupt on F4 */
+# define IRQ_GPIO5INTR 24 /* GPIO External IRQ Interrupt on F5 */
+# define IRQ_GPIO6INTR 25 /* GPIO External IRQ Interrupt on F6 */
+# define IRQ_GPIO7INTR 26 /* GPIO External IRQ Interrupt on F7 */
+# define IRQ_BMIINTR 27 /* Battery Monitor Interface (BMI) */
+
+# define NR_IRQ_CPU 28 /* IRQs directly recognized by CPU */
+
+ /* Given IRQ, return GPIO interrupt number 0-7 */
+# define IRQ_TO_GPIO(i) ((i) \
+ - (((i) > IRQ_GPIO3INTR) ? IRQ_GPIO4INTR - IRQ_GPIO3INTR - 1 : 0)\
+ - (((i) > IRQ_GPIO0INTR) ? IRQ_GPIO1INTR - IRQ_GPIO0INTR - 1 : 0))
+
+#endif
+
+#if defined (CONFIG_ARCH_LH7A404)
+
+# define IRQ_BROWN 0 /* Brownout */
+# define IRQ_WDTINTR 1 /* Watchdog Timer */
+# define IRQ_COMMRX 2 /* ARM Comm Rx for Debug */
+# define IRQ_COMMTX 3 /* ARM Comm Tx for Debug */
+# define IRQ_T1UI 4 /* Timer 1 underflow */
+# define IRQ_T2UI 5 /* Timer 2 underflow */
+# define IRQ_CSINT 6 /* Codec Interrupt (shared by AAC on 404) */
+# define IRQ_DMAM2P0 7 /* -- DMA Memory to Peripheral */
+# define IRQ_DMAM2P1 8
+# define IRQ_DMAM2P2 9
+# define IRQ_DMAM2P3 10
+# define IRQ_DMAM2P4 11
+# define IRQ_DMAM2P5 12
+# define IRQ_DMAM2P6 13
+# define IRQ_DMAM2P7 14
+# define IRQ_DMAM2P8 15
+# define IRQ_DMAM2P9 16
+# define IRQ_DMAM2M0 17 /* -- DMA Memory to Memory */
+# define IRQ_DMAM2M1 18
+# define IRQ_GPIO0INTR 19 /* -- GPIOF Interrupt */
+# define IRQ_GPIO1INTR 20
+# define IRQ_GPIO2INTR 21
+# define IRQ_GPIO3INTR 22
+# define IRQ_SOFT_V1_23 23 /* -- Unassigned */
+# define IRQ_SOFT_V1_24 24
+# define IRQ_SOFT_V1_25 25
+# define IRQ_SOFT_V1_26 26
+# define IRQ_SOFT_V1_27 27
+# define IRQ_SOFT_V1_28 28
+# define IRQ_SOFT_V1_29 29
+# define IRQ_SOFT_V1_30 30
+# define IRQ_SOFT_V1_31 31
+
+# define IRQ_BLINT 32 /* Battery Low */
+# define IRQ_BMIINTR 33 /* Battery Monitor */
+# define IRQ_MCINTR 34 /* Media Change */
+# define IRQ_TINTR 35 /* 64Hz Tick */
+# define IRQ_WEINT 36 /* Watchdog Expired */
+# define IRQ_RTCMI 37 /* Real-time Clock Match */
+# define IRQ_UART1INTR 38 /* UART1 Interrupt (including error) */
+# define IRQ_UART1ERR 39 /* UART1 Error */
+# define IRQ_UART2INTR 40 /* UART2 Interrupt (including error) */
+# define IRQ_UART2ERR 41 /* UART2 Error */
+# define IRQ_UART3INTR 42 /* UART3 Interrupt (including error) */
+# define IRQ_UART3ERR 43 /* UART3 Error */
+# define IRQ_SCIINTR 44 /* Smart Card */
+# define IRQ_TSCINTR 45 /* Touchscreen */
+# define IRQ_KMIINTR 46 /* Keyboard/Mouse (PS/2) */
+# define IRQ_GPIO4INTR 47 /* -- GPIOF Interrupt */
+# define IRQ_GPIO5INTR 48
+# define IRQ_GPIO6INTR 49
+# define IRQ_GPIO7INTR 50
+# define IRQ_T3UI 51 /* Timer 3 underflow */
+# define IRQ_LCDINTR 52 /* LCD Controller */
+# define IRQ_SSPINTR 53 /* Synchronous Serial Port */
+# define IRQ_SDINTR 54 /* Secure Digital Port (MMC) */
+# define IRQ_USBINTR 55 /* USB Device Port */
+# define IRQ_USHINTR 56 /* USB Host Port */
+# define IRQ_SOFT_V2_25 57 /* -- Unassigned */
+# define IRQ_SOFT_V2_26 58
+# define IRQ_SOFT_V2_27 59
+# define IRQ_SOFT_V2_28 60
+# define IRQ_SOFT_V2_29 61
+# define IRQ_SOFT_V2_30 62
+# define IRQ_SOFT_V2_31 63
+
+# define NR_IRQ_CPU 64 /* IRQs directly recognized by CPU */
+
+ /* Given IRQ, return GPIO interrupt number 0-7 */
+# define IRQ_TO_GPIO(i) ((i) \
+ - (((i) > IRQ_GPIO3INTR) ? IRQ_GPIO4INTR - IRQ_GPIO3INTR - 1 : 0)\
+ - IRQ_GPIO0INTR)
+
+ /* Vector Address constants */
+# define VA_VECTORED 0x100 /* Set for vectored interrupt */
+# define VA_VIC1DEFAULT 0x200 /* Set as default VECTADDR for VIC1 */
+# define VA_VIC2DEFAULT 0x400 /* Set as default VECTADDR for VIC2 */
+
+#endif
+
+ /* IRQ aliases */
+
+#if !defined (IRQ_GPIO0INTR)
+# define IRQ_GPIO0INTR IRQ_GPIO0FIQ
+#endif
+#define IRQ_TICK IRQ_TINTR
+#define IRQ_PCC1_RDY IRQ_GPIO6INTR /* PCCard 1 ready */
+#define IRQ_PCC2_RDY IRQ_GPIO7INTR /* PCCard 2 ready */
+
+#ifdef CONFIG_MACH_KEV7A400
+# define IRQ_TS IRQ_GPIOFIQ /* Touchscreen */
+# define IRQ_CPLD IRQ_GPIO1INTR /* CPLD cascade */
+# define IRQ_PCC1_CD IRQ_GPIO_F2 /* PCCard 1 card detect */
+# define IRQ_PCC2_CD IRQ_GPIO_F3 /* PCCard 2 card detect */
+#endif
+
+#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
+# define IRQ_CPLD_V28 IRQ_GPIO7INTR /* CPLD cascade through GPIO_PF7 */
+# define IRQ_CPLD_V34 IRQ_GPIO3INTR /* CPLD cascade through GPIO_PF3 */
+#endif
+
+ /* System specific IRQs */
+
+#define IRQ_BOARD_START NR_IRQ_CPU
+
+#ifdef CONFIG_MACH_KEV7A400
+# define IRQ_KEV7A400_CPLD IRQ_BOARD_START
+# define NR_IRQ_BOARD 5
+# define IRQ_KEV7A400_MMC_CD IRQ_KEV7A400_CPLD + 0 /* MMC Card Detect */
+# define IRQ_KEV7A400_RI2 IRQ_KEV7A400_CPLD + 1 /* Ring Indicator 2 */
+# define IRQ_KEV7A400_IDE_CF IRQ_KEV7A400_CPLD + 2 /* Compact Flash (?) */
+# define IRQ_KEV7A400_ETH_INT IRQ_KEV7A400_CPLD + 3 /* Ethernet chip */
+# define IRQ_KEV7A400_INT IRQ_KEV7A400_CPLD + 4
+#endif
+
+#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
+# define IRQ_LPD7A40X_CPLD IRQ_BOARD_START
+# define NR_IRQ_BOARD 2
+# define IRQ_LPD7A40X_ETH_INT IRQ_LPD7A40X_CPLD + 0 /* Ethernet chip */
+# define IRQ_LPD7A400_TS IRQ_LPD7A40X_CPLD + 1 /* Touch screen */
+#endif
+
+#define NR_IRQS (NR_IRQ_CPU + NR_IRQ_BOARD)
+
+#endif
--- /dev/null
+/* include/asm-arm/arch-lh7a40x/memory.h
+ *
+ * Copyright (C) 2004 Coastal Environmental Systems
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+
+#define BANKS_PER_NODE 1 /* Define as either 1 or 2 */
+
+/*
+ * Task size: 3GB
+ */
+#define TASK_SIZE (0xbf000000UL) /* 0xc0000000? */
+#define TASK_SIZE_26 (0x04000000UL)
+
+/*
+ * This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE (0x40000000)
+
+/*
+ * Page offset: 3GB
+ */
+#define PAGE_OFFSET (0xc0000000UL)
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET (0xc0000000UL)
+
+/*
+ * physical vs virtual ram conversion
+ */
+#define __virt_to_phys__is_a_macro
+#define __phys_to_virt__is_a_macro
+#define __virt_to_phys(x) ((x) - PAGE_OFFSET + PHYS_OFFSET)
+#define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ * address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ * to an address that the kernel can use.
+ */
+#define __virt_to_bus__is_a_macro
+#define __bus_to_virt__is_a_macro
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#ifdef CONFIG_DISCONTIGMEM
+/*
+ * Because of the wide memory address space between physical RAM
+ * banks, it's convenient to use Linux's NUMA support to represent our
+ * memory map. Assuming all memory nodes have equal access
+ * characteristics, we then have a generic discontiguous memory setup.
+ *
+ * Of course, all this isn't mandatory for implementations with only
+ * one used memory bank. For those, simply undefine
+ * CONFIG_DISCONTIGMEM. However, keep in mind that a featurefull
+ * system will need more than 4MiB of RAM.
+ *
+ * The contiguous memory blocks are small enough that it pays to
+ * aggregate two banks into one node. Setting BANKS_PER_NODE to 2
+ * puts pairs of banks into a node.
+ *
+ * A typical layout would start like this:
+ *
+ * node 0: 0xc0000000
+ * 0xc1000000
+ * node 1: 0xc4000000
+ * 0xc5000000
+ * node 2: 0xc8000000
+ * 0xc9000000
+ *
+ * The proximity of the pairs of blocks makes it feasible to combine them.
+ *
+ */
+
+/*
+ * Given a kernel address, find the home node of the underlying memory.
+ */
+
+#if BANKS_PER_NODE==1
+#define KVADDR_TO_NID(addr) \
+ ( ((((unsigned long) (addr) - PAGE_OFFSET) >> 24) & 1)\
+ | ((((unsigned long) (addr) - PAGE_OFFSET) >> 25) & ~1))
+#else /* 2 banks per node */
+#define KVADDR_TO_NID(addr) \
+ ((unsigned long) (addr) - PAGE_OFFSET) >> 26)
+#endif
+
+/*
+ * Given a page frame number, convert it to a node id.
+ */
+
+#if BANKS_PER_NODE==1
+#define PFN_TO_NID(pfn) \
+ (((((pfn) - PHYS_PFN_OFFSET) >> (24 - PAGE_SHIFT)) & 1)\
+ | ((((pfn) - PHYS_PFN_OFFSET) >> (25 - PAGE_SHIFT)) & ~1))
+#else /* 2 banks per node */
+#define PFN_TO_NID(addr) \
+ (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT))
+#endif
+
+/*
+ * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
+ * and return the mem_map of that node.
+ */
+#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
+
+/*
+ * Given a page frame number, find the owning node of the memory
+ * and return the mem_map of that node.
+ */
+#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
+
+/*
+ * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
+ * and returns the index corresponding to the appropriate page in the
+ * node's mem_map.
+ */
+
+#if BANKS_PER_NODE==1
+#define LOCAL_MAP_NR(addr) \
+ (((unsigned long)(addr) & 0x003fffff) >> PAGE_SHIFT)
+#else /* 2 banks per node */
+#define LOCAL_MAP_NR(addr) \
+ (((unsigned long)(addr) & 0x01ffffff) >> PAGE_SHIFT)
+#endif
+
+#else
+
+#define PFN_TO_NID(addr) (0)
+
+#endif
+
+#endif
--- /dev/null
+/* include/asm-arm/arch-lh7a40x/param.h
+ *
+ * Copyright (C) 2004 Coastal Environmental Systems
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
--- /dev/null
+/* include/asm-arm/arch-lh7a40x/registers.h
+ *
+ * Copyright (C) 2004 Coastal Environmental Systems
+ * Copyright (C) 2004 Logic Product Development
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/config.h>
+#include <asm/arch/constants.h>
+
+#ifndef __ASM_ARCH_REGISTERS_H
+#define __ASM_ARCH_REGISTERS_H
+
+
+ /* Physical register base addresses */
+
+#define AC97_PHYS (0x80000000) /* AC97 Controller */
+#define MMC_PHYS (0x80000100) /* Multimedia Card Controller */
+#define USB_PHYS (0x80000200) /* USB Client */
+#define SCI_PHYS (0x80000300) /* Secure Card Interface */
+#define CSC_PHYS (0x80000400) /* Clock/State Controller */
+#define INTC_PHYS (0x80000500) /* Interrupt Controller */
+#define UART1_PHYS (0x80000600) /* UART1 Controller */
+#define SIR_PHYS (0x80000600) /* IR Controller, same are UART1 */
+#define UART2_PHYS (0x80000700) /* UART2 Controller */
+#define UART3_PHYS (0x80000800) /* UART3 Controller */
+#define DCDC_PHYS (0x80000900) /* DC to DC Controller */
+#define ACI_PHYS (0x80000a00) /* Audio Codec Interface */
+#define SSP_PHYS (0x80000b00) /* Synchronous ... */
+#define TIMER_PHYS (0x80000c00) /* Timer Controller */
+#define RTC_PHYS (0x80000d00) /* Real-time Clock */
+#define GPIO_PHYS (0x80000e00) /* General Purpose IO */
+#define BMI_PHYS (0x80000f00) /* Battery Monitor Interface */
+#define WDT_PHYS (0x80001400) /* Watchdog Timer */
+#define SMC_PHYS (0x80002000) /* Static Memory Controller */
+#define SDRC_PHYS (0x80002400) /* SDRAM Controller */
+#define DMAC_PHYS (0x80002800) /* DMA Controller */
+#define CLCDC_PHYS (0x80003000) /* Color LCD Controller */
+
+ /* Physical registers of the LH7A404 */
+
+#define VIC1_PHYS (0x80008000) /* Vectored Interrupt Controller 1 */
+#define USBH_PHYS (0x80009000) /* USB OHCI host controller */
+#define VIC2_PHYS (0x8000a000) /* Vectored Interrupt Controller 2 */
+
+/*#define KBD_PHYS (0x80000e00) */
+/*#define LCDICP_PHYS (0x80001000) */
+
+
+ /* Clock/State Controller register */
+
+#define CSC_PWRCNT __REG(CSC_PHYS + 0x04) /* Power control */
+
+#define CSC_PWRCNT_USBH_EN (1<<28) /* USB Host power enable */
+
+
+ /* Interrupt Controller registers */
+
+#define INTC_INTSR __REG(INTC_PHYS + 0x00) /* Status */
+#define INTC_INTRSR __REG(INTC_PHYS + 0x04) /* Raw Status */
+#define INTC_INTENS __REG(INTC_PHYS + 0x08) /* Enable Set */
+#define INTC_INTENC __REG(INTC_PHYS + 0x0c) /* Enable Clear */
+
+
+ /* Vectored Interrupted Controller registers */
+
+#define VIC1_IRQSTATUS __REG(VIC1_PHYS + 0x00)
+#define VIC1_FIQSTATUS __REG(VIC1_PHYS + 0x04)
+#define VIC1_RAWINTR __REG(VIC1_PHYS + 0x08)
+#define VIC1_INTSEL __REG(VIC1_PHYS + 0x0c)
+#define VIC1_INTEN __REG(VIC1_PHYS + 0x10)
+#define VIC1_INTENCLR __REG(VIC1_PHYS + 0x14)
+#define VIC1_SOFTINT __REG(VIC1_PHYS + 0x18)
+#define VIC1_SOFTINTCLR __REG(VIC1_PHYS + 0x1c)
+#define VIC1_PROTECT __REG(VIC1_PHYS + 0x20)
+#define VIC1_VECTADDR __REG(VIC1_PHYS + 0x30)
+#define VIC1_NVADDR __REG(VIC1_PHYS + 0x34)
+#define VIC1_VAD0 __REG(VIC1_PHYS + 0x100)
+#define VIC1_VECTCNTL0 __REG(VIC1_PHYS + 0x200)
+#define VIC2_IRQSTATUS __REG(VIC2_PHYS + 0x00)
+#define VIC2_FIQSTATUS __REG(VIC2_PHYS + 0x04)
+#define VIC2_RAWINTR __REG(VIC2_PHYS + 0x08)
+#define VIC2_INTSEL __REG(VIC2_PHYS + 0x0c)
+#define VIC2_INTEN __REG(VIC2_PHYS + 0x10)
+#define VIC2_INTENCLR __REG(VIC2_PHYS + 0x14)
+#define VIC2_SOFTINT __REG(VIC2_PHYS + 0x18)
+#define VIC2_SOFTINTCLR __REG(VIC2_PHYS + 0x1c)
+#define VIC2_PROTECT __REG(VIC2_PHYS + 0x20)
+#define VIC2_VECTADDR __REG(VIC2_PHYS + 0x30)
+#define VIC2_NVADDR __REG(VIC2_PHYS + 0x34)
+#define VIC2_VAD0 __REG(VIC2_PHYS + 0x100)
+#define VIC2_VECTCNTL0 __REG(VIC2_PHYS + 0x200)
+
+#define VIC_CNTL_ENABLE (0x20)
+
+ /* USB Host registers (Open HCI compatible) */
+
+#define USBH_CMDSTATUS __REG(USBH_PHYS + 0x08)
+
+
+ /* GPIO registers */
+
+#define GPIO_INTTYPE1 __REG(GPIO_PHYS + 0x4c) /* Interrupt Type 1 (Edge) */
+#define GPIO_INTTYPE2 __REG(GPIO_PHYS + 0x50) /* Interrupt Type 2 */
+#define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */
+#define GPIO_GPIOINTEN __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */
+#define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */
+
+
+ /* Static Memory Controller registers */
+
+#define SMC_BCR0 __REG(SMC_PHYS + 0x00) /* Bank 0 Configuration */
+#define SMC_BCR1 __REG(SMC_PHYS + 0x04) /* Bank 1 Configuration */
+#define SMC_BCR2 __REG(SMC_PHYS + 0x08) /* Bank 2 Configuration */
+#define SMC_BCR3 __REG(SMC_PHYS + 0x0C) /* Bank 3 Configuration */
+#define SMC_BCR6 __REG(SMC_PHYS + 0x18) /* Bank 6 Configuration */
+#define SMC_BCR7 __REG(SMC_PHYS + 0x1c) /* Bank 7 Configuration */
+
+
+#ifdef CONFIG_MACH_KEV7A400
+# define CPLD_RD_OPT_DIP_SW __REG16(CPLD_PHYS + 0x00) /* Read Option SW */
+# define CPLD_WR_IO_BRD_CTL __REG16(CPLD_PHYS + 0x00) /* Write Control */
+# define CPLD_RD_PB_KEYS __REG16(CPLD_PHYS + 0x02) /* Read Btn Keys */
+# define CPLD_LATCHED_INTS __REG16(CPLD_PHYS + 0x04) /* Read INTR stat. */
+# define CPLD_CL_INT __REG16(CPLD_PHYS + 0x04) /* Clear INTR stat */
+# define CPLD_BOOT_MMC_STATUS __REG16(CPLD_PHYS + 0x06) /* R/O */
+# define CPLD_RD_KPD_ROW_SENSE __REG16(CPLD_PHYS + 0x08)
+# define CPLD_WR_PB_INT_MASK __REG16(CPLD_PHYS + 0x08)
+# define CPLD_RD_BRD_DISP_SW __REG16(CPLD_PHYS + 0x0a)
+# define CPLD_WR_EXT_INT_MASK __REG16(CPLD_PHYS + 0x0a)
+# define CPLD_LCD_PWR_CNTL __REG16(CPLD_PHYS + 0x0c)
+# define CPLD_SEVEN_SEG __REG16(CPLD_PHYS + 0x0e) /* 7 seg. LED mask */
+
+#endif
+
+#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
+# define CPLD_CONTROL __REG8(CPLD02_PHYS)
+# define CPLD_SPI_DATA __REG8(CPLD06_PHYS)
+# define CPLD_SPI_CONTROL __REG8(CPLD08_PHYS)
+# define CPLD_SPI_EEPROM __REG8(CPLD0A_PHYS)
+# define CPLD_INTERRUPTS __REG8(CPLD0C_PHYS) /* IRQ mask/status */
+# define CPLD_BOOT_MODE __REG8(CPLD0E_PHYS)
+# define CPLD_FLASH __REG8(CPLD10_PHYS)
+# define CPLD_POWER_MGMT __REG8(CPLD12_PHYS)
+# define CPLD_REVISION __REG8(CPLD14_PHYS)
+# define CPLD_GPIO_EXT __REG8(CPLD16_PHYS)
+# define CPLD_GPIO_DATA __REG8(CPLD18_PHYS)
+# define CPLD_GPIO_DIR __REG8(CPLD1A_PHYS)
+#endif
+
+
+ /* Timer registers */
+
+#define TIMER_LOAD1 __REG(TIMER_PHYS + 0x00) /* Timer 1 initial value */
+#define TIMER_VALUE1 __REG(TIMER_PHYS + 0x04) /* Timer 1 current value */
+#define TIMER_CONTROL1 __REG(TIMER_PHYS + 0x08) /* Timer 1 control word */
+#define TIMER_EOI1 __REG(TIMER_PHYS + 0x0c) /* Timer 1 interrupt clear */
+
+#define TIMER_LOAD2 __REG(TIMER_PHYS + 0x20) /* Timer 2 initial value */
+#define TIMER_VALUE2 __REG(TIMER_PHYS + 0x24) /* Timer 2 current value */
+#define TIMER_CONTROL2 __REG(TIMER_PHYS + 0x28) /* Timer 2 control word */
+#define TIMER_EOI2 __REG(TIMER_PHYS + 0x2c) /* Timer 2 interrupt clear */
+
+#define TIMER_BUZZCON __REG(TIMER_PHYS + 0x40) /* Buzzer configuration */
+
+#define TIMER_LOAD3 __REG(TIMER_PHYS + 0x80) /* Timer 3 initial value */
+#define TIMER_VALUE3 __REG(TIMER_PHYS + 0x84) /* Timer 3 current value */
+#define TIMER_CONTROL3 __REG(TIMER_PHYS + 0x88) /* Timer 3 control word */
+#define TIMER_EOI3 __REG(TIMER_PHYS + 0x8c) /* Timer 3 interrupt clear */
+
+#define TIMER_C_ENABLE (1<<7)
+#define TIMER_C_PERIODIC (1<<6)
+#define TIMER_C_FREERUNNING (0)
+#define TIMER_C_2KHZ (0x00) /* 1.986 kHz */
+#define TIMER_C_508KHZ (0x08)
+
+ /* GPIO registers */
+
+#define GPIO_PFDD __REG(GPIO_PHYS + 0x34) /* PF direction */
+#define GPIO_INTTYPE1 __REG(GPIO_PHYS + 0x4c) /* IRQ edge or lvl */
+#define GPIO_INTTYPE2 __REG(GPIO_PHYS + 0x50) /* IRQ activ hi/lo */
+#define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIOF end of IRQ */
+#define GPIO_GPIOFINTEN __REG(GPIO_PHYS + 0x58) /* GPIOF IRQ enable */
+#define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIOF IRQ latch */
+#define GPIO_RAWINTSTATUS __REG(GPIO_PHYS + 0x60) /* GPIOF IRQ raw */
+
+
+#endif /* _ASM_ARCH_REGISTERS_H */
+
--- /dev/null
+/* include/asm-arm/arch-lh7a40x/serial.h
+ *
+ * Copyright (C) 2004 Coastal Environmental Systems
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_SERIAL_H
+#define __ASM_ARCH_SERIAL_H
+
+#include <asm/arch/registers.h>
+
+#define UART_R_DATA (0x00)
+#define UART_R_FCON (0x04)
+#define UART_R_BRCON (0x08)
+#define UART_R_CON (0x0c)
+#define UART_R_STATUS (0x10)
+#define UART_R_RAWISR (0x14)
+#define UART_R_INTEN (0x18)
+#define UART_R_ISR (0x1c)
+
+#endif /* _ASM_ARCH_SERIAL_H */
--- /dev/null
+/* include/asm-arm/arch-lh7a40x/system.h
+ *
+ * Copyright (C) 2004 Coastal Environmental Systems
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+static inline void arch_idle(void)
+{
+ cpu_do_idle ();
+}
+
+static inline void arch_reset(char mode)
+{
+ cpu_reset (0);
+}
--- /dev/null
+/* include/asm-arm/arch-lh7a40x/time.h
+ *
+ * Copyright (C) 2004 Logic Product Development
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#if HZ < 100
+# define TIMER_CONTROL TIMER_CONTROL1
+# define TIMER_LOAD TIMER_LOAD1
+# define TIMER_CONSTANT (508469/HZ)
+# define TIMER_MODE (TIMER_C_ENABLE | TIMER_C_PERIODIC | TIMER_C_508KHZ)
+# define TIMER_EOI TIMER_EOI1
+# define TIMER_IRQ IRQ_T1UI
+#else
+# define TIMER_CONTROL TIMER_CONTROL3
+# define TIMER_LOAD TIMER_LOAD3
+# define TIMER_CONSTANT (3686400/HZ)
+# define TIMER_MODE (TIMER_C_ENABLE | TIMER_C_PERIODIC)
+# define TIMER_EOI TIMER_EOI3
+# define TIMER_IRQ IRQ_T3UI
+#endif
+
+static irqreturn_t
+lh7a40x_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+ TIMER_EOI = 0;
+ do_profile (regs);
+ do_leds();
+ do_set_rtc();
+ do_timer (regs);
+
+ return IRQ_HANDLED;
+}
+
+void __init time_init(void)
+{
+ /* Stop/disable all timers */
+ TIMER_CONTROL1 = 0;
+ TIMER_CONTROL2 = 0;
+ TIMER_CONTROL3 = 0;
+
+ timer_irq.handler = lh7a40x_timer_interrupt;
+ timer_irq.flags |= SA_INTERRUPT;
+ setup_irq (TIMER_IRQ, &timer_irq);
+
+ TIMER_LOAD = TIMER_CONSTANT;
+ TIMER_CONTROL = TIMER_MODE;
+}
+
--- /dev/null
+/* include/asm-arm/arch-lh7a40x/timex.h
+ *
+ * Copyright (C) 2004 Coastal Environmental Systems
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#include <asm/arch/constants.h>
+
+#define CLOCK_TICK_RATE (PLL_CLOCK/6/16)
+
+/*
+#define CLOCK_TICK_RATE 3686400
+#define CLOCK_TICK_FACTOR 80
+*/
--- /dev/null
+/* include/asm-arm/arch-lh7a40x/uncompress.h
+ *
+ * Copyright (C) 2004 Coastal Environmental Systems
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#include <asm/arch/registers.h>
+
+#ifndef UART_R_DATA
+# define UART_R_DATA (0x00)
+#endif
+#ifndef UART_R_STATUS
+# define UART_R_STATUS (0x10)
+#endif
+#define nTxRdy (0x20) /* Not TxReady (literally Tx FIFO full) */
+
+ /* Access UART with physical addresses before MMU is setup */
+#define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS))
+#define UART_DATA (*(volatile unsigned long*) (UART2_PHYS + UART_R_DATA))
+
+static __inline__ void putc (char ch)
+{
+ while (UART_STATUS & nTxRdy)
+ ;
+ UART_DATA = ch;
+}
+
+static void puts (const char* sz)
+{
+ for (; *sz; ++sz) {
+ putc (*sz);
+ if (*sz == '\n')
+ putc ('\r');
+ }
+}
+
+ /* NULL functions; we don't presently need them */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
--- /dev/null
+/* include/asm-arm/arch-lh7a40x/vmalloc.h
+ *
+ * Copyright (C) 2004 Coastal Environmental Systems
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after
+ * the physical memory until the kernel virtual memory starts. That
+ * means that any out-of-bounds memory accesses will hopefully be
+ * caught. The vmalloc() routines leaves a hole of 4kB (one page)
+ * between each vmalloced area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET (8*1024*1024)
+#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_END (0xe8000000)
#ifndef __ASM_ARM_NUMNODES_H
#define __ASM_ARM_NUMNODES_H
-/* Max 4 Nodes */
-#define NODES_SHIFT 2
+#ifdef CONFIG_ARCH_LH7A40X
+# define NODES_SHIFT 4 /* Max 16 nodes for the Sharp CPUs */
+#else
+# define NODES_SHIFT 2 /* Normally, Max 4 Nodes */
+#endif
#endif
/*
* Memory map description
*/
-#define NR_BANKS 8
+#ifdef CONFIG_ARCH_LH7A40X
+# define NR_BANKS 16
+#else
+# define NR_BANKS 8
+#endif
struct meminfo {
int nr_banks;
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