ia64: Jim Wilson says that gcc v3.3 also supports marking ar.pfs as

	clobbered, so use ia64_spinlock_contention() for any GCC with
	v3.3 or newer.

diff --git a/arch/ia64/kernel/head.S b/arch/ia64/kernel/head.S
index db5f71d05bb521afc239ecdf70338880543a768b..2d64faf699815376675a2bf371616051f03032b6 100644 (file)
--- a/arch/ia64/kernel/head.S
+++ b/arch/ia64/kernel/head.S
@@ -864,7 +864,7 @@ SET_REG(b5);
         * the clobber lists for spin_lock() in include/asm-ia64/spinlock.h.
         */
 
-#if __GNUC__ < 3 || (__GNUC__ == 3 && __GNUC_MINOR__ < 4)
+#if __GNUC__ < 3 || (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
 
 GLOBAL_ENTRY(ia64_spinlock_contention_pre3_4)
        .prologue

diff --git a/include/asm-ia64/spinlock.h b/include/asm-ia64/spinlock.h
index d2bcd9b207845b3498572e2b09778f52f5179657..45cdfc53a11217df985cfa216d6554740643b8f9 100644 (file)
--- a/include/asm-ia64/spinlock.h
+++ b/include/asm-ia64/spinlock.h
@@ -39,7 +39,7 @@ _raw_spin_lock (spinlock_t *lock)
 {
        register volatile unsigned int *ptr asm ("r31") = &lock->lock;
 
-#if __GNUC__ < 3 || (__GNUC__ == 3 && __GNUC_MINOR__ < 4)
+#if __GNUC__ < 3 || (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
 # ifdef CONFIG_ITANIUM
        /* don't use brl on Itanium... */
        asm volatile ("{\n\t"