[PATCH] sn: One less panic

From: Pat Gefre <pfg@sgi.com>

One less panic

diff --git a/arch/ia64/sn/io/sn2/ml_iograph.c b/arch/ia64/sn/io/sn2/ml_iograph.c
index 7d5992a549f559b74b61564ae90cac956a815301..26a3c45bfff08aad53475b30933dcebb4eda11d7 100644 (file)
--- a/arch/ia64/sn/io/sn2/ml_iograph.c
+++ b/arch/ia64/sn/io/sn2/ml_iograph.c
@@ -587,11 +587,14 @@ io_init_node(cnodeid_t cnodeid)
                npdap->basew_id = 0;
 
        } else {
-               npdap->basew_id = (((*(volatile int32_t *)(NODE_SWIN_BASE(COMPACT_TO_NASID_NODEID(cnodeid), 0) + BRIDGE_WID_CONTROL))) & WIDGET_WIDGET_ID);
+               void    *bridge;
+               extern uint64_t pcireg_control_get(void *);
 
-               panic(" ****io_init_node: Unknown Widget Part Number 0x%x Widget ID 0x%x attached to Hubv 0x%p ****\n", widget_partnum, npdap->basew_id, (void *)hubv);
+               bridge = (void *)NODE_SWIN_BASE(COMPACT_TO_NASID_NODEID(cnodeid), 0);
+               npdap->basew_id = pcireg_control_get(bridge) & WIDGET_WIDGET_ID;
 
-               /*NOTREACHED*/
+               printk(" ****io_init_node: Unknown Widget Part Number 0x%x Widget ID 0x%x attached to Hubv 0x%p ****\n", widget_partnum, npdap->basew_id, (void *)hubv);
+               return;
        }
        {
                char widname[10];

diff --git a/arch/ia64/sn/io/sn2/pcibr/pcibr_reg.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_reg.c
index 0a95fcfbe973a4927df1ee7434cd553dac28818c..545290f653273e0d6c875ee504c46bd02ba190ef 100644 (file)
--- a/arch/ia64/sn/io/sn2/pcibr/pcibr_reg.c
+++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_reg.c
@@ -17,6 +17,25 @@
 
 #define IS_IOADDR(ptr) (!(((uint64_t)(ptr) & CAC_BASE) == CAC_BASE))
 
+/*
+ * Control Register Access -- Read/Write                            0000_0020
+ */
+
+uint64_t
+pcireg_control_get(void *ptr)
+{
+       uint64_t    ret = 0;
+       pic_t       *bridge;
+
+       if ( IS_IOADDR(ptr) )
+               bridge = (pic_t *)ptr;
+       else
+               bridge = (pic_t *)((pcibr_soft_t)(ptr))->bs_base;
+
+       ret = ((pic_t *)bridge)->p_wid_control;
+       return ret;
+}
+
 void
 pcireg_intr_enable_bit_clr(void *ptr, uint64_t bits)
 {