drm/nouveau/gr/nv3x: fix instobj write offsets in gr setup

[ Upstream commit d0e62ef6ed257715a88d0e5d7cd850a1695429e2 ]

This should fix some unaligned access warnings. This is also likely to
fix non-descript issues on nv30/nv34 as a result of incorrect channel
setup.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96836
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: stable@vger.kernel.org
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
index dcc84eb54fb6dca741199f072abcc5bf85bc0b18..183d1701ae948c4a99a02b963591a37a854c9eaa 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
@@ -88,8 +88,8 @@ nv30_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
                nv_wo32(chan, i, 0x00040004);
        for (i = 0x1f18; i <= 0x3088 ; i += 16) {
                nv_wo32(chan, i + 0, 0x10700ff9);
-               nv_wo32(chan, i + 1, 0x0436086c);
-               nv_wo32(chan, i + 2, 0x000c001b);
+               nv_wo32(chan, i + 4, 0x0436086c);
+               nv_wo32(chan, i + 8, 0x000c001b);
        }
        for (i = 0x30b8; i < 0x30c8; i += 4)
                nv_wo32(chan, i, 0x0000ffff);

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
index 985b7f3306ae03a6f081955b2a5f52fbef5c65e5..720c97135e8537287db6d63a7e1df968d86575d5 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
@@ -86,8 +86,8 @@ nv34_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
                nv_wo32(chan, i, 0x00040004);
        for (i = 0x15ac; i <= 0x271c ; i += 16) {
                nv_wo32(chan, i + 0, 0x10700ff9);
-               nv_wo32(chan, i + 1, 0x0436086c);
-               nv_wo32(chan, i + 2, 0x000c001b);
+               nv_wo32(chan, i + 4, 0x0436086c);
+               nv_wo32(chan, i + 8, 0x000c001b);
        }
        for (i = 0x274c; i < 0x275c; i += 4)
                nv_wo32(chan, i, 0x0000ffff);