drm/msm/a6xx: Fix IRQ storm during msm_recovery test

Once a hang is triggered by the msm_recovery test, the gpu error irq
remains asserted and triggers an interrupt storm. In the worst case,
this IRQ storm lands on the CPU core where the hangcheck timer is
scheduled, blocking it from running. This eventually leads to CPU
watchdog timeouts.

To fix this, mask the gpu error irqs during msm_recovery test and
enable them back during the recovery.

Fixes: 5edf2750d998 ("drm/msm: Add debugfs to disable hw err handling")
Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/730660/
Message-ID: <20260605-assorted-fixes-june-v1-5-2caa04f7287c@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 2c0bbac43c52b105f0fa5574a0c06671c58870e2..f1df2514c6132ba06080439e38dfc497a6d300ce 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -1275,6 +1275,11 @@ static irqreturn_t a5xx_irq(struct msm_gpu *gpu)
                status & ~A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR);
 
        if (priv->disable_err_irq) {
+               /* Turn off interrupts to avoid interrupt storm */
+               gpu_write(gpu, REG_A5XX_RBBM_INT_0_MASK,
+                              A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS |
+                              A5XX_RBBM_INT_0_MASK_CP_SW);
+
                status &= A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS |
                          A5XX_RBBM_INT_0_MASK_CP_SW;
        }

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index a44380316aaa940749cf65d5471835b8af1a646a..e293b4ca808a468ebacaef233fc077c6bad32e53 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1911,8 +1911,11 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
 
        gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status);
 
-       if (priv->disable_err_irq)
+       if (priv->disable_err_irq) {
+               /* Turn off interrupts to avoid interrupt storm */
+               gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS);
                status &= A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS;
+       }
 
        if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT)
                a6xx_fault_detect_irq(gpu);

diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
index 9e44fd1ae634632e9526a3c68e64c6b1f85ab9a0..0f6fd35bd5878bf3a3c6b2ffdcec352409393db8 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
@@ -1211,8 +1211,11 @@ irqreturn_t a8xx_irq(struct msm_gpu *gpu)
 
        gpu_write(gpu, REG_A8XX_RBBM_INT_CLEAR_CMD, status);
 
-       if (priv->disable_err_irq)
+       if (priv->disable_err_irq) {
+               /* Turn off interrupts to avoid interrupt storm */
+               gpu_write(gpu, REG_A8XX_RBBM_INT_0_MASK, A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS);
                status &= A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS;
+       }
 
        if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT)
                a8xx_fault_detect_irq(gpu);

diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 9ac7740a87f0136fa07bc565a6f171819770dbb9..48ac51f4119beac74177de65b9d5c758304da1ea 100644 (file)
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -552,6 +552,8 @@ static void recover_worker(struct kthread_work *work)
                msm_update_fence(ring->fctx, fence);
        }
 
+       priv->disable_err_irq = false;
+
        gpu->funcs->recover(gpu);
 
        /* retire completed submits, plus the one that hung: */