* pci_read_config_word(HWIF(drive)->pci_dev, 0x40, ®40);
* pci_read_config_word(HWIF(drive)->pci_dev, 0x42, ®42);
* pci_read_config_word(HWIF(drive)->pci_dev, 0x44, ®44);
- * pci_read_config_word(HWIF(drive)->pci_dev, 0x48, ®48);
+ * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, ®48);
* pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, ®4a);
- * pci_read_config_word(HWIF(drive)->pci_dev, 0x54, ®54);
+ * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, ®54);
*
* Documentation
* Publically available from Intel web site. Errata documentation
int w_flag = 0x10 << drive->dn;
int u_speed = 0;
int sitre;
- u16 reg4042, reg44, reg48, reg4a, reg54;
- u8 reg55;
+ u16 reg4042, reg4a;
+ u8 reg48, reg54, reg55;
pci_read_config_word(dev, maslave, ®4042);
sitre = (reg4042 & 0x4000) ? 1 : 0;
- pci_read_config_word(dev, 0x44, ®44);
- pci_read_config_word(dev, 0x48, ®48);
+ pci_read_config_byte(dev, 0x48, ®48);
pci_read_config_word(dev, 0x4a, ®4a);
- pci_read_config_word(dev, 0x54, ®54);
+ pci_read_config_byte(dev, 0x54, ®54);
pci_read_config_byte(dev, 0x55, ®55);
switch(speed) {
if (speed >= XFER_UDMA_0) {
if (!(reg48 & u_flag))
- pci_write_config_word(dev, 0x48, reg48|u_flag);
+ pci_write_config_byte(dev, 0x48, reg48 | u_flag);
if (speed == XFER_UDMA_5) {
pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
} else {
pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
}
- if (!(reg4a & u_speed)) {
- pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
- pci_write_config_word(dev, 0x4a, reg4a|u_speed);
- }
+ if ((reg4a & a_speed) != u_speed)
+ pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
if (speed > XFER_UDMA_2) {
- if (!(reg54 & v_flag)) {
- pci_write_config_word(dev, 0x54, reg54|v_flag);
- }
- } else {
- pci_write_config_word(dev, 0x54, reg54 & ~v_flag);
- }
+ if (!(reg54 & v_flag))
+ pci_write_config_byte(dev, 0x54, reg54 | v_flag);
+ } else
+ pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
} else {
if (reg48 & u_flag)
- pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
+ pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
if (reg4a & a_speed)
pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
if (reg54 & v_flag)
- pci_write_config_word(dev, 0x54, reg54 & ~v_flag);
+ pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
if (reg55 & w_flag)
pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
}
int w_flag = 0x10 << drive_dn;
int u_speed = 0;
int sitre;
- u16 reg4042, reg44, reg48, reg4a, reg54;
- u8 reg55;
+ u16 reg4042, reg4a;
+ u8 reg48, reg54, reg55;
pci_read_config_word(dev, maslave, ®4042);
DPRINTK("reg4042 = 0x%04x\n", reg4042);
sitre = (reg4042 & 0x4000) ? 1 : 0;
- pci_read_config_word(dev, 0x44, ®44);
- pci_read_config_word(dev, 0x48, ®48);
+ pci_read_config_byte(dev, 0x48, ®48);
pci_read_config_word(dev, 0x4a, ®4a);
- pci_read_config_word(dev, 0x54, ®54);
+ pci_read_config_byte(dev, 0x54, ®54);
pci_read_config_byte(dev, 0x55, ®55);
switch(speed) {
}
if (!(reg48 & u_flag))
- pci_write_config_word(dev, 0x48, reg48|u_flag);
+ pci_write_config_byte(dev, 0x48, reg48 | u_flag);
if (speed == XFER_UDMA_5) {
pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
} else {
pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
}
- if (!(reg4a & u_speed)) {
- pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
- pci_write_config_word(dev, 0x4a, reg4a|u_speed);
- }
+ if ((reg4a & a_speed) != u_speed)
+ pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
if (speed > XFER_UDMA_2) {
- if (!(reg54 & v_flag)) {
- pci_write_config_word(dev, 0x54, reg54|v_flag);
- }
- } else {
- pci_write_config_word(dev, 0x54, reg54 & ~v_flag);
- }
+ if (!(reg54 & v_flag))
+ pci_write_config_byte(dev, 0x54, reg54 | v_flag);
+ } else
+ pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
}
/* move to PCI layer, integrate w/ MSI stuff */