#ifdef CONFIG_ARCH_COTULLA_IDP
mov r7, #MACH_TYPE_COTULLA_IDP
#endif
-
-#ifdef CONFIG_ARCH_IQ80310
- /*
- * Crank the CPU up to 733MHz
- */
- mov r1, #9
- mcr p14, 0, r1, c6, c0, 0
-
- /*
- * Disable ECC error notification
- * At some point, we should add an ECC handler to Linux
- */
- mov r1, #0x1500
- mov r0, #0x4
- str r0, [r1, #0x34]
-
- mov r7, #MACH_TYPE_IQ80310
-#endif
-
-
+++ /dev/null
-#
-# Automatically generated make config: don't edit
-#
-CONFIG_ARM=y
-CONFIG_MMU=y
-CONFIG_UID16=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-
-#
-# General setup
-#
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-# CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_EMBEDDED is not set
-CONFIG_KALLSYMS=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-# CONFIG_MODULE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
-# CONFIG_MODVERSIONS is not set
-CONFIG_KMOD=y
-
-#
-# System Type
-#
-# CONFIG_ARCH_ADIFCC is not set
-# CONFIG_ARCH_CLPS7500 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CO285 is not set
-# CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-CONFIG_ARCH_IOP3XX=y
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_SHARK is not set
-
-#
-# CLPS711X/EP721X Implementations
-#
-
-#
-# Epxa10db
-#
-
-#
-# Footbridge Implementations
-#
-
-#
-# IOP3xx Implementation Options
-#
-CONFIG_ARCH_IQ80310=y
-# CONFIG_ARCH_IQ80321 is not set
-CONFIG_ARCH_IOP310=y
-# CONFIG_ARCH_IOP321 is not set
-
-#
-# IOP3xx Chipset Features
-#
-# CONFIG_IOP3XX_AAU is not set
-# CONFIG_IOP3XX_DMA is not set
-# CONFIG_IOP3XX_MU is not set
-# CONFIG_IOP3XX_PMON is not set
-
-#
-# ADIFCC Implementation Options
-#
-
-#
-# ADI Board Types
-#
-
-#
-# Intel PXA250/210 Implementations
-#
-
-#
-# SA11x0 Implementations
-#
-
-#
-# Processor Type
-#
-CONFIG_CPU_32=y
-CONFIG_CPU_XSCALE=y
-CONFIG_XS80200=y
-CONFIG_CPU_32v5=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-CONFIG_XSCALE_PMU=y
-
-#
-# General setup
-#
-CONFIG_PCI=y
-# CONFIG_ZBOOT_ROM is not set
-CONFIG_ZBOOT_ROM_TEXT=0x00060000
-CONFIG_ZBOOT_ROM_BSS=0xa1008000
-# CONFIG_PCI_LEGACY_PROC is not set
-CONFIG_PCI_NAMES=y
-# CONFIG_HOTPLUG is not set
-
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-
-#
-# At least one math emulation must be selected
-#
-CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
-# CONFIG_FPE_FASTFPE is not set
-CONFIG_KCORE_ELF=y
-# CONFIG_KCORE_AOUT is not set
-CONFIG_BINFMT_AOUT=y
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_MISC is not set
-# CONFIG_PM is not set
-# CONFIG_PREEMPT is not set
-# CONFIG_ARTHUR is not set
-CONFIG_CMDLINE="console=ttyS0,115200 ip=bootp mem=32M root=/dev/nfs initrd=0xc0800000,4M"
-CONFIG_ALIGNMENT_TRAP=y
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_REDBOOT_PARTS=y
-# CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_AFS_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_GEN_PROBE=y
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_CFI_INTELEXT=y
-# CONFIG_MTD_CFI_AMDSTD is not set
-# CONFIG_MTD_CFI_STAA is not set
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PHYSMAP is not set
-# CONFIG_MTD_ARM_INTEGRATOR is not set
-CONFIG_MTD_IQ80310=y
-# CONFIG_MTD_EDB7312 is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_PMC551 is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLKMTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
-# CONFIG_MTD_NAND is not set
-
-#
-# Plug and Play support
-#
-# CONFIG_PNP is not set
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_FD is not set
-# CONFIG_BLK_CPQ_DA is not set
-# CONFIG_BLK_CPQ_CISS_DA is not set
-# CONFIG_BLK_DEV_DAC960 is not set
-# CONFIG_BLK_DEV_UMEM is not set
-# CONFIG_BLK_DEV_LOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_BLK_DEV_INITRD=y
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# Networking support
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-# CONFIG_PACKET is not set
-# CONFIG_NETLINK_DEV is not set
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_INET_ECN is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-
-#
-# IP: Netfilter Configuration
-#
-# CONFIG_IP_NF_CONNTRACK is not set
-# CONFIG_IP_NF_QUEUE is not set
-# CONFIG_IP_NF_IPTABLES is not set
-# CONFIG_IP_NF_ARPTABLES is not set
-# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
-# CONFIG_IP_NF_COMPAT_IPFWADM is not set
-
-#
-# IP: Virtual Server Configuration
-#
-# CONFIG_IP_VS is not set
-# CONFIG_IPV6 is not set
-# CONFIG_XFRM_USER is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-CONFIG_IPV6_SCTP__=y
-# CONFIG_IP_SCTP is not set
-# CONFIG_ATM is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_LLC is not set
-# CONFIG_DECNET is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_NET_HW_FLOWCONTROL is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-CONFIG_NETDEVICES=y
-
-#
-# ARCnet devices
-#
-# CONFIG_ARCNET is not set
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_ETHERTAP is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-# CONFIG_SMC91X is not set
-# CONFIG_HAPPYMEAL is not set
-# CONFIG_SUNGEM is not set
-# CONFIG_NET_VENDOR_3COM is not set
-
-#
-# Tulip family network device support
-#
-# CONFIG_NET_TULIP is not set
-# CONFIG_HP100 is not set
-CONFIG_NET_PCI=y
-# CONFIG_PCNET32 is not set
-# CONFIG_AMD8111_ETH is not set
-# CONFIG_ADAPTEC_STARFIRE is not set
-# CONFIG_B44 is not set
-# CONFIG_DGRS is not set
-CONFIG_EEPRO100=y
-# CONFIG_EEPRO100_PIO is not set
-# CONFIG_E100 is not set
-# CONFIG_FEALNX is not set
-# CONFIG_NATSEMI is not set
-# CONFIG_NE2K_PCI is not set
-# CONFIG_8139CP is not set
-# CONFIG_8139TOO is not set
-# CONFIG_SIS900 is not set
-# CONFIG_EPIC100 is not set
-# CONFIG_SUNDANCE is not set
-# CONFIG_TLAN is not set
-# CONFIG_VIA_RHINE is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-# CONFIG_ACENIC is not set
-# CONFIG_DL2K is not set
-# CONFIG_E1000 is not set
-# CONFIG_NS83820 is not set
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-# CONFIG_R8169 is not set
-# CONFIG_SK98LIN is not set
-# CONFIG_TIGON3 is not set
-
-#
-# Ethernet (10000 Mbit)
-#
-# CONFIG_IXGB is not set
-# CONFIG_FDDI is not set
-# CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Token Ring devices (depends on LLC=y)
-#
-# CONFIG_RCPCI is not set
-# CONFIG_SHAPER is not set
-
-#
-# Wan interfaces
-#
-# CONFIG_WAN is not set
-
-#
-# IrDA (infrared) support
-#
-# CONFIG_IRDA is not set
-
-#
-# Amateur Radio support
-#
-# CONFIG_HAMRADIO is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-CONFIG_IDE=y
-
-#
-# IDE, ATA and ATAPI Block devices
-#
-CONFIG_BLK_DEV_IDE=y
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_HD is not set
-CONFIG_BLK_DEV_IDEDISK=y
-# CONFIG_IDEDISK_MULTI_MODE is not set
-# CONFIG_IDEDISK_STROKE is not set
-CONFIG_BLK_DEV_IDECD=y
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-# CONFIG_IDE_TASKFILE_IO is not set
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_BLK_DEV_IDEPCI is not set
-
-#
-# SCSI device support
-#
-# CONFIG_SCSI is not set
-
-#
-# IEEE 1394 (FireWire) support (EXPERIMENTAL)
-#
-# CONFIG_IEEE1394 is not set
-
-#
-# I2O device support
-#
-# CONFIG_I2O is not set
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN_BOOL is not set
-
-#
-# Input device support
-#
-# CONFIG_INPUT is not set
-
-#
-# Userland interfaces
-#
-
-#
-# Input I/O drivers
-#
-# CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
-# CONFIG_SERIO is not set
-
-#
-# Input Device Drivers
-#
-
-#
-# Character devices
-#
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_SERIAL_8250_EXTENDED is not set
-
-#
-# Non-8250 serial port support
-#
-# CONFIG_SERIAL_DZ is not set
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_UNIX98_PTY_COUNT=256
-
-#
-# I2C support
-#
-# CONFIG_I2C is not set
-
-#
-# I2C Hardware Sensors Mainboard support
-#
-
-#
-# I2C Hardware Sensors Chip support
-#
-# CONFIG_I2C_SENSOR is not set
-
-#
-# L3 serial bus support
-#
-# CONFIG_L3 is not set
-
-#
-# Mice
-#
-# CONFIG_BUSMOUSE is not set
-# CONFIG_QIC02_TAPE is not set
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-# CONFIG_NVRAM is not set
-# CONFIG_RTC is not set
-# CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_FTAPE is not set
-# CONFIG_AGP is not set
-# CONFIG_DRM is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_HANGCHECK_TIMER is not set
-
-#
-# Multimedia devices
-#
-CONFIG_VIDEO_DEV=y
-
-#
-# Video For Linux
-#
-# CONFIG_VIDEO_PROC_FS is not set
-
-#
-# Video Adapters
-#
-# CONFIG_VIDEO_PMS is not set
-# CONFIG_VIDEO_CPIA is not set
-# CONFIG_VIDEO_STRADIS is not set
-# CONFIG_VIDEO_HEXIUM_ORION is not set
-# CONFIG_VIDEO_HEXIUM_GEMINI is not set
-
-#
-# Radio Adapters
-#
-# CONFIG_RADIO_GEMTEK_PCI is not set
-# CONFIG_RADIO_MAXIRADIO is not set
-# CONFIG_RADIO_MAESTRO is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-CONFIG_DVB=y
-CONFIG_DVB_CORE=y
-
-#
-# Supported Frontend Modules
-#
-# CONFIG_DVB_STV0299 is not set
-# CONFIG_DVB_ALPS_BSRV2 is not set
-# CONFIG_DVB_ALPS_TDLB7 is not set
-# CONFIG_DVB_ALPS_TDMB7 is not set
-# CONFIG_DVB_ATMEL_AT76C651 is not set
-# CONFIG_DVB_CX24110 is not set
-# CONFIG_DVB_GRUNDIG_29504_491 is not set
-# CONFIG_DVB_GRUNDIG_29504_401 is not set
-# CONFIG_DVB_MT312 is not set
-# CONFIG_DVB_VES1820 is not set
-# CONFIG_DVB_TDA1004X is not set
-
-#
-# Supported SAA7146 based PCI Adapters
-#
-# CONFIG_DVB_AV7110 is not set
-# CONFIG_DVB_BUDGET is not set
-
-#
-# Supported FlexCopII (B2C2) Adapters
-#
-# CONFIG_DVB_B2C2_SKYSTAR is not set
-# CONFIG_VIDEO_BTCX is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_JBD is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-# CONFIG_FAT_FS is not set
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-# CONFIG_DEVFS_FS is not set
-CONFIG_DEVPTS_FS=y
-# CONFIG_DEVPTS_FS_XATTR is not set
-CONFIG_TMPFS=y
-CONFIG_RAMFS=y
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_JFFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-# CONFIG_JFFS2_FS_NAND is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
-CONFIG_NFS_FS=y
-# CONFIG_NFS_V3 is not set
-# CONFIG_NFS_V4 is not set
-# CONFIG_NFSD is not set
-CONFIG_ROOT_NFS=y
-CONFIG_LOCKD=y
-# CONFIG_EXPORTFS is not set
-CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_GSS is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_INTERMEZZO_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-# CONFIG_NEC98_PARTITION is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-
-#
-# Graphics support
-#
-# CONFIG_FB is not set
-
-#
-# Sound
-#
-# CONFIG_SOUND is not set
-
-#
-# Misc devices
-#
-
-#
-# Multimedia Capabilities Port drivers
-#
-# CONFIG_MCP is not set
-
-#
-# Console Switches
-#
-# CONFIG_SWITCHES is not set
-
-#
-# USB support
-#
-# CONFIG_USB is not set
-# CONFIG_USB_GADGET is not set
-
-#
-# Bluetooth support
-#
-# CONFIG_BT is not set
-
-#
-# Kernel hacking
-#
-CONFIG_FRAME_POINTER=y
-CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_INFO is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_WAITQ is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_DEBUG_LL=y
-
-#
-# Security options
-#
-# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-# CONFIG_CRYPTO is not set
-
-#
-# Library routines
-#
-# CONFIG_CRC32 is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_STANDALONE=y
+CONFIG_BROKEN_ON_SMP=y
#
# General setup
#
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_HOTPLUG is not set
+# CONFIG_IKCONFIG is not set
# CONFIG_EMBEDDED is not set
CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_FUTEX=y
CONFIG_EPOLL=y
+CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
#
# Loadable module support
#
# System Type
#
-# CONFIG_ARCH_ADIFCC is not set
# CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set
-# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_CAMELOT is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_INTEGRATOR is not set
CONFIG_ARCH_IOP3XX=y
+# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_SHARK is not set
-
-#
-# CLPS711X/EP721X Implementations
-#
-
-#
-# Epxa10db
-#
-
-#
-# Footbridge Implementations
-#
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_VERSATILE_PB is not set
#
# IOP3xx Implementation Options
# CONFIG_IOP3XX_MU is not set
# CONFIG_IOP3XX_PMON is not set
-#
-# ADIFCC Implementation Options
-#
-
-#
-# ADI Board Types
-#
-
-#
-# Intel PXA250/210 Implementations
-#
-
-#
-# SA11x0 Implementations
-#
-
#
# Processor Type
#
CONFIG_CPU_32=y
CONFIG_CPU_XSCALE=y
CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_MINICACHE=y
#
# Processor Features
CONFIG_ZBOOT_ROM_BSS=0x0
# CONFIG_PCI_LEGACY_PROC is not set
CONFIG_PCI_NAMES=y
-# CONFIG_HOTPLUG is not set
-
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
#
# At least one math emulation must be selected
CONFIG_FPE_NWFPE=y
# CONFIG_FPE_NWFPE_XP is not set
# CONFIG_FPE_FASTFPE is not set
-CONFIG_KCORE_ELF=y
-# CONFIG_KCORE_AOUT is not set
-CONFIG_BINFMT_AOUT=y
+# CONFIG_VFP is not set
CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_AOUT=y
# CONFIG_BINFMT_MISC is not set
+
+#
+# Generic Driver Options
+#
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_DEBUG_DRIVER is not set
# CONFIG_PM is not set
# CONFIG_PREEMPT is not set
# CONFIG_ARTHUR is not set
#
# Plug and Play support
#
-# CONFIG_PNP is not set
#
# Block devices
# CONFIG_BLK_DEV_UMEM is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
# CONFIG_BLK_DEV_INITRD is not set
#
# CONFIG_PACKET is not set
# CONFIG_NETLINK_DEV is not set
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
-# CONFIG_INET_ECN is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
+#
+# IP: Virtual Server Configuration
+#
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
#
# IP: Netfilter Configuration
#
# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
# CONFIG_IP_NF_COMPAT_IPFWADM is not set
-#
-# IP: Virtual Server Configuration
-#
-# CONFIG_IP_VS is not set
-# CONFIG_IPV6 is not set
-# CONFIG_XFRM_USER is not set
-
#
# SCTP Configuration (EXPERIMENTAL)
#
-CONFIG_IPV6_SCTP__=y
# CONFIG_IP_SCTP is not set
# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
-# CONFIG_LLC is not set
# CONFIG_DECNET is not set
-# CONFIG_BRIDGE is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_NET_DIVERT is not set
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
#
# ARCnet devices
#
# CONFIG_ARCNET is not set
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_ETHERTAP is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
-# CONFIG_MII is not set
-# CONFIG_SMC91X is not set
+CONFIG_MII=y
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNGEM is not set
# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_SMC91X is not set
#
# Tulip family network device support
# CONFIG_AMD8111_ETH is not set
# CONFIG_ADAPTEC_STARFIRE is not set
# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
# CONFIG_DGRS is not set
CONFIG_EEPRO100=y
# CONFIG_EEPRO100_PIO is not set
# CONFIG_SUNDANCE is not set
# CONFIG_TLAN is not set
# CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_VELOCITY is not set
#
# Ethernet (1000 Mbit)
# Ethernet (10000 Mbit)
#
# CONFIG_IXGB is not set
-# CONFIG_FDDI is not set
-# CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
+# CONFIG_S2IO is not set
#
-# Wireless LAN (non-hamradio)
+# Token Ring devices
#
-# CONFIG_NET_RADIO is not set
+# CONFIG_TR is not set
#
-# Token Ring devices (depends on LLC=y)
+# Wireless LAN (non-hamradio)
#
-# CONFIG_RCPCI is not set
-# CONFIG_SHAPER is not set
+# CONFIG_NET_RADIO is not set
#
# Wan interfaces
#
# CONFIG_WAN is not set
-
-#
-# IrDA (infrared) support
-#
-# CONFIG_IRDA is not set
-
-#
-# Amateur Radio support
-#
-# CONFIG_HAMRADIO is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
#
# ATA/ATAPI/MFM/RLL support
#
CONFIG_IDE=y
-
-#
-# IDE, ATA and ATAPI Block devices
-#
CONFIG_BLK_DEV_IDE=y
#
# Please see Documentation/ide.txt for help/info on IDE drives
#
-# CONFIG_BLK_DEV_HD is not set
+# CONFIG_BLK_DEV_IDE_SATA is not set
CONFIG_BLK_DEV_IDEDISK=y
# CONFIG_IDEDISK_MULTI_MODE is not set
-# CONFIG_IDEDISK_STROKE is not set
CONFIG_BLK_DEV_IDECD=y
+# CONFIG_BLK_DEV_IDETAPE is not set
# CONFIG_BLK_DEV_IDEFLOPPY is not set
# CONFIG_IDE_TASK_IOCTL is not set
# CONFIG_IDE_TASKFILE_IO is not set
#
# IDE chipset support/bugfixes
#
+CONFIG_IDE_GENERIC=y
CONFIG_BLK_DEV_IDEPCI=y
-# CONFIG_BLK_DEV_GENERIC is not set
# CONFIG_IDEPCI_SHARE_IRQ is not set
-CONFIG_BLK_DEV_IDEDMA_PCI=y
-# CONFIG_BLK_DEV_IDE_TCQ is not set
# CONFIG_BLK_DEV_OFFBOARD is not set
+# CONFIG_BLK_DEV_GENERIC is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_SL82C105 is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
CONFIG_IDEDMA_PCI_AUTO=y
# CONFIG_IDEDMA_ONLYDISK is not set
-CONFIG_BLK_DEV_IDEDMA=y
CONFIG_BLK_DEV_ADMA=y
# CONFIG_BLK_DEV_AEC62XX is not set
# CONFIG_BLK_DEV_ALI15X3 is not set
# CONFIG_BLK_DEV_TRIFLEX is not set
# CONFIG_BLK_DEV_CY82C693 is not set
# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
# CONFIG_BLK_DEV_HPT34X is not set
# CONFIG_BLK_DEV_HPT366 is not set
# CONFIG_BLK_DEV_SC1200 is not set
# CONFIG_BLK_DEV_PIIX is not set
# CONFIG_BLK_DEV_NS87415 is not set
-# CONFIG_BLK_DEV_OPTI621 is not set
# CONFIG_BLK_DEV_PDC202XX_OLD is not set
# CONFIG_BLK_DEV_PDC202XX_NEW is not set
# CONFIG_BLK_DEV_SVWKS is not set
# CONFIG_BLK_DEV_SLC90E66 is not set
# CONFIG_BLK_DEV_TRM290 is not set
# CONFIG_BLK_DEV_VIA82CXXX is not set
-# CONFIG_BLK_DEV_SL82C105 is not set
-CONFIG_IDEDMA_AUTO=y
+# CONFIG_IDE_ARM is not set
+CONFIG_BLK_DEV_IDEDMA=y
# CONFIG_IDEDMA_IVB is not set
+CONFIG_IDEDMA_AUTO=y
+# CONFIG_BLK_DEV_HD is not set
#
# SCSI device support
# CONFIG_SCSI is not set
#
-# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
#
# CONFIG_IEEE1394 is not set
#
# ISDN subsystem
#
-# CONFIG_ISDN_BOOL is not set
+# CONFIG_ISDN is not set
#
# Input device support
#
-# CONFIG_INPUT is not set
+CONFIG_INPUT=y
#
# Userland interfaces
#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
#
# Input I/O drivers
# CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y
# CONFIG_SERIO is not set
+# CONFIG_SERIO_I8042 is not set
#
# Input Device Drivers
#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
#
# Character devices
#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
# CONFIG_SERIAL_NONSTANDARD is not set
#
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
# CONFIG_SERIAL_8250_EXTENDED is not set
#
# Non-8250 serial port support
#
-# CONFIG_SERIAL_DZ is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
-CONFIG_UNIX98_PTY_COUNT=256
-
-#
-# I2C support
-#
-# CONFIG_I2C is not set
-
-#
-# I2C Hardware Sensors Mainboard support
-#
-
-#
-# I2C Hardware Sensors Chip support
-#
-# CONFIG_I2C_SENSOR is not set
-
-#
-# L3 serial bus support
-#
-# CONFIG_L3 is not set
-
-#
-# Mice
-#
-# CONFIG_BUSMOUSE is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_QIC02_TAPE is not set
#
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
-# CONFIG_HANGCHECK_TIMER is not set
-
-#
-# Multimedia devices
-#
-CONFIG_VIDEO_DEV=y
#
-# Video For Linux
-#
-# CONFIG_VIDEO_PROC_FS is not set
-
-#
-# Video Adapters
+# I2C support
#
-# CONFIG_VIDEO_PMS is not set
-# CONFIG_VIDEO_CPIA is not set
-# CONFIG_VIDEO_STRADIS is not set
-# CONFIG_VIDEO_HEXIUM_ORION is not set
-# CONFIG_VIDEO_HEXIUM_GEMINI is not set
+# CONFIG_I2C is not set
#
-# Radio Adapters
+# Multimedia devices
#
-# CONFIG_RADIO_GEMTEK_PCI is not set
-# CONFIG_RADIO_MAXIRADIO is not set
-# CONFIG_RADIO_MAESTRO is not set
+# CONFIG_VIDEO_DEV is not set
#
# Digital Video Broadcasting Devices
#
# CONFIG_DVB is not set
-# CONFIG_VIDEO_BTCX is not set
#
# File systems
# Pseudo filesystems
#
CONFIG_PROC_FS=y
+CONFIG_SYSFS=y
# CONFIG_DEVFS_FS is not set
-CONFIG_DEVPTS_FS=y
# CONFIG_DEVPTS_FS_XATTR is not set
CONFIG_TMPFS=y
+# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
# CONFIG_EXPORTFS is not set
CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_GSS is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
-# CONFIG_INTERMEZZO_FS is not set
# CONFIG_AFS_FS is not set
#
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
-# CONFIG_NEC98_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
#
-# Graphics support
+# Native Language Support
#
-# CONFIG_FB is not set
+# CONFIG_NLS is not set
#
-# Sound
+# Profiling support
#
-# CONFIG_SOUND is not set
+# CONFIG_PROFILING is not set
#
-# Misc devices
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Console display driver support
#
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
#
-# Multimedia Capabilities Port drivers
+# Sound
#
-# CONFIG_MCP is not set
+# CONFIG_SOUND is not set
#
-# Console Switches
+# Misc devices
#
-# CONFIG_SWITCHES is not set
#
# USB support
#
# CONFIG_USB is not set
-# CONFIG_USB_GADGET is not set
#
-# Bluetooth support
+# USB Gadget Support
#
-# CONFIG_BT is not set
+# CONFIG_USB_GADGET is not set
#
# Kernel hacking
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_ERRORS=y
CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
#
# Security options
#
# Library routines
#
-# CONFIG_CRC32 is not set
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
.macro addruart,rx
mov \rx, #0xfe000000 @ physical
-#ifdef CONFIG_ARCH_IQ80310
- orr \rx, \rx, #0x00810000 @ location of the UART
-#elif defined(CONFIG_ARCH_IQ80321)
+#if defined(CONFIG_ARCH_IQ80321)
orr \rx, \rx, #0x00800000 @ location of the UART
#else
#error Unknown IOP3XX implementation
.macro irq_prio_table
.endm
-#elif defined(CONFIG_ARCH_IOP310)
-
- .macro disable_fiq
- .endm
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- mrc p13, 0, \irqstat, c4, c0, 0 @ get INTSRC
- mrc p13, 0, \base, c0, c0, 0 @ get INTCTL
-
- tst \irqstat, #(1<<29) @ if INTSRC_BI
- tstne \base, #(1<<3) @ and INTCTL_BM
- movne \irqnr, #IRQ_XS80200_BCU
- bne 1001f
-
- tst \irqstat, #(1<<28) @ if INTSRC_PI
- tstne \base, #(1<<2) @ and INTCTL_PM
- movne \irqnr, #IRQ_XS80200_PMU
- bne 1001f
-
- tst \irqstat, #(1<<31) @ if INTSRC_FI
- tstne \base, #(1<<0) @ and INTCTL_FM
- movne \irqnr, #IRQ_XS80200_EXTFIQ
- bne 1001f
-
- tst \irqstat, #(1<<30) @ if INTSRC_II
- tstne \base, #(1<<1) @ and INTCTL_IM
- movne \irqnr, #IRQ_XS80200_EXTIRQ
-
-1001:
- .endm
-
- .macro irq_prio_table
- .endm
-
#elif defined(CONFIG_ARCH_IOP321)
.macro disable_fiq
.endm
choice
prompt "IOP3xx System Type"
- default ARCH_IQ80310
-
-config ARCH_IQ80310
- bool "IQ80310"
- help
- Say Y here if you want to run your kernel on the Intel IQ80310
- evaluation kit for the IOP310 chipset.
+ default ARCH_IQ80321
config ARCH_IQ80321
bool "IQ80321"
endchoice
# Which IOP variant are we running?
-config ARCH_IOP310
- bool
- default ARCH_IQ80310
- help
- The IQ80310 uses the IOP310 variant.
-
config ARCH_IOP321
bool
default ARCH_IQ80321
bool "Support Intel IOP3xx DMA (EXPERIMENTAL)"
depends on EXPERIMENTAL
-config IOP3XX_MU
- bool "Support Intel IOP3xx Messaging Unit (EXPERIMENTAL)"
- depends on EXPERIMENTAL
-
-config IOP3XX_PMON
- bool "Support Intel IOP3xx Performance Monitor (EXPERIMENTAL)"
- depends on EXPERIMENTAL
-
endmenu
endif
obj-n :=
obj- :=
-obj-$(CONFIG_ARCH_IOP310) += xs80200-irq.o iop310-irq.o iop310-pci.o mm.o
-
-obj-$(CONFIG_ARCH_IQ80310) += iq80310-pci.o iq80310-irq.o
-
obj-$(CONFIG_ARCH_IOP321) += iop321-irq.o iop321-pci.o mm-321.o iop321-time.o
obj-$(CONFIG_ARCH_IQ80321) += iq80321-pci.o
-ifeq ($(CONFIG_ARCH_IQ80310),y)
- ifneq ($(CONFIG_XSCALE_PMU_TIMER),y)
- obj-y += iq80310-time.o
- endif
-endif
-
obj-$(CONFIG_IOP3XX_AAU) += aau.o
obj-$(CONFIG_IOP3XX_DMA) += dma.o
-obj-$(CONFIG_IOP3XX_MU) += message.o
-obj-$(CONFIG_IOP3XX_PMON) += pmon.o
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
-#ifdef CONFIG_ARCH_IQ80310
-extern void iq80310_map_io(void);
-extern void iq80310_init_irq(void);
-#endif
-
#ifdef CONFIG_ARCH_IQ80321
extern void iq80321_map_io(void);
extern void iop321_init_irq(void);
extern void iop321_init_time(void);
#endif
-#ifdef CONFIG_ARCH_IQ80310
-static void __init
-fixup_iq80310(struct machine_desc *desc, struct tag *tags,
- char **cmdline, struct meminfo *mi)
-{
- system_rev = (*(volatile unsigned int*)0xfe830000) & 0x0f;
-
- if (system_rev)
- system_rev = 0xF;
-}
-#endif
-
#ifdef CONFIG_ARCH_IQ80321
static void __init
-fixup_iop321(struct machine_desc *desc, struct param_struct *params,
+fixup_iop321(struct machine_desc *desc, struct tag *tags,
char **cmdline, struct meminfo *mi)
{
}
#endif
-#ifdef CONFIG_ARCH_IQ80310
-MACHINE_START(IQ80310, "Cyclone IQ80310")
- MAINTAINER("MontaVista Software Inc.")
- BOOT_MEM(0xa0000000, 0xfe000000, 0xfe000000)
- FIXUP(fixup_iq80310)
- MAPIO(iq80310_map_io)
- INITIRQ(iq80310_init_irq)
-MACHINE_END
-
-#elif defined(CONFIG_ARCH_IQ80321)
+#if defined(CONFIG_ARCH_IQ80321)
MACHINE_START(IQ80321, "Intel IQ80321")
- MAINTAINER("MontaVista Software, Inc.")
+ MAINTAINER("Intel Corporation")
BOOT_MEM(PHYS_OFFSET, IQ80321_UART1, 0xfe800000)
FIXUP(fixup_iop321)
MAPIO(iq80321_map_io)
MACHINE_END
#else
-#error No machine descriptor defined for this IOP310 implementation
+#error No machine descriptor defined for this IOP3xx implementation
#endif
+++ /dev/null
-/*
- * linux/arch/arm/mach-iop3xx/iop310-irq.c
- *
- * Generic IOP310 IRQ handling functionality
- *
- * Author: Nicolas Pitre
- * Copyright: (C) 2001 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Added IOP310 chipset and IQ80310 board demuxing, masking code. - DS
- *
- */
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-
-#include <asm/mach/irq.h>
-#include <asm/irq.h>
-#include <asm/hardware.h>
-
-extern void xs80200_irq_mask(unsigned int);
-extern void xs80200_irq_unmask(unsigned int);
-extern void xs80200_init_irq(void);
-
-extern void do_IRQ(int, struct pt_regs *);
-
-static u32 iop310_mask /* = 0 */;
-
-static void iop310_irq_mask (unsigned int irq)
-{
- iop310_mask ++;
-
- /*
- * No mask bits on the 80312, so we have to
- * mask everything from the outside!
- */
- if (iop310_mask == 1) {
- disable_irq(IRQ_XS80200_EXTIRQ);
- irq_desc[IRQ_XS80200_EXTIRQ].chip->mask(IRQ_XS80200_EXTIRQ);
- }
-}
-
-static void iop310_irq_unmask (unsigned int irq)
-{
- if (iop310_mask)
- iop310_mask --;
-
- /*
- * Check if all 80312 sources are unmasked now
- */
- if (iop310_mask == 0)
- enable_irq(IRQ_XS80200_EXTIRQ);
-}
-
-struct irqchip ext_chip = {
- .ack = iop310_irq_mask,
- .mask = iop310_irq_mask,
- .unmask = iop310_irq_unmask,
-};
-
-void
-iop310_irq_demux(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
-{
- u32 fiq1isr = *((volatile u32*)IOP310_FIQ1ISR);
- u32 fiq2isr = *((volatile u32*)IOP310_FIQ2ISR);
- struct irqdesc *d;
- unsigned int irqno = 0;
-
- if(fiq1isr)
- {
- if(fiq1isr & 0x1)
- irqno = IRQ_IOP310_DMA0;
- if(fiq1isr & 0x2)
- irqno = IRQ_IOP310_DMA1;
- if(fiq1isr & 0x4)
- irqno = IRQ_IOP310_DMA2;
- if(fiq1isr & 0x10)
- irqno = IRQ_IOP310_PMON;
- if(fiq1isr & 0x20)
- irqno = IRQ_IOP310_AAU;
- }
- else
- {
- if(fiq2isr & 0x2)
- irqno = IRQ_IOP310_I2C;
- if(fiq2isr & 0x4)
- irqno = IRQ_IOP310_MU;
- }
-
- if (irqno) {
- d = irq_desc + irqno;
- d->handle(irqno, d, regs);
- }
-}
-
-void __init iop310_init_irq(void)
-{
- unsigned int i;
-
- for(i = IOP310_IRQ_OFS; i < NR_IOP310_IRQS; i++)
- {
- set_irq_chip(i, &ext_chip);
- set_irq_handler(i, do_level_IRQ);
- set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
- }
-
- xs80200_init_irq();
-}
+++ /dev/null
-/*
- * arch/arm/mach-iop3xx/iop310-pci.c
- *
- * PCI support for the Intel IOP310 chipset
- *
- * Matt Porter <mporter@mvista.com>
- *
- * Copyright (C) 2001 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/slab.h>
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/system.h>
-#include <asm/hardware.h>
-#include <asm/mach/pci.h>
-
-#include <asm/arch/iop310.h>
-
-/*
- * *** Special note - why the IOP310 should NOT be used ***
- *
- * The PCI ATU is a brain dead implementation, only allowing 32-bit
- * accesses to PCI configuration space. This is especially brain
- * dead for writes to this space. A simple for-instance:
- *
- * You want to modify the command register *without* corrupting the
- * status register.
- *
- * To perform this, you need to read *32* bits of data from offset 4,
- * mask off the low 16, replace them with the new data, and write *32*
- * bits back.
- *
- * Writing the status register at offset 6 with status bits set *clears*
- * the status.
- *
- * Hello? Could we have a *SANE* implementation of a PCI ATU some day
- * *PLEASE*?
- */
-#undef DEBUG
-#ifdef DEBUG
-#define DBG(x...) printk(x)
-#else
-#define DBG(x...) do { } while (0)
-#endif
-
-/*
- * Calculate the address, etc from the bus, devfn and register
- * offset. Note that we have two root buses, so we need some
- * method to determine whether we need config type 0 or 1 cycles.
- * We use a root bus number in our bus->sysdata structure for this.
- */
-static u32 iop310_cfg_address(struct pci_bus *bus, int devfn, int where)
-{
- struct pci_sys_data *sys = bus->sysdata;
- u32 addr;
-
- if (sys->busnr == bus->number)
- addr = 1 << (PCI_SLOT(devfn) + 16);
- else
- addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
-
- addr |= PCI_FUNC(devfn) << 8 | (where & ~3);
-
- return addr;
-}
-
-/*
- * Primary PCI interface support.
- */
-static int iop310_pri_pci_status(void)
-{
- unsigned int status;
- int ret = 0;
-
- status = *IOP310_PATUSR;
- if (status & 0xf900) {
- *IOP310_PATUSR = status & 0xf900;
- ret = 1;
- }
- status = *IOP310_PATUISR;
- if (status & 0x0000018f) {
- *IOP310_PATUISR = status & 0x0000018f;
- ret = 1;
- }
- status = *IOP310_PSR;
- if (status & 0xf900) {
- *IOP310_PSR = status & 0xf900;
- ret = 1;
- }
- status = *IOP310_PBISR;
- if (status & 0x003f) {
- *IOP310_PBISR = status & 0x003f;
- ret = 1;
- }
- return ret;
-}
-
-/*
- * Simply write the address register and read the configuration
- * data. Note that the 4 nop's ensure that we are able to handle
- * a delayed abort (in theory.)
- */
-static inline u32 iop310_pri_read(unsigned long addr)
-{
- u32 val;
-
- __asm__ __volatile__(
- "str %1, [%2]\n\t"
- "ldr %0, [%3]\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- : "=r" (val)
- : "r" (addr), "r" (IOP310_POCCAR), "r" (IOP310_POCCDR));
-
- return val;
-}
-
-static int
-iop310_pri_read_config(struct pci_bus *bus, unsigned int devfn, int where,
- int size, u32 *value)
-{
- unsigned long addr = iop310_cfg_address(bus, devfn, where);
- u32 val = iop310_pri_read(addr) >> ((where & 3) * 8);
-
- if (iop310_pri_pci_status())
- val = 0xffffffff;
-
- *value = val;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-iop310_pri_write_config(struct pci_bus *bus, unsigned int devfn, int where,
- int size, u32 value)
-{
- unsigned long addr = iop310_cfg_address(bus, devfn, where);
- u32 val;
-
- if (size != 4) {
- val = iop310_pri_read(addr);
- if (!iop310_pri_pci_status() == 0)
- return PCIBIOS_SUCCESSFUL;
-
- where = (where & 3) * 8;
-
- if (size == 1)
- val &= ~(0xff << where);
- else
- val &= ~(0xffff << where);
-
- *IOP310_POCCDR = val | value << where;
- } else {
- asm volatile(
- "str %1, [%2]\n\t"
- "str %0, [%3]\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- :
- : "r" (value), "r" (addr),
- "r" (IOP310_POCCAR), "r" (IOP310_POCCDR));
- }
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static struct pci_ops iop310_primary_ops = {
- .read = iop310_pri_read_config,
- .write = iop310_pri_write_config,
-};
-
-/*
- * Secondary PCI interface support.
- */
-static int iop310_sec_pci_status(void)
-{
- unsigned int usr, uisr;
- int ret = 0;
-
- usr = *IOP310_SATUSR;
- uisr = *IOP310_SATUISR;
- if (usr & 0xf900) {
- *IOP310_SATUSR = usr & 0xf900;
- ret = 1;
- }
- if (uisr & 0x0000069f) {
- *IOP310_SATUISR = uisr & 0x0000069f;
- ret = 1;
- }
- if (ret)
- DBG("ERROR (%08x %08x)", usr, uisr);
- return ret;
-}
-
-/*
- * Simply write the address register and read the configuration
- * data. Note that the 4 nop's ensure that we are able to handle
- * a delayed abort (in theory.)
- */
-static inline u32 iop310_sec_read(unsigned long addr)
-{
- u32 val;
-
- __asm__ __volatile__(
- "str %1, [%2]\n\t"
- "ldr %0, [%3]\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- : "=r" (val)
- : "r" (addr), "r" (IOP310_SOCCAR), "r" (IOP310_SOCCDR));
-
- return val;
-}
-
-static int
-iop310_sec_read_config(struct pci_bus *bus, unsigned int devfn, int where,
- int size, u32 *value)
-{
- unsigned long addr = iop310_cfg_address(bus, devfn, where);
- u32 val = iop310_sec_read(addr) >> ((where & 3) * 8);
-
- if (iop310_sec_pci_status())
- val = 0xffffffff;
-
- *value = val;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-iop310_sec_write_config(struct pci_bus *bus, unsigned int devfn, int where,
- int size, u32 value)
-{
- unsigned long addr = iop310_cfg_address(bus, devfn, where);
- u32 val;
-
- if (size != 4) {
- val = iop310_sec_read(addr);
-
- if (!iop310_sec_pci_status() == 0)
- return PCIBIOS_SUCCESSFUL;
-
- where = (where & 3) * 8;
-
- if (size == 1)
- val &= ~(0xff << where);
- else
- val &= ~(0xffff << where);
-
- *IOP310_SOCCDR = val | value << where;
- } else {
- asm volatile(
- "str %1, [%2]\n\t"
- "str %0, [%3]\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- :
- : "r" (value), "r" (addr),
- "r" (IOP310_SOCCAR), "r" (IOP310_SOCCDR));
- }
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static struct pci_ops iop310_secondary_ops = {
- .read = iop310_sec_read_config,
- .write = iop310_sec_write_config,
-};
-
-/*
- * When a PCI device does not exist during config cycles, the 80200 gets
- * an external abort instead of returning 0xffffffff. If it was an
- * imprecise abort, we need to correct the return address to point after
- * the instruction. Also note that the Xscale manual says:
- *
- * "if a stall-until-complete LD or ST instruction triggers an
- * imprecise fault, then that fault will be seen by the program
- * within 3 instructions."
- *
- * This does not appear to be the case. With 8 NOPs after the load, we
- * see the imprecise abort occurring on the STM of iop310_sec_pci_status()
- * which is about 10 instructions away.
- *
- * Always trust reality!
- */
-static int
-iop310_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
-{
- DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n",
- addr, fsr, regs->ARM_pc, regs->ARM_lr);
-
- /*
- * If it was an imprecise abort, then we need to correct the
- * return address to be _after_ the instruction.
- */
- if (fsr & (1 << 10))
- regs->ARM_pc += 4;
-
- return 0;
-}
-
-/*
- * Scan an IOP310 PCI bus. sys->bus defines which bus we scan.
- */
-struct pci_bus *iop310_scan_bus(int nr, struct pci_sys_data *sys)
-{
- struct pci_ops *ops;
-
- if (nr)
- ops = &iop310_secondary_ops;
- else
- ops = &iop310_primary_ops;
-
- return pci_scan_bus(sys->busnr, ops, sys);
-}
-
-/*
- * Setup the system data for controller 'nr'. Return 0 if none found,
- * 1 if found, or negative error.
- *
- * We can alter:
- * io_offset - offset between IO resources and PCI bus BARs
- * mem_offset - offset between mem resources and PCI bus BARs
- * resource[0] - parent IO resource
- * resource[1] - parent non-prefetchable memory resource
- * resource[2] - parent prefetchable memory resource
- * swizzle - bridge swizzling function
- * map_irq - irq mapping function
- *
- * Note that 'io_offset' and 'mem_offset' are left as zero since
- * the IOP310 doesn't attempt to perform any address translation
- * on accesses from the host to the bus.
- */
-int iop310_setup(int nr, struct pci_sys_data *sys)
-{
- struct resource *res;
-
- if (nr >= 2)
- return 0;
-
- res = kmalloc(sizeof(struct resource) * 2, GFP_KERNEL);
- if (!res)
- panic("PCI: unable to alloc resources");
-
- memset(res, 0, sizeof(struct resource) * 2);
-
- switch (nr) {
- case 0:
- res[0].start = IOP310_PCIPRI_LOWER_IO + 0x6e000000;
- res[0].end = IOP310_PCIPRI_LOWER_IO + 0x6e00ffff;
- res[0].name = "PCI IO Primary";
- res[0].flags = IORESOURCE_IO;
-
- res[1].start = IOP310_PCIPRI_LOWER_MEM;
- res[1].end = IOP310_PCIPRI_LOWER_MEM + IOP310_PCI_WINDOW_SIZE;
- res[1].name = "PCI Memory Primary";
- res[1].flags = IORESOURCE_MEM;
- break;
-
- case 1:
- res[0].start = IOP310_PCISEC_LOWER_IO + 0x6e000000;
- res[0].end = IOP310_PCISEC_LOWER_IO + 0x6e00ffff;
- res[0].name = "PCI IO Secondary";
- res[0].flags = IORESOURCE_IO;
-
- res[1].start = IOP310_PCISEC_LOWER_MEM;
- res[1].end = IOP310_PCISEC_LOWER_MEM + IOP310_PCI_WINDOW_SIZE;
- res[1].name = "PCI Memory Secondary";
- res[1].flags = IORESOURCE_MEM;
- break;
- }
-
- request_resource(&ioport_resource, &res[0]);
- request_resource(&iomem_resource, &res[1]);
-
- sys->resource[0] = &res[0];
- sys->resource[1] = &res[1];
- sys->resource[2] = NULL;
- sys->io_offset = 0x6e000000;
-
- return 1;
-}
-
-void iop310_init(void)
-{
- DBG("PCI: Intel 80312 PCI-to-PCI init code.\n");
- DBG(" ATU secondary: ATUCR =0x%08x\n", *IOP310_ATUCR);
- DBG(" ATU secondary: SOMWVR=0x%08x SOIOWVR=0x%08x\n",
- *IOP310_SOMWVR, *IOP310_SOIOWVR);
- DBG(" ATU secondary: SIABAR=0x%08x SIALR =0x%08x SIATVR=%08x\n",
- *IOP310_SIABAR, *IOP310_SIALR, *IOP310_SIATVR);
- DBG(" ATU primary: POMWVR=0x%08x POIOWVR=0x%08x\n",
- *IOP310_POMWVR, *IOP310_POIOWVR);
- DBG(" ATU primary: PIABAR=0x%08x PIALR =0x%08x PIATVR=%08x\n",
- *IOP310_PIABAR, *IOP310_PIALR, *IOP310_PIATVR);
- DBG(" P2P: PCR=0x%04x BCR=0x%04x EBCR=0x%04x\n",
- *IOP310_PCR, *IOP310_BCR, *IOP310_EBCR);
-
- /*
- * Windows have to be carefully opened via a nice set of calls
- * here or just some direct register fiddling in the board
- * specific init when we want transactions to occur between the
- * two PCI hoses.
- *
- * To do this, we will have manage RETRY assertion between the
- * firmware and the kernel. This will ensure that the host
- * system's enumeration code is held off until we have tweaked
- * the interrupt routing and public/private IDSELs.
- *
- * For now we will simply default to disabling the integrated type
- * 81 P2P bridge.
- */
- *IOP310_PCR &= 0xfff8;
-
- hook_fault_code(16+6, iop310_pci_abort, SIGBUS, "imprecise external abort");
-}
: "r" (value), "r" (addr),
"r" (IOP321_OCCAR), "r" (IOP321_OCCDR));
}
+ return PCIBIOS_SUCCESSFUL;
}
static struct pci_ops iop321_ops = {
void __init iop321_init_time(void)
{
u32 timer_ctl;
- u32 latch = LATCH;
+/* u32 latch = LATCH; */
gettimeoffset = iop321_gettimeoffset;
setup_irq(IRQ_IOP321_TIMER0, &iop321_timer_irq);
+++ /dev/null
-/*
- * linux/arch/arm/mach-iop3xx/iq80310-irq.c
- *
- * IRQ hadling/demuxing for IQ80310 board
- *
- * Author: Nicolas Pitre
- * Copyright: (C) 2001 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * 2.4.7-rmk1-iop310.1
- * Moved demux from asm to C - DS
- * Fixes for various revision boards - DS
- */
-#include <linux/init.h>
-#include <linux/list.h>
-
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
-#include <asm/hardware.h>
-#include <asm/system.h>
-
-extern void iop310_init_irq(void);
-extern void iop310_irq_demux(unsigned int, struct irqdesc *, struct pt_regs *);
-
-static void iq80310_irq_mask(unsigned int irq)
-{
- *(volatile char *)IQ80310_INT_MASK |= (1 << (irq - IQ80310_IRQ_OFS));
-}
-
-static void iq80310_irq_unmask(unsigned int irq)
-{
- *(volatile char *)IQ80310_INT_MASK &= ~(1 << (irq - IQ80310_IRQ_OFS));
-}
-
-static struct irqchip iq80310_irq_chip = {
- .ack = iq80310_irq_mask,
- .mask = iq80310_irq_mask,
- .unmask = iq80310_irq_unmask,
-};
-
-extern struct irqchip ext_chip;
-
-static void
-iq80310_cpld_irq_handler(unsigned int irq, struct irqdesc *desc,
- struct pt_regs *regs)
-{
- unsigned int irq_stat = *(volatile u8*)IQ80310_INT_STAT;
- unsigned int irq_mask = *(volatile u8*)IQ80310_INT_MASK;
- unsigned int i, handled = 0;
- struct irqdesc *d;
-
- desc->chip->ack(irq);
-
- /*
- * Mask out the interrupts which aren't enabled.
- */
- irq_stat &= 0x1f & ~irq_mask;
-
- /*
- * Test each IQ80310 CPLD interrupt
- */
- for (i = IRQ_IQ80310_TIMER, d = irq_desc + IRQ_IQ80310_TIMER;
- irq_stat; i++, d++, irq_stat >>= 1)
- if (irq_stat & 1) {
- d->handle(i, d, regs);
- handled++;
- }
-
- /*
- * If running on a board later than REV D.1, we can
- * decode the PCI interrupt status.
- */
- if (system_rev) {
- irq_stat = *((volatile u8*)IQ80310_PCI_INT_STAT) & 7;
-
- for (i = IRQ_IQ80310_INTA, d = irq_desc + IRQ_IQ80310_INTA;
- irq_stat; i++, d++, irq_stat >>= 1)
- if (irq_stat & 0x1) {
- d->handle(i, d, regs);
- handled++;
- }
- }
-
- /*
- * If on a REV D.1 or lower board, we just assumed INTA
- * since PCI is not routed, and it may actually be an
- * on-chip interrupt.
- *
- * Note that we're giving on-chip interrupts slightly
- * higher priority than PCI by handling them first.
- *
- * On boards later than REV D.1, if we didn't read a
- * CPLD interrupt, we assume it's from a device on the
- * chipset itself.
- */
- if (system_rev == 0 || handled == 0)
- iop310_irq_demux(irq, desc, regs);
-
- desc->chip->unmask(irq);
-}
-
-void __init iq80310_init_irq(void)
-{
- volatile char *mask = (volatile char *)IQ80310_INT_MASK;
- unsigned int i;
-
- iop310_init_irq();
-
- /*
- * Setup PIRSR to route PCI interrupts into xs80200
- */
- *IOP310_PIRSR = 0xff;
-
- /*
- * Setup the IRQs in the FE820000/FE860000 registers
- */
- for (i = IQ80310_IRQ_OFS; i <= IRQ_IQ80310_INTD; i++) {
- set_irq_chip(i, &iq80310_irq_chip);
- set_irq_handler(i, do_level_IRQ);
- set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
- }
-
- /*
- * Setup the PCI IRQs
- */
- for (i = IRQ_IQ80310_INTA; i < IRQ_IQ80310_INTC; i++) {
- set_irq_chip(i, &ext_chip);
- set_irq_handler(i, do_level_IRQ);
- set_irq_flags(i, IRQF_VALID);
- }
-
- *mask = 0xff; /* mask all sources */
-
- set_irq_chained_handler(IRQ_XS80200_EXTIRQ,
- &iq80310_cpld_irq_handler);
-}
+++ /dev/null
-/*
- * arch/arm/mach-iop3xx/iq80310-pci.c
- *
- * PCI support for the Intel IQ80310 reference board
- *
- * Matt Porter <mporter@mvista.com>
- *
- * Copyright (C) 2001 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/init.h>
-
-#include <asm/hardware.h>
-#include <asm/irq.h>
-#include <asm/mach/pci.h>
-#include <asm/mach-types.h>
-
-/*
- * The following macro is used to lookup irqs in a standard table
- * format for those systems that do not already have PCI
- * interrupts properly routed. We assume 1 <= pin <= 4
- */
-#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \
-({ int _ctl_ = -1; \
- unsigned int _idsel = idsel - minid; \
- if (_idsel <= maxid) \
- _ctl_ = pci_irq_table[_idsel][pin-1]; \
- _ctl_; })
-
-#define INTA IRQ_IQ80310_INTA
-#define INTB IRQ_IQ80310_INTB
-#define INTC IRQ_IQ80310_INTC
-#define INTD IRQ_IQ80310_INTD
-
-#define INTE IRQ_IQ80310_I82559
-
-typedef u8 irq_table[4];
-
-/*
- * IRQ tables for primary bus.
- *
- * On a Rev D.1 and older board, INT A-C are not routed, so we
- * just fake it as INTA and than we take care of handling it
- * correctly in the IRQ demux routine.
- */
-static irq_table pci_pri_d_irq_table[] = {
-/* Pin: A B C D */
- { INTA, INTD, INTA, INTA }, /* PCI Slot J3 */
- { INTD, INTA, INTA, INTA }, /* PCI Slot J4 */
-};
-
-static irq_table pci_pri_f_irq_table[] = {
-/* Pin: A B C D */
- { INTC, INTD, INTA, INTB }, /* PCI Slot J3 */
- { INTD, INTA, INTB, INTC }, /* PCI Slot J4 */
-};
-
-static int __init
-iq80310_pri_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
-{
- irq_table *pci_irq_table;
-
- BUG_ON(pin < 1 || pin > 4);
-
- if (!system_rev) {
- pci_irq_table = pci_pri_d_irq_table;
- } else {
- pci_irq_table = pci_pri_f_irq_table;
- }
-
- return PCI_IRQ_TABLE_LOOKUP(2, 3);
-}
-
-/*
- * IRQ tables for secondary bus.
- *
- * On a Rev D.1 and older board, INT A-C are not routed, so we
- * just fake it as INTA and than we take care of handling it
- * correctly in the IRQ demux routine.
- */
-static irq_table pci_sec_d_irq_table[] = {
-/* Pin: A B C D */
- { INTA, INTA, INTA, INTD }, /* PCI Slot J1 */
- { INTA, INTA, INTD, INTA }, /* PCI Slot J5 */
- { INTE, INTE, INTE, INTE }, /* P2P Bridge */
-};
-
-static irq_table pci_sec_f_irq_table[] = {
-/* Pin: A B C D */
- { INTA, INTB, INTC, INTD }, /* PCI Slot J1 */
- { INTB, INTC, INTD, INTA }, /* PCI Slot J5 */
- { INTE, INTE, INTE, INTE }, /* P2P Bridge */
-};
-
-static int __init
-iq80310_sec_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
-{
- irq_table *pci_irq_table;
-
- BUG_ON(pin < 1 || pin > 4);
-
- if (!system_rev) {
- pci_irq_table = pci_sec_d_irq_table;
- } else {
- pci_irq_table = pci_sec_f_irq_table;
- }
-
- return PCI_IRQ_TABLE_LOOKUP(0, 2);
-}
-
-static int iq80310_pri_host;
-
-static int iq80310_setup(int nr, struct pci_sys_data *sys)
-{
- switch (nr) {
- case 0:
- if (!iq80310_pri_host)
- return 0;
-
- sys->map_irq = iq80310_pri_map_irq;
- break;
-
- case 1:
- sys->map_irq = iq80310_sec_map_irq;
- break;
-
- default:
- return 0;
- }
-
- return iop310_setup(nr, sys);
-}
-
-static void iq80310_preinit(void)
-{
- iq80310_pri_host = *(volatile u32 *)IQ80310_BACKPLANE & 1;
-
- printk(KERN_INFO "PCI: IQ80310 is a%s\n",
- iq80310_pri_host ? " system controller" : "n agent");
-
- iop310_init();
-}
-
-static struct hw_pci iq80310_pci __initdata = {
- .swizzle = pci_std_swizzle,
- .nr_controllers = 2,
- .setup = iq80310_setup,
- .scan = iop310_scan_bus,
- .preinit = iq80310_preinit,
-};
-
-static int __init iq80310_pci_init(void)
-{
- if (machine_is_iq80310())
- pci_common_init(&iq80310_pci);
- return 0;
-}
-
-subsys_initcall(iq80310_pci_init);
+++ /dev/null
-/*
- * linux/arch/arm/mach-iop3xx/time-iq80310.c
- *
- * Timer functions for IQ80310 onboard timer
- *
- * Author: Nicolas Pitre
- * Copyright: (C) 2001 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/time.h>
-#include <linux/init.h>
-#include <linux/timex.h>
-
-#include <asm/hardware.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/uaccess.h>
-#include <asm/mach/irq.h>
-
-static void iq80310_write_timer (u_long val)
-{
- volatile u_char *la0 = (volatile u_char *)IQ80310_TIMER_LA0;
- volatile u_char *la1 = (volatile u_char *)IQ80310_TIMER_LA1;
- volatile u_char *la2 = (volatile u_char *)IQ80310_TIMER_LA2;
-
- *la0 = val;
- *la1 = val >> 8;
- *la2 = (val >> 16) & 0x3f;
-}
-
-static u_long iq80310_read_timer (void)
-{
- volatile u_char *la0 = (volatile u_char *)IQ80310_TIMER_LA0;
- volatile u_char *la1 = (volatile u_char *)IQ80310_TIMER_LA1;
- volatile u_char *la2 = (volatile u_char *)IQ80310_TIMER_LA2;
- volatile u_char *la3 = (volatile u_char *)IQ80310_TIMER_LA3;
- u_long b0, b1, b2, b3, val;
-
- b0 = *la0; b1 = *la1; b2 = *la2; b3 = *la3;
- b0 = (((b0 & 0x40) >> 1) | (b0 & 0x1f));
- b1 = (((b1 & 0x40) >> 1) | (b1 & 0x1f));
- b2 = (((b2 & 0x40) >> 1) | (b2 & 0x1f));
- b3 = (b3 & 0x0f);
- val = ((b0 << 0) | (b1 << 6) | (b2 << 12) | (b3 << 18));
- return val;
-}
-
-/*
- * IRQs are disabled before entering here from do_gettimeofday().
- * Note that the counter may wrap. When it does, 'elapsed' will
- * be small, but we will have a pending interrupt.
- */
-static unsigned long iq80310_gettimeoffset (void)
-{
- unsigned long elapsed, usec;
- unsigned int stat1, stat2;
-
- stat1 = *(volatile u8 *)IQ80310_INT_STAT;
- elapsed = iq80310_read_timer();
- stat2 = *(volatile u8 *)IQ80310_INT_STAT;
-
- /*
- * If an interrupt was pending before we read the timer,
- * we've already wrapped. Factor this into the time.
- * If an interrupt was pending after we read the timer,
- * it may have wrapped between checking the interrupt
- * status and reading the timer. Re-read the timer to
- * be sure its value is after the wrap.
- */
- if (stat1 & 1)
- elapsed += LATCH;
- else if (stat2 & 1)
- elapsed = LATCH + iq80310_read_timer();
-
- /*
- * Now convert them to usec.
- */
- usec = (unsigned long)(elapsed * (tick_nsec / 1000))/LATCH;
-
- return usec;
-}
-
-
-static irqreturn_t
-iq80310_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
-{
- volatile u_char *timer_en = (volatile u_char *)IQ80310_TIMER_EN;
-
- /* clear timer interrupt */
- *timer_en &= ~2;
- *timer_en |= 2;
-
- do_timer(regs);
-
- return IRQ_HANDLED;
-}
-
-extern unsigned long (*gettimeoffset)(void);
-
-static struct irqaction timer_irq = {
- .name = "timer",
- .handler = iq80310_timer_interrupt,
-};
-
-
-void __init time_init(void)
-{
- volatile u_char *timer_en = (volatile u_char *)IQ80310_TIMER_EN;
-
- gettimeoffset = iq80310_gettimeoffset;
-
- setup_irq(IRQ_IQ80310_TIMER, &timer_irq);
-
- *timer_en = 0;
- iq80310_write_timer(LATCH);
- *timer_en |= 2;
- *timer_en |= 1;
-}
+++ /dev/null
-/*
- * linux/arch/arm/mach-iop3xx/mm.c
- *
- * Low level memory initialization for IOP310 based systems
- *
- * Author: Nicolas Pitre <npitre@mvista.com>
- *
- * Copyright 2000-2001 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-#include <linux/config.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/init.h>
-
-#include <asm/io.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-
-#include <asm/mach/map.h>
-
-#ifdef CONFIG_IOP310_MU
-#include "message.h"
-#endif
-
-/*
- * Standard IO mapping for all IOP310 based systems
- */
-static struct map_desc iop80310_std_desc[] __initdata = {
- /* virtual physical length type */
- // IOP310 Memory Mapped Registers
- { 0xe8001000, 0x00001000, 0x00001000, MT_DEVICE },
- // PCI I/O Space
- { 0xfe000000, 0x90000000, 0x00020000, MT_DEVICE }
-};
-
-void __init iop310_map_io(void)
-{
- iotable_init(iop80310_std_desc, ARRAY_SIZE(iop80310_std_desc));
-}
-
-/*
- * IQ80310 specific IO mappings
- */
-#ifdef CONFIG_ARCH_IQ80310
-static struct map_desc iq80310_io_desc[] __initdata = {
- /* virtual physical length type */
- // IQ80310 On-Board Devices
- { 0xfe800000, 0xfe800000, 0x00100000, MT_DEVICE }
-};
-
-void __init iq80310_map_io(void)
-{
-#ifdef CONFIG_IOP310_MU
- /* acquiring 1MB of memory aligned on 1MB boundary for MU */
- mu_mem = __alloc_bootmem(0x100000, 0x100000, 0);
-#endif
-
- iop310_map_io();
-
- iotable_init(iq80310_io_desc, ARRAY_SIZE(iq80310_io_desc));
-}
-#endif // CONFIG_ARCH_IQ80310
-
+++ /dev/null
-/*
- * linux/arch/arm/mach-iop3xx/xs80200-irq.c
- *
- * Generic IRQ handling for the XS80200 XScale core.
- *
- * Author: Nicolas Pitre
- * Copyright: (C) 2001 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/list.h>
-
-#include <asm/mach/irq.h>
-#include <asm/irq.h>
-#include <asm/hardware.h>
-
-static void xs80200_irq_mask (unsigned int irq)
-{
- unsigned long intctl;
- asm ("mrc p13, 0, %0, c0, c0, 0" : "=r" (intctl));
- switch (irq) {
- case IRQ_XS80200_BCU: intctl &= ~(1<<3); break;
- case IRQ_XS80200_PMU: intctl &= ~(1<<2); break;
- case IRQ_XS80200_EXTIRQ: intctl &= ~(1<<1); break;
- case IRQ_XS80200_EXTFIQ: intctl &= ~(1<<0); break;
- }
- asm ("mcr p13, 0, %0, c0, c0, 0" : : "r" (intctl));
-}
-
-static void xs80200_irq_unmask (unsigned int irq)
-{
- unsigned long intctl;
- asm ("mrc p13, 0, %0, c0, c0, 0" : "=r" (intctl));
- switch (irq) {
- case IRQ_XS80200_BCU: intctl |= (1<<3); break;
- case IRQ_XS80200_PMU: intctl |= (1<<2); break;
- case IRQ_XS80200_EXTIRQ: intctl |= (1<<1); break;
- case IRQ_XS80200_EXTFIQ: intctl |= (1<<0); break;
- }
- asm ("mcr p13, 0, %0, c0, c0, 0" : : "r" (intctl));
-}
-
-static struct irqchip xs80200_chip = {
- .ack = xs80200_irq_mask,
- .mask = xs80200_irq_mask,
- .unmask = xs80200_irq_unmask,
-};
-
-void __init xs80200_init_irq(void)
-{
- unsigned int i;
-
- asm("mcr p13, 0, %0, c0, c0, 0" : : "r" (0));
-
- for (i = 0; i < NR_XS80200_IRQS; i++) {
- set_irq_chip(i, &xs80200_chip);
- set_irq_handler(i, do_level_IRQ);
- set_irq_flags(i, IRQF_VALID);
- }
-}
/*
- * linux/include/asm-arm/arch-iop80310/dma.h
+ * linux/include/asm-arm/arch-iop3xx/dma.h
*
- * Copyright (C) 2001 MontaVista Software, Inc.
+ * Copyright (C) 2004 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-#ifndef _IOP310_DMA_H_
-#define _IOP310_DMA_H_
+#ifndef _IOP3XX_DMA_H_P
+#define _IOP3XX_DMA_H_P
-/* 2 DMA on primary PCI and 1 on secondary for 80310 */
-#define MAX_IOP310_DMA_CHANNEL 3
+/* 80310 not supported */
+#define MAX_IOP3XX_DMA_CHANNEL 2
#define MAX_DMA_DESC 64 /*128 */
+#define DMA_FREE 0x0
+#define DMA_ACTIVE 0x1
+#define DMA_COMPLETE 0x2
+#define DMA_ERROR 0x4
+
/*
* Make the generic DMA bits go away since we don't use it
*/
#define MAX_DMA_ADDRESS 0xffffffff
-#define IOP310_DMA_P0 0
-#define IOP310_DMA_P1 1
-#define IOP310_DMA_S0 2
-
-#define DMA_MOD_READ 0x0001
-#define DMA_MOD_WRITE 0x0002
-#define DMA_MOD_CACHED 0x0004
-#define DMA_MOD_NONCACHED 0x0008
-
-
-#define DMA_DESC_DONE 0x0010
-#define DMA_INCOMPLETE 0x0020
-#define DMA_HOLD 0x0040
-#define DMA_END_CHAIN 0x0080
-#define DMA_COMPLETE 0x0100
-#define DMA_NOTIFY 0x0200
-#define DMA_NEW_HEAD 0x0400
-
-#define DMA_USER_MASK (DMA_NOTIFY | DMA_INCOMPLETE | \
- DMA_HOLD | DMA_COMPLETE)
+#define DMA_POLL 0x0
+#define DMA_INTERRUPT 0x1
+#define DMA_DCR_MTM 0x00000040 /* memory to memory transfer */
#define DMA_DCR_DAC 0x00000020 /* Dual Addr Cycle Enab */
#define DMA_DCR_IE 0x00000010 /* Interrupt Enable */
#define DMA_DCR_PCI_IOR 0x00000002 /* I/O Read */
#define DMA_DCR_PCI_MRL 0x0000000E /* Memory Read Line */
#define DMA_DCR_PCI_MWI 0x0000000F /* Mem Write and Inval */
-#define DMA_USER_CMD_IE 0x00000001 /* user request int */
-#define DMA_USER_END_CHAIN 0x00000002 /* end of sgl chain flag */
-
-/* ATU defines */
-#define IOP310_ATUCR_PRIM_OUT_ENAB /* Configuration */ 0x00000002
-#define IOP310_ATUCR_DIR_ADDR_ENAB /* Configuration */ 0x00000080
-
-
-typedef void (*dma_callback_t) (void *buf_context);
-/*
- * DMA Descriptor
- */
-typedef struct _dma_desc
-{
- u32 NDAR; /* next descriptor address */
- u32 PDAR; /* PCI address */
- u32 PUADR; /* upper PCI address */
- u32 LADR; /* local address */
- u32 BC; /* byte count */
- u32 DC; /* descriptor control */
-} dma_desc_t;
-
-typedef struct _dma_sgl
-{
- dma_desc_t dma_desc; /* DMA descriptor pointer */
- u32 status; /* descriptor status */
- void *data; /* local virt */
- struct _dma_sgl *next; /* next descriptor */
-} dma_sgl_t;
-
-/* dma sgl head */
-typedef struct _dma_head
-{
- u32 total; /* total elements in SGL */
- u32 status; /* status of sgl */
- u32 mode; /* read or write mode */
- dma_sgl_t *list; /* pointer to list */
- dma_callback_t callback; /* callback function */
-} dma_head_t;
+//extern iop3xx_dma_t dma_chan[2];
/* function prototypes */
-int dma_request(dmach_t, const char *);
-int dma_queue_buffer(dmach_t, dma_head_t *);
-int dma_suspend(dmach_t);
-int dma_resume(dmach_t);
-int dma_flush_all(dmach_t);
-void dma_free(dmach_t);
-void dma_set_irq_threshold(dmach_t, int);
-dma_sgl_t *dma_get_buffer(dmach_t, int);
-void dma_return_buffer(dmach_t, dma_sgl_t *);
+#ifdef CONFIG_IOP3XX_DMACOPY
+extern int iop_memcpy;
+void * dma_memcpy(void * to, const void* from, __kernel_size_t n);
+#endif
-#endif /* _ASM_ARCH_DMA_H */
+#endif /* _ASM_ARCH_DMA_H_P */
/*
- * linux/include/asm-arm/arch-iop80310/hardware.h
+ * linux/include/asm-arm/arch-iop3xx/hardware.h
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
* The PCI IO space is located at virtual 0xfe000000 from physical
* 0x90000000. The PCI BARs must be programmed with physical addresses,
* but when we read them, we convert them to virtual addresses. See
- * arch/arm/mach-iop310/iop310-pci.c
+ * arch/arm/mach-iop3xx/iop3XX-pci.c
*/
#define pcibios_assign_all_busses() 1
-#ifdef CONFIG_ARCH_IOP310
-/*
- * these are the values for the secondary PCI bus on the 80312 chip. I will
- * have to do some fixup in the bus/dev fixup code
- */
-#define PCIBIOS_MIN_IO 0
-#define PCIBIOS_MIN_MEM 0x88000000
-
-// Generic chipset bits
-#include "iop310.h"
-
-// Board specific
-#if defined(CONFIG_ARCH_IQ80310)
-#include "iq80310.h"
-#endif
-#endif
-
#ifdef CONFIG_ARCH_IOP321
#define PCIBIOS_MIN_IO 0x90000000
+++ /dev/null
-/*
- * linux/include/asm-arm/arch-iop310/irqs.h
- *
- * Author: Nicolas Pitre
- * Copyright: (C) 2001 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * 06/13/01: Added 80310 on-chip interrupt sources <dsaxena@mvista.com>
- *
- */
-#include <linux/config.h>
-
-/*
- * XS80200 specific IRQs
- */
-#define IRQ_XS80200_BCU 0 /* Bus Control Unit */
-#define IRQ_XS80200_PMU 1 /* Performance Monitoring Unit */
-#define IRQ_XS80200_EXTIRQ 2 /* external IRQ signal */
-#define IRQ_XS80200_EXTFIQ 3 /* external IRQ signal */
-
-#define NR_XS80200_IRQS 4
-
-#define XSCALE_PMU_IRQ IRQ_XS80200_PMU
-
-/*
- * IOP80310 chipset interrupts
- */
-#define IOP310_IRQ_OFS NR_XS80200_IRQS
-#define IOP310_IRQ(x) (IOP310_IRQ_OFS + (x))
-
-/*
- * On FIQ1ISR register
- */
-#define IRQ_IOP310_DMA0 IOP310_IRQ(0) /* DMA Channel 0 */
-#define IRQ_IOP310_DMA1 IOP310_IRQ(1) /* DMA Channel 1 */
-#define IRQ_IOP310_DMA2 IOP310_IRQ(2) /* DMA Channel 2 */
-#define IRQ_IOP310_PMON IOP310_IRQ(3) /* Bus performance Unit */
-#define IRQ_IOP310_AAU IOP310_IRQ(4) /* Application Accelator Unit */
-
-/*
- * On FIQ2ISR register
- */
-#define IRQ_IOP310_I2C IOP310_IRQ(5) /* I2C unit */
-#define IRQ_IOP310_MU IOP310_IRQ(6) /* messaging unit */
-
-#define NR_IOP310_IRQS (IOP310_IRQ(6) + 1)
-
-#define NR_IRQS NR_IOP310_IRQS
-
-
-/*
- * Interrupts available on the Cyclone IQ80310 board
- */
-#ifdef CONFIG_ARCH_IQ80310
-
-#define IQ80310_IRQ_OFS NR_IOP310_IRQS
-#define IQ80310_IRQ(y) ((IQ80310_IRQ_OFS) + (y))
-
-#define IRQ_IQ80310_TIMER IQ80310_IRQ(0) /* Timer Interrupt */
-#define IRQ_IQ80310_I82559 IQ80310_IRQ(1) /* I82559 Ethernet Interrupt */
-#define IRQ_IQ80310_UART1 IQ80310_IRQ(2) /* UART1 Interrupt */
-#define IRQ_IQ80310_UART2 IQ80310_IRQ(3) /* UART2 Interrupt */
-#define IRQ_IQ80310_INTD IQ80310_IRQ(4) /* PCI INTD */
-
-
-/*
- * ONLY AVAILABLE ON REV F OR NEWER BOARDS!
- */
-#define IRQ_IQ80310_INTA IQ80310_IRQ(5) /* PCI INTA */
-#define IRQ_IQ80310_INTB IQ80310_IRQ(6) /* PCI INTB */
-#define IRQ_IQ80310_INTC IQ80310_IRQ(7) /* PCI INTC */
-
-#undef NR_IRQS
-#define NR_IRQS (IQ80310_IRQ(7) + 1)
-
-#endif // CONFIG_ARCH_IQ80310
-
+++ /dev/null
-/*
- * linux/include/asm/arch-iop3xx/iop310.h
- *
- * Intel IOP310 Companion Chip definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _IOP310_HW_H_
-#define _IOP310_HW_H_
-
-/*
- * This is needed for mixed drivers that need to work on all
- * IOP3xx variants but behave slightly differently on each.
- */
-#ifndef __ASSEMBLY__
-#define iop_is_310() ((processor_id & 0xffffe3f0) == 0x69052000)
-#endif
-
-/*
- * IOP310 I/O and Mem space regions for PCI autoconfiguration
- */
-#define IOP310_PCISEC_LOWER_IO 0x90010000
-#define IOP310_PCISEC_UPPER_IO 0x9001ffff
-#define IOP310_PCISEC_LOWER_MEM 0x88000000
-#define IOP310_PCISEC_UPPER_MEM 0x8bffffff
-
-#define IOP310_PCIPRI_LOWER_IO 0x90000000
-#define IOP310_PCIPRI_UPPER_IO 0x9000ffff
-#define IOP310_PCIPRI_LOWER_MEM 0x80000000
-#define IOP310_PCIPRI_UPPER_MEM 0x83ffffff
-
-#define IOP310_PCI_WINDOW_SIZE 64 * 0x100000
-
-/*
- * IOP310 chipset registers
- */
-#define IOP310_VIRT_MEM_BASE 0xe8001000 /* chip virtual mem address*/
-#define IOP310_PHY_MEM_BASE 0x00001000 /* chip physical memory address */
-#define IOP310_REG_ADDR(reg) (IOP310_VIRT_MEM_BASE | IOP310_PHY_MEM_BASE | (reg))
-
-/* PCI-to-PCI Bridge Unit 0x00001000 through 0x000010FF */
-#define IOP310_VIDR (volatile u16 *)IOP310_REG_ADDR(0x00001000)
-#define IOP310_DIDR (volatile u16 *)IOP310_REG_ADDR(0x00001002)
-#define IOP310_PCR (volatile u16 *)IOP310_REG_ADDR(0x00001004)
-#define IOP310_PSR (volatile u16 *)IOP310_REG_ADDR(0x00001006)
-#define IOP310_RIDR (volatile u8 *)IOP310_REG_ADDR(0x00001008)
-#define IOP310_CCR (volatile u32 *)IOP310_REG_ADDR(0x00001009)
-#define IOP310_CLSR (volatile u8 *)IOP310_REG_ADDR(0x0000100C)
-#define IOP310_PLTR (volatile u8 *)IOP310_REG_ADDR(0x0000100D)
-#define IOP310_HTR (volatile u8 *)IOP310_REG_ADDR(0x0000100E)
-/* Reserved 0x0000100F through 0x00001017 */
-#define IOP310_PBNR (volatile u8 *)IOP310_REG_ADDR(0x00001018)
-#define IOP310_SBNR (volatile u8 *)IOP310_REG_ADDR(0x00001019)
-#define IOP310_SUBBNR (volatile u8 *)IOP310_REG_ADDR(0x0000101A)
-#define IOP310_SLTR (volatile u8 *)IOP310_REG_ADDR(0x0000101B)
-#define IOP310_IOBR (volatile u8 *)IOP310_REG_ADDR(0x0000101C)
-#define IOP310_IOLR (volatile u8 *)IOP310_REG_ADDR(0x0000101D)
-#define IOP310_SSR (volatile u16 *)IOP310_REG_ADDR(0x0000101E)
-#define IOP310_MBR (volatile u16 *)IOP310_REG_ADDR(0x00001020)
-#define IOP310_MLR (volatile u16 *)IOP310_REG_ADDR(0x00001022)
-#define IOP310_PMBR (volatile u16 *)IOP310_REG_ADDR(0x00001024)
-#define IOP310_PMLR (volatile u16 *)IOP310_REG_ADDR(0x00001026)
-/* Reserved 0x00001028 through 0x00001033 */
-#define IOP310_CAPR (volatile u8 *)IOP310_REG_ADDR(0x00001034)
-/* Reserved 0x00001035 through 0x0000103D */
-#define IOP310_BCR (volatile u16 *)IOP310_REG_ADDR(0x0000103E)
-#define IOP310_EBCR (volatile u16 *)IOP310_REG_ADDR(0x00001040)
-#define IOP310_SISR (volatile u16 *)IOP310_REG_ADDR(0x00001042)
-#define IOP310_PBISR (volatile u32 *)IOP310_REG_ADDR(0x00001044)
-#define IOP310_SBISR (volatile u32 *)IOP310_REG_ADDR(0x00001048)
-#define IOP310_SACR (volatile u32 *)IOP310_REG_ADDR(0x0000104C)
-#define IOP310_PIRSR (volatile u32 *)IOP310_REG_ADDR(0x00001050)
-#define IOP310_SIOBR (volatile u8 *)IOP310_REG_ADDR(0x00001054)
-#define IOP310_SIOLR (volatile u8 *)IOP310_REG_ADDR(0x00001055)
-#define IOP310_SCDR (volatile u8 *)IOP310_REG_ADDR(0x00001056)
-
-#define IOP310_SMBR (volatile u16 *)IOP310_REG_ADDR(0x00001058)
-#define IOP310_SMLR (volatile u16 *)IOP310_REG_ADDR(0x0000105A)
-#define IOP310_SDER (volatile u16 *)IOP310_REG_ADDR(0x0000105C)
-#define IOP310_QCR (volatile u16 *)IOP310_REG_ADDR(0x0000105E)
-#define IOP310_CAPID (volatile u8 *)IOP310_REG_ADDR(0x00001068)
-#define IOP310_NIPTR (volatile u8 *)IOP310_REG_ADDR(0x00001069)
-#define IOP310_PMCR (volatile u16 *)IOP310_REG_ADDR(0x0000106A)
-#define IOP310_PMCSR (volatile u16 *)IOP310_REG_ADDR(0x0000106C)
-#define IOP310_PMCSRBSE (volatile u8 *)IOP310_REG_ADDR(0x0000106E)
-/* Reserved 0x00001064 through 0x000010FFH */
-
-/* Performance monitoring unit 0x00001100 through 0x000011FF*/
-#define IOP310_PMONGTMR (volatile u32 *)IOP310_REG_ADDR(0x00001100)
-#define IOP310_PMONESR (volatile u32 *)IOP310_REG_ADDR(0x00001104)
-#define IOP310_PMONEMISR (volatile u32 *)IOP310_REG_ADDR(0x00001108)
-#define IOP310_PMONGTSR (volatile u32 *)IOP310_REG_ADDR(0x00001110)
-#define IOP310_PMONPECR1 (volatile u32 *)IOP310_REG_ADDR(0x00001114)
-#define IOP310_PMONPECR2 (volatile u32 *)IOP310_REG_ADDR(0x00001118)
-#define IOP310_PMONPECR3 (volatile u32 *)IOP310_REG_ADDR(0x0000111C)
-#define IOP310_PMONPECR4 (volatile u32 *)IOP310_REG_ADDR(0x00001120)
-#define IOP310_PMONPECR5 (volatile u32 *)IOP310_REG_ADDR(0x00001124)
-#define IOP310_PMONPECR6 (volatile u32 *)IOP310_REG_ADDR(0x00001128)
-#define IOP310_PMONPECR7 (volatile u32 *)IOP310_REG_ADDR(0x0000112C)
-#define IOP310_PMONPECR8 (volatile u32 *)IOP310_REG_ADDR(0x00001130)
-#define IOP310_PMONPECR9 (volatile u32 *)IOP310_REG_ADDR(0x00001134)
-#define IOP310_PMONPECR10 (volatile u32 *)IOP310_REG_ADDR(0x00001138)
-#define IOP310_PMONPECR11 (volatile u32 *)IOP310_REG_ADDR(0x0000113C)
-#define IOP310_PMONPECR12 (volatile u32 *)IOP310_REG_ADDR(0x00001140)
-#define IOP310_PMONPECR13 (volatile u32 *)IOP310_REG_ADDR(0x00001144)
-#define IOP310_PMONPECR14 (volatile u32 *)IOP310_REG_ADDR(0x00001148)
-
-/* Address Translation Unit 0x00001200 through 0x000012FF */
-#define IOP310_ATUVID (volatile u16 *)IOP310_REG_ADDR(0x00001200)
-#define IOP310_ATUDID (volatile u16 *)IOP310_REG_ADDR(0x00001202)
-#define IOP310_PATUCMD (volatile u16 *)IOP310_REG_ADDR(0x00001204)
-#define IOP310_PATUSR (volatile u16 *)IOP310_REG_ADDR(0x00001206)
-#define IOP310_ATURID (volatile u8 *)IOP310_REG_ADDR(0x00001208)
-#define IOP310_ATUCCR (volatile u32 *)IOP310_REG_ADDR(0x00001209)
-#define IOP310_ATUCLSR (volatile u8 *)IOP310_REG_ADDR(0x0000120C)
-#define IOP310_ATULT (volatile u8 *)IOP310_REG_ADDR(0x0000120D)
-#define IOP310_ATUHTR (volatile u8 *)IOP310_REG_ADDR(0x0000120E)
-
-#define IOP310_PIABAR (volatile u32 *)IOP310_REG_ADDR(0x00001210)
-/* Reserved 0x00001214 through 0x0000122B */
-#define IOP310_ASVIR (volatile u16 *)IOP310_REG_ADDR(0x0000122C)
-#define IOP310_ASIR (volatile u16 *)IOP310_REG_ADDR(0x0000122E)
-#define IOP310_ERBAR (volatile u32 *)IOP310_REG_ADDR(0x00001230)
-#define IOP310_ATUCAPPTR (volatile u8 *)IOP310_REG_ADDR(0x00001234)
-/* Reserved 0x00001235 through 0x0000123B */
-#define IOP310_ATUILR (volatile u8 *)IOP310_REG_ADDR(0x0000123C)
-#define IOP310_ATUIPR (volatile u8 *)IOP310_REG_ADDR(0x0000123D)
-#define IOP310_ATUMGNT (volatile u8 *)IOP310_REG_ADDR(0x0000123E)
-#define IOP310_ATUMLAT (volatile u8 *)IOP310_REG_ADDR(0x0000123F)
-#define IOP310_PIALR (volatile u32 *)IOP310_REG_ADDR(0x00001240)
-#define IOP310_PIATVR (volatile u32 *)IOP310_REG_ADDR(0x00001244)
-#define IOP310_SIABAR (volatile u32 *)IOP310_REG_ADDR(0x00001248)
-#define IOP310_SIALR (volatile u32 *)IOP310_REG_ADDR(0x0000124C)
-#define IOP310_SIATVR (volatile u32 *)IOP310_REG_ADDR(0x00001250)
-#define IOP310_POMWVR (volatile u32 *)IOP310_REG_ADDR(0x00001254)
-/* Reserved 0x00001258 through 0x0000125B */
-#define IOP310_POIOWVR (volatile u32 *)IOP310_REG_ADDR(0x0000125C)
-#define IOP310_PODWVR (volatile u32 *)IOP310_REG_ADDR(0x00001260)
-#define IOP310_POUDR (volatile u32 *)IOP310_REG_ADDR(0x00001264)
-#define IOP310_SOMWVR (volatile u32 *)IOP310_REG_ADDR(0x00001268)
-#define IOP310_SOIOWVR (volatile u32 *)IOP310_REG_ADDR(0x0000126C)
-/* Reserved 0x00001270 through 0x00001273*/
-#define IOP310_ERLR (volatile u32 *)IOP310_REG_ADDR(0x00001274)
-#define IOP310_ERTVR (volatile u32 *)IOP310_REG_ADDR(0x00001278)
-/* Reserved 0x00001279 through 0x0000127C*/
-#define IOP310_ATUCAPID (volatile u8 *)IOP310_REG_ADDR(0x00001280)
-#define IOP310_ATUNIPTR (volatile u8 *)IOP310_REG_ADDR(0x00001281)
-#define IOP310_APMCR (volatile u16 *)IOP310_REG_ADDR(0x00001282)
-#define IOP310_APMCSR (volatile u16 *)IOP310_REG_ADDR(0x00001284)
-/* Reserved 0x00001286 through 0x00001287 */
-#define IOP310_ATUCR (volatile u32 *)IOP310_REG_ADDR(0x00001288)
-/* Reserved 0x00001289 through 0x0000128C*/
-#define IOP310_PATUISR (volatile u32 *)IOP310_REG_ADDR(0x00001290)
-#define IOP310_SATUISR (volatile u32 *)IOP310_REG_ADDR(0x00001294)
-#define IOP310_SATUCMD (volatile u16 *)IOP310_REG_ADDR(0x00001298)
-#define IOP310_SATUSR (volatile u16 *)IOP310_REG_ADDR(0x0000129A)
-#define IOP310_SODWVR (volatile u32 *)IOP310_REG_ADDR(0x0000129C)
-#define IOP310_SOUDR (volatile u32 *)IOP310_REG_ADDR(0x000012A0)
-#define IOP310_POCCAR (volatile u32 *)IOP310_REG_ADDR(0x000012A4)
-#define IOP310_SOCCAR (volatile u32 *)IOP310_REG_ADDR(0x000012A8)
-#define IOP310_POCCDR (volatile u32 *)IOP310_REG_ADDR(0x000012AC)
-#define IOP310_SOCCDR (volatile u32 *)IOP310_REG_ADDR(0x000012B0)
-#define IOP310_PAQCR (volatile u32 *)IOP310_REG_ADDR(0x000012B4)
-#define IOP310_SAQCR (volatile u32 *)IOP310_REG_ADDR(0x000012B8)
-#define IOP310_PATUIMR (volatile u32 *)IOP310_REG_ADDR(0x000012BC)
-#define IOP310_SATUIMR (volatile u32 *)IOP310_REG_ADDR(0x000012C0)
-/* Reserved 0x000012C4 through 0x000012FF */
-/* Messaging Unit 0x00001300 through 0x000013FF */
-#define IOP310_MUIMR0 (volatile u32 *)IOP310_REG_ADDR(0x00001310)
-#define IOP310_MUIMR1 (volatile u32 *)IOP310_REG_ADDR(0x00001314)
-#define IOP310_MUOMR0 (volatile u32 *)IOP310_REG_ADDR(0x00001318)
-#define IOP310_MUOMR1 (volatile u32 *)IOP310_REG_ADDR(0x0000131C)
-#define IOP310_MUIDR (volatile u32 *)IOP310_REG_ADDR(0x00001320)
-#define IOP310_MUIISR (volatile u32 *)IOP310_REG_ADDR(0x00001324)
-#define IOP310_MUIIMR (volatile u32 *)IOP310_REG_ADDR(0x00001328)
-#define IOP310_MUODR (volatile u32 *)IOP310_REG_ADDR(0x0000132C)
-#define IOP310_MUOISR (volatile u32 *)IOP310_REG_ADDR(0x00001330)
-#define IOP310_MUOIMR (volatile u32 *)IOP310_REG_ADDR(0x00001334)
-#define IOP310_MUMUCR (volatile u32 *)IOP310_REG_ADDR(0x00001350)
-#define IOP310_MUQBAR (volatile u32 *)IOP310_REG_ADDR(0x00001354)
-#define IOP310_MUIFHPR (volatile u32 *)IOP310_REG_ADDR(0x00001360)
-#define IOP310_MUIFTPR (volatile u32 *)IOP310_REG_ADDR(0x00001364)
-#define IOP310_MUIPHPR (volatile u32 *)IOP310_REG_ADDR(0x00001368)
-#define IOP310_MUIPTPR (volatile u32 *)IOP310_REG_ADDR(0x0000136C)
-#define IOP310_MUOFHPR (volatile u32 *)IOP310_REG_ADDR(0x00001370)
-#define IOP310_MUOFTPR (volatile u32 *)IOP310_REG_ADDR(0x00001374)
-#define IOP310_MUOPHPR (volatile u32 *)IOP310_REG_ADDR(0x00001378)
-#define IOP310_MUOPTPR (volatile u32 *)IOP310_REG_ADDR(0x0000137C)
-#define IOP310_MUIAR (volatile u32 *)IOP310_REG_ADDR(0x00001380)
-/* DMA Controller 0x00001400 through 0x000014FF */
-#define IOP310_DMA0CCR (volatile u32 *)IOP310_REG_ADDR(0x00001400)
-#define IOP310_DMA0CSR (volatile u32 *)IOP310_REG_ADDR(0x00001404)
-/* Reserved 0x001408 through 0x00140B */
-#define IOP310_DMA0DAR (volatile u32 *)IOP310_REG_ADDR(0x0000140C)
-#define IOP310_DMA0NDAR (volatile u32 *)IOP310_REG_ADDR(0x00001410)
-#define IOP310_DMA0PADR (volatile u32 *)IOP310_REG_ADDR(0x00001414)
-#define IOP310_DMA0PUADR (volatile u32 *)IOP310_REG_ADDR(0x00001418)
-#define IOP310_DMA0LADR (volatile u32 *)IOP310_REG_ADDR(0x0000141C)
-#define IOP310_DMA0BCR (volatile u32 *)IOP310_REG_ADDR(0x00001420)
-#define IOP310_DMA0DCR (volatile u32 *)IOP310_REG_ADDR(0x00001424)
-/* Reserved 0x00001428 through 0x0000143F */
-#define IOP310_DMA1CCR (volatile u32 *)IOP310_REG_ADDR(0x00001440)
-#define IOP310_DMA1CSR (volatile u32 *)IOP310_REG_ADDR(0x00001444)
-/* Reserved 0x00001448 through 0x0000144B */
-#define IOP310_DMA1DAR (volatile u32 *)IOP310_REG_ADDR(0x0000144C)
-#define IOP310_DMA1NDAR (volatile u32 *)IOP310_REG_ADDR(0x00001450)
-#define IOP310_DMA1PADR (volatile u32 *)IOP310_REG_ADDR(0x00001454)
-#define IOP310_DMA1PUADR (volatile u32 *)IOP310_REG_ADDR(0x00001458)
-#define IOP310_DMA1LADR (volatile u32 *)IOP310_REG_ADDR(0x0000145C)
-#define IOP310_DMA1BCR (volatile u32 *)IOP310_REG_ADDR(0x00001460)
-#define IOP310_DMA1DCR (volatile u32 *)IOP310_REG_ADDR(0x00001464)
-/* Reserved 0x00001468 through 0x0000147F */
-#define IOP310_DMA2CCR (volatile u32 *)IOP310_REG_ADDR(0x00001480)
-#define IOP310_DMA2CSR (volatile u32 *)IOP310_REG_ADDR(0x00001484)
-/* Reserved 0x00001488 through 0x0000148B */
-#define IOP310_DMA2DAR (volatile u32 *)IOP310_REG_ADDR(0x0000148C)
-#define IOP310_DMA2NDAR (volatile u32 *)IOP310_REG_ADDR(0x00001490)
-#define IOP310_DMA2PADR (volatile u32 *)IOP310_REG_ADDR(0x00001494)
-#define IOP310_DMA2PUADR (volatile u32 *)IOP310_REG_ADDR(0x00001498)
-#define IOP310_DMA2LADR (volatile u32 *)IOP310_REG_ADDR(0x0000149C)
-#define IOP310_DMA2BCR (volatile u32 *)IOP310_REG_ADDR(0x000014A0)
-#define IOP310_DMA2DCR (volatile u32 *)IOP310_REG_ADDR(0x000014A4)
-
-/* Memory controller 0x00001500 through 0x0015FF */
-
-/* core interface unit 0x00001640 - 0x0000167F */
-#define IOP310_CIUISR (volatile u32 *)IOP310_REG_ADDR(0x00001644)
-
-/* PCI and Peripheral Interrupt Controller 0x00001700 - 0x0000171B */
-#define IOP310_IRQISR (volatile u32 *)IOP310_REG_ADDR(0x00001700)
-#define IOP310_FIQ2ISR (volatile u32 *)IOP310_REG_ADDR(0x00001704)
-#define IOP310_FIQ1ISR (volatile u32 *)IOP310_REG_ADDR(0x00001708)
-#define IOP310_PDIDR (volatile u32 *)IOP310_REG_ADDR(0x00001710)
-
-/* AAU registers. DJ 0x00001800 - 0x00001838 */
-#define IOP310_AAUACR (volatile u32 *)IOP310_REG_ADDR(0x00001800)
-#define IOP310_AAUASR (volatile u32 *)IOP310_REG_ADDR(0x00001804)
-#define IOP310_AAUADAR (volatile u32 *)IOP310_REG_ADDR(0x00001808)
-#define IOP310_AAUANDAR (volatile u32 *)IOP310_REG_ADDR(0x0000180C)
-#define IOP310_AAUSAR1 (volatile u32 *)IOP310_REG_ADDR(0x00001810)
-#define IOP310_AAUSAR2 (volatile u32 *)IOP310_REG_ADDR(0x00001814)
-#define IOP310_AAUSAR3 (volatile u32 *)IOP310_REG_ADDR(0x00001818)
-#define IOP310_AAUSAR4 (volatile u32 *)IOP310_REG_ADDR(0x0000181C)
-#define IOP310_AAUDAR (volatile u32 *)IOP310_REG_ADDR(0x00001820)
-#define IOP310_AAUABCR (volatile u32 *)IOP310_REG_ADDR(0x00001824)
-#define IOP310_AAUADCR (volatile u32 *)IOP310_REG_ADDR(0x00001828)
-#define IOP310_AAUSAR5 (volatile u32 *)IOP310_REG_ADDR(0x0000182C)
-#define IOP310_AAUSAR6 (volatile u32 *)IOP310_REG_ADDR(0x00001830)
-#define IOP310_AAUSAR7 (volatile u32 *)IOP310_REG_ADDR(0x00001834)
-#define IOP310_AAUSAR8 (volatile u32 *)IOP310_REG_ADDR(0x00001838)
-
-#endif // _IOP310_HW_H_
#define IOP321_PCI_IO_BASE 0x90000000
#define IOP321_PCI_IO_SIZE 0x00010000
-#define IOP321_PCI_MEM_BASE 0x40000000
+#define IOP321_PCI_MEM_BASE 0x80000000
#define IOP321_PCI_MEM_SIZE 0x40000000
/*
+++ /dev/null
-/*
- * linux/include/asm/arch-iop80310/iq80310.h
- *
- * Intel IQ-80310 evaluation board registers
- */
-
-#ifndef _IQ80310_H_
-#define _IQ80310_H_
-
-#define IQ80310_RAMBASE 0xa0000000
-#define IQ80310_UART1 0xfe800000 /* UART #1 */
-#define IQ80310_UART2 0xfe810000 /* UART #2 */
-#define IQ80310_INT_STAT 0xfe820000 /* Interrupt (XINT3#) Status */
-#define IQ80310_BOARD_REV 0xfe830000 /* Board revision register */
-#define IQ80310_CPLD_REV 0xfe840000 /* CPLD revision register */
-#define IQ80310_7SEG_1 0xfe840000 /* 7-Segment MSB */
-#define IQ80310_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */
-#define IQ80310_PCI_INT_STAT 0xfe850000 /* PCI Interrupt Status */
-#define IQ80310_INT_MASK 0xfe860000 /* Interrupt (XINT3#) Mask */
-#define IQ80310_BACKPLANE 0xfe870000 /* Backplane Detect */
-#define IQ80310_TIMER_LA0 0xfe880000 /* Timer LA0 */
-#define IQ80310_TIMER_LA1 0xfe890000 /* Timer LA1 */
-#define IQ80310_TIMER_LA2 0xfe8a0000 /* Timer LA2 */
-#define IQ80310_TIMER_LA3 0xfe8b0000 /* Timer LA3 */
-#define IQ80310_TIMER_EN 0xfe8c0000 /* Timer Enable */
-#define IQ80310_ROTARY_SW 0xfe8d0000 /* Rotary Switch */
-#define IQ80310_JTAG 0xfe8e0000 /* JTAG Port Access */
-#define IQ80310_BATT_STAT 0xfe8f0000 /* Battery Status */
-
-#endif // _IQ80310_H_
/*
* Whic iop3xx implementation is this?
*/
-#ifdef CONFIG_ARCH_IOP310
-
-#include "iop310-irqs.h"
-
-#else
+#ifdef CONFIG_ARCH_IOP321
#include "iop321-irqs.h"
/*
- * linux/include/asm-arm/arch-iop80310/memory.h
+ * linux/include/asm-arm/arch-iop3xx/memory.h
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#include <linux/config.h>
-#include <asm/arch/iop310.h>
#include <asm/arch/iop321.h>
/*
* bus_to_virt: Used to convert an address for DMA operations
* to an address that the kernel can use.
*/
-#ifdef CONFIG_ARCH_IOP310
-
-#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP310_SIATVR)) | ((*IOP310_SIABAR) & 0xfffffff0))
-#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP310_SIALR)) | ( *IOP310_SIATVR)))
-
-#elif defined(CONFIG_ARCH_IOP321)
+#if defined(CONFIG_ARCH_IOP321)
#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP321_IATVR2)) | ((*IOP321_IABAR2) & 0xfffffff0))
#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP321_IALR2)) | ( *IOP321_IATVR2)))
#endif
-/* boot mem allocate global pointer for MU circular queues QBAR */
-#ifdef CONFIG_IOP3XX_MU
-extern void *mu_mem;
-#endif
-
#define PFN_TO_NID(addr) (0)
#endif
/*
- * linux/include/asm-arm/arch-iop80310/param.h
+ * linux/include/asm-arm/arch-iop3xx/param.h
*/
+++ /dev/null
-/*
- * Definitions for XScale 80312 PMON
- * (C) 2001 Intel Corporation
- * Author: Chen Chen(chen.chen@intel.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _IOP310_PMON_H_
-#define _IOP310_PMON_H_
-
-/*
- * Different modes for Event Select Register for intel 80312
- */
-
-#define IOP310_PMON_MODE0 0x00000000
-#define IOP310_PMON_MODE1 0x00000001
-#define IOP310_PMON_MODE2 0x00000002
-#define IOP310_PMON_MODE3 0x00000003
-#define IOP310_PMON_MODE4 0x00000004
-#define IOP310_PMON_MODE5 0x00000005
-#define IOP310_PMON_MODE6 0x00000006
-#define IOP310_PMON_MODE7 0x00000007
-
-typedef struct _iop310_pmon_result
-{
- u32 timestamp; /* Global Time Stamp Register */
- u32 timestamp_overflow; /* Time Stamp overflow count */
- u32 event_count[14]; /* Programmable Event Counter
- Registers 1-14 */
- u32 event_overflow[14]; /* Overflow counter for PECR1-14 */
-} iop310_pmon_res_t;
-
-/* function prototypes */
-
-/* Claim IQ80312 PMON for usage */
-int iop310_pmon_claim(void);
-
-/* Start IQ80312 PMON */
-int iop310_pmon_start(int, int);
-
-/* Stop Performance Monitor Unit */
-int iop310_pmon_stop(iop310_pmon_res_t *);
-
-/* Release IQ80312 PMON */
-int iop310_pmon_release(int);
-
-#endif
/* Standard COM flags */
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
-#ifdef CONFIG_ARCH_IQ80310
-
-#define IRQ_UART1 IRQ_IQ80310_UART1
-#define IRQ_UART2 IRQ_IQ80310_UART2
-
-#define STD_SERIAL_PORT_DEFNS \
- /* UART CLK PORT IRQ FLAGS */ \
- { 0, BASE_BAUD, IQ80310_UART2, IRQ_UART2, STD_COM_FLAGS }, /* ttyS0 */ \
- { 0, BASE_BAUD, IQ80310_UART1, IRQ_UART1, STD_COM_FLAGS } /* ttyS1 */
-
-#endif // CONFIG_ARCH_IQ80310
-
#ifdef CONFIG_ARCH_IQ80321
#define IRQ_UART1 IRQ_IQ80321_UART
/*
- * linux/include/asm-arm/arch-iop80310/system.h
+ * linux/include/asm-arm/arch-iop3xx/system.h
*
* Copyright (C) 2001 MontaVista Software, Inc.
*
/*
* linux/include/asm-arm/arch-iop3xx/timex.h
*
- * IOP310 architecture timex specifications
+ * IOP3xx architecture timex specifications
*/
#include <linux/config.h>
-#ifdef CONFIG_ARCH_IQ80310
-
-#ifndef CONFIG_XSCALE_PMU_TIMER
-/* This is for the on-board timer */
-#define CLOCK_TICK_RATE 33000000 /* Underlying HZ */
-#else
-/* This is for the underlying xs80200 PMU clock. We run the core @ 733MHz */
-#define CLOCK_TICK_RATE 733000000
-#endif // IQ80310
-
-#elif defined(CONFIG_ARCH_IQ80321)
+#if defined(CONFIG_ARCH_IQ80321)
#define CLOCK_TICK_RATE 200000000
/*
- * linux/include/asm-arm/arch-iop80310/uncompress.h
+ * linux/include/asm-arm/arch-iop3xx/uncompress.h
*/
#include <linux/config.h>
#include <linux/serial_reg.h>
#include <asm/hardware.h>
-#ifdef CONFIG_ARCH_IQ80310
-#define UART2_BASE ((volatile unsigned char *)IQ80310_UART2)
-#elif defined(CONFIG_ARCH_IQ80321)
+#if defined(CONFIG_ARCH_IQ80321)
#define UART2_BASE ((volatile unsigned char *)IQ80321_UART1)
#endif
/*
* PCI controllers
*/
-extern int iop310_setup(int nr, struct pci_sys_data *);
-extern struct pci_bus *iop310_scan_bus(int nr, struct pci_sys_data *);
-extern void iop310_init(void);
-
extern int iop321_setup(int nr, struct pci_sys_data *);
extern struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *);
extern void iop321_init(void);
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