At the moment, there are two different switches used, irqbalance_disabled
and no_balance_irq ... each of which switches half the code off. This
patch harmonises them into one (irqbalance_disable), and uses the old
subarch stuff as a default value so that this is auto-disabled on boxes
like NUMA-Q that can't cope with it.
Also renamed no_balance_irq to NO_BALANCE_IRQ as it's really a static
defined number now, not pretending to be a switch variable any more.
Now off by default for NUMA-Q, on by default for others, but can be
disabled with the boot time flag if people desire.
extern unsigned long irq_affinity [NR_IRQS];
int __cacheline_aligned pending_irq_balance_apicid [NR_IRQS];
-static int irqbalance_disabled __initdata = 0;
+static int irqbalance_disabled = NO_BALANCE_IRQ;
static int physical_balance = 0;
struct irq_cpu_info {
unsigned long allowed_mask;
unsigned int new_cpu;
- if (no_balance_irq)
+ if (irqbalance_disabled)
return;
allowed_mask = cpu_online_map & irq_affinity[irq];
((phys_apic) & (~0xf)) )
#endif
-#define no_balance_irq (1)
+#define NO_BALANCE_IRQ (1)
#define esr_disable (1)
static inline int apic_id_registered(void)
#define TARGET_CPUS 0x01
#endif
-#define no_balance_irq (0)
+#define NO_BALANCE_IRQ (0)
#define esr_disable (0)
#define INT_DELIVERY_MODE dest_LowestPrio
#define TARGET_CPUS (0xf)
-#define no_balance_irq (1)
+#define NO_BALANCE_IRQ (1)
#define esr_disable (1)
#define INT_DELIVERY_MODE dest_LowestPrio
extern int x86_summit;
#define esr_disable (x86_summit ? 1 : 0)
-#define no_balance_irq (0)
+#define NO_BALANCE_IRQ (0)
#define XAPIC_DEST_CPUS_MASK 0x0Fu
#define XAPIC_DEST_CLUSTER_MASK 0xF0u