[PATCH] ppc64: add performance monitor register information to processor.h

Most special purpose registers on the ppc64 have both the SPR number, and
the various fields within the register defined in asm-ppc64/processor.h.
So far that's not true for the performance counter control registers, MMCR0
and MMCRA.  They have the SPR numbers defined, but the internal fields are
defined in the oprofile code and (just a few) in traps.c where they're
actually used.

This patch moves all the MMCR0 and MMCRA definitions, plus the MSR
performance monitor bit, MSR_PMM, into processor.h.

Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

diff --git a/arch/ppc64/kernel/traps.c b/arch/ppc64/kernel/traps.c
index 76c942871e015162b45e999d8329b5f09eb93bb7..8d7d292d1eff3a5dafefe9f31edcefe9c4e7dfde 100644 (file)
--- a/arch/ppc64/kernel/traps.c
+++ b/arch/ppc64/kernel/traps.c
@@ -549,9 +549,6 @@ void AltivecUnavailableException(struct pt_regs *regs)
 }
 
 /* Ensure exceptions are disabled */
-#define MMCR0_PMXE      (1UL << (31 - 5))
-#define MMCR0_PMAO      (1UL << (31 - 24))
-
 static void dummy_perf(struct pt_regs *regs)
 {
        unsigned int mmcr0 = mfspr(SPRN_MMCR0);

diff --git a/arch/ppc64/oprofile/op_impl.h b/arch/ppc64/oprofile/op_impl.h
index 30c71a03b189b583db02c9c219d020e010234852..7fa7eaabc035113452be4e1efcf08bd9b2558cda 100644 (file)
--- a/arch/ppc64/oprofile/op_impl.h
+++ b/arch/ppc64/oprofile/op_impl.h
@@ -14,44 +14,6 @@
 
 #define OP_MAX_COUNTER 8
 
-#define MSR_PMM                (1UL << (63 - 61))
-
-/* freeze counters. set to 1 on a perfmon exception */
-#define MMCR0_FC       (1UL << (31 - 0))
-
-/* freeze in supervisor state */
-#define MMCR0_KERNEL_DISABLE (1UL << (31 - 1))
-
-/* freeze in problem state */
-#define MMCR0_PROBLEM_DISABLE (1UL << (31 - 2))
-
-/* freeze counters while MSR mark = 1 */
-#define MMCR0_FCM1     (1UL << (31 - 3))
-
-/* performance monitor exception enable */
-#define MMCR0_PMXE     (1UL << (31 - 5))
-
-/* freeze counters on enabled condition or event */
-#define MMCR0_FCECE    (1UL << (31 - 6))
-
-/* PMC1 count enable*/
-#define MMCR0_PMC1INTCONTROL   (1UL << (31 - 16))
-
-/* PMCn count enable*/
-#define MMCR0_PMCNINTCONTROL   (1UL << (31 - 17))
-
-/* performance monitor alert has occurred, set to 0 after handling exception */
-#define MMCR0_PMAO     (1UL << (31 - 24))
-
-/* state of MSR HV when SIAR set */
-#define MMCRA_SIHV     (1UL << (63 - 35))
-
-/* state of MSR PR when SIAR set */
-#define MMCRA_SIPR     (1UL << (63 - 36))
-
-/* enable sampling */
-#define MMCRA_SAMPLE_ENABLE    (1UL << (63 - 63))
-
 /* Per-counter configuration as set via oprofilefs.  */
 struct op_counter_config {
        unsigned long valid;

diff --git a/include/asm-ppc64/processor.h b/include/asm-ppc64/processor.h
index 0ec53a4addf6176653d544dcf09646187f8fccc0..d5b23b426efab6f0cadb8e7265ce901aa699968c 100644 (file)
--- a/include/asm-ppc64/processor.h
+++ b/include/asm-ppc64/processor.h
@@ -45,6 +45,7 @@
 #define MSR_DR_LG      4               /* Data Relocate */
 #define MSR_PE_LG      3               /* Protection Enable */
 #define MSR_PX_LG      2               /* Protection Exclusive Mode */
+#define MSR_PMM_LG     2               /* Performance monitor */
 #define MSR_RI_LG      1               /* Recoverable Exception */
 #define MSR_LE_LG      0               /* Little Endian */
 
@@ -77,6 +78,7 @@
 #define MSR_DR         __MASK(MSR_DR_LG)       /* Data Relocate */
 #define MSR_PE         __MASK(MSR_PE_LG)       /* Protection Enable */
 #define MSR_PX         __MASK(MSR_PX_LG)       /* Protection Exclusive Mode */
+#define MSR_PMM                __MASK(MSR_PMM_LG)      /* Performance monitor */
 #define MSR_RI         __MASK(MSR_RI_LG)       /* Recoverable Exception */
 #define MSR_LE         __MASK(MSR_LE_LG)       /* Little Endian */
 
@@ -306,6 +308,9 @@
 #define SPRN_SIAR      780
 #define SPRN_SDAR      781
 #define SPRN_MMCRA     786
+#define   MMCRA_SIHV   0x10000000UL /* state of MSR HV when SIAR set */
+#define   MMCRA_SIPR   0x08000000UL /* state of MSR PR when SIAR set */
+#define   MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
 #define SPRN_PMC1      787
 #define SPRN_PMC2      788
 #define SPRN_PMC3      789
@@ -315,6 +320,26 @@
 #define SPRN_PMC7      793
 #define SPRN_PMC8      794
 #define SPRN_MMCR0     795
+#define   MMCR0_FC     0x80000000UL /* freeze counters. set to 1 on a perfmon exception */
+#define   MMCR0_FCS    0x40000000UL /* freeze in supervisor state */
+#define   MMCR0_KERNEL_DISABLE MMCR0_FCS
+#define   MMCR0_FCP    0x20000000UL /* freeze in problem state */
+#define   MMCR0_PROBLEM_DISABLE MMCR0_FCP
+#define   MMCR0_FCM1   0x10000000UL /* freeze counters while MSR mark = 1 */
+#define   MMCR0_FCM0   0x08000000UL /* freeze counters while MSR mark = 0 */
+#define   MMCR0_PMXE   0x04000000UL /* performance monitor exception enable */
+#define   MMCR0_FCECE  0x02000000UL /* freeze counters on enabled condition or event */
+/* time base exception enable */
+#define   MMCR0_TBEE   0x00400000UL /* time base exception enable */
+#define   MMCR0_PMC1INTCONTROL 0x00008000UL /* PMC1 count enable*/
+#define   MMCR0_PMCNINTCONTROL 0x00004000UL /* PMCn count enable*/
+#define   MMCR0_TRIGGER        0x00002000UL /* TRIGGER enable */
+#define   MMCR0_PMAO   0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
+#define   MMCR0_SHRFC  0x00000040UL /* SHRre freeze conditions between threads */
+#define   MMCR0_FCTI   0x00000008UL /* freeze counters in tags inactive mode */
+#define   MMCR0_FCTA   0x00000004UL /* freeze counters in tags active mode */
+#define   MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */
+#define   MMCR0_FCHV   0x00000001UL /* freeze conditions in hypervisor mode */
 #define SPRN_MMCR1     798
 
 /* Short-hand versions for a number of the above SPRNs */