riscv: Remove duplicated GET_RM

[ Upstream commit 164f66de6bb6ef454893f193c898dc8f1da6d18b ]

The macro GET_RM defined twice in this file, one can be removed.

Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
Fixes: 956d705dd279 ("riscv: Unaligned load/store handling for M_MODE")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20241008094141.549248-3-zhangchunyan@iscas.ac.cn
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index b246c3dc6993054623c0d74e8a9f9fa4ba200e54..d548d6992d988b4feb08a0a5edd1d734c94ec151 100644 (file)
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -131,8 +131,6 @@
 #define REG_PTR(insn, pos, regs)       \
        (ulong *)((ulong)(regs) + REG_OFFSET(insn, pos))
 
-#define GET_RM(insn)                   (((insn) >> 12) & 7)
-
 #define GET_RS1(insn, regs)            (*REG_PTR(insn, SH_RS1, regs))
 #define GET_RS2(insn, regs)            (*REG_PTR(insn, SH_RS2, regs))
 #define GET_RS1S(insn, regs)           (*REG_PTR(RVC_RS1S(insn), 0, regs))