This makes NMIs work - otherwise they go to CPU 0 only and any hard
lockup on the other CPUs will not be detected by the nmi_watchdog.
end_lapic_irq
};
-static void enable_NMI_through_LVT0 (void * dummy)
+void enable_NMI_through_LVT0 (void * dummy)
{
unsigned int v, ver;
while (!test_bit(smp_processor_id(), &smp_commenced_mask))
rep_nop();
setup_secondary_APIC_clock();
+ if (nmi_watchdog == NMI_IO_APIC) {
+ disable_8259A_irq(0);
+ enable_NMI_through_LVT0(NULL);
+ enable_8259A_irq(0);
+ }
enable_APIC_timer();
/*
* low-memory mappings have been cleared, flush them from
extern unsigned int apic_timer_irqs [NR_CPUS];
extern int check_nmi_watchdog (void);
+extern void enable_NMI_through_LVT0 (void * dummy);
extern unsigned int nmi_watchdog;
#define NMI_NONE 0