drm/amd/display: Add Debug Option To Enable Per-DPM De-rate Usage

[Why]
DML has been updated to use per-DPM derates when provided but per-DPM de-rates have not been finalized.
Need to validate to see what values should be stored in the bounding box.

[How]
Add debug options to set custom derates per DPM (starting at DPM0) and their values

Each entry in the custom derate expects the derates to be stored in the following format:
bits 0-7: dram_derate_percent_pixel
bits 8-15: fclk_derate_percent
bits 16-23: dcfclk_derate_percent
bits 24-31 are unused.

e.g. Using the value 0x414020 will set the following derates for DPM0
DPM0: 0x20, 0x40, 0x41 for dram, fclk, and dcfclk respectively

Note that global derate value will be used if the per-DPM derate is 0.

Reviewed-by: Jun Lei <jun.lei@amd.com>
Signed-off-by: Austin Zheng <Austin.Zheng@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index c2a1f75ae9ae0bd5bfd0f731ea65eb25c8a778e1..c628bf8778c925585f7d58fd041b77f1ba8ecf0c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1289,6 +1289,8 @@ struct dc_debug_options {
        bool enable_replay_esd_recovery;
        uint8_t iommu_mismatch_temp_wka;
        bool disable_dynamic_expansion_for_test_pattern;
+       uint32_t dml21_custom_derate_num_dpms;
+       uint32_t dml21_custom_derate_at_dpm[DML2_MAX_NUM_DPM_LVL];
 };
 
 

diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c
index 89f7ccd7f81f067d38a0cb0119a689ace5f89f4d..0c8e652c35321e92a6848051594d2f61b01a751f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c
+++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c
@@ -269,6 +269,22 @@ void dcn401_update_soc_bb_with_values_from_software_policy(struct dml2_soc_bb *s
        if (dc->bb_overrides.sr_enter_plus_exit_z8_time_ns)
                soc_bb->power_management_parameters.z8_stutter_enter_plus_exit_latency_us =
                                dc->bb_overrides.sr_enter_plus_exit_z8_time_ns / 1000.0;
+
+       /* Override per-dpm derates based on a custom derate table.
+        * Global derate value will be used for derates that aren't populated
+        * 3 derates for a single DPM level:
+        *  bits 0-7: dram_derate_percent_pixel
+        *  bits 8-15: fclk_derate_percent
+        *  bits 16-23: dcfclk_derate_percent
+        */
+       for (unsigned int i = 0; i < dc->debug.dml21_custom_derate_num_dpms; i++) {
+               soc_bb->qos_parameters.derate_table_per_dpm.system_active_derates_per_dpm.dram_derate_percent_pixel[i]
+                       = dc->debug.dml21_custom_derate_at_dpm[i] & 0xFF;
+               soc_bb->qos_parameters.derate_table_per_dpm.system_active_derates_per_dpm.fclk_derate_percent[i]
+                       = (dc->debug.dml21_custom_derate_at_dpm[i] >> 8) & 0xFF;
+               soc_bb->qos_parameters.derate_table_per_dpm.system_active_derates_per_dpm.dcfclk_derate_percent[i]
+                       = (dc->debug.dml21_custom_derate_at_dpm[i] >> 16) & 0xFF;
+       }
 }
 
 static void apply_soc_bb_updates(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config)