+++ /dev/null
-/* Linker script for the Midas labs Anna V850E2 evaluation board
- (CONFIG_V850E2_ANNA), with kernel in ROM (CONFIG_ROM_KERNEL). */
-
-MEMORY {
- /* 8MB of flash ROM. */
- ROM : ORIGIN = 0, LENGTH = 0x00800000
-
- /* 1MB of static RAM. This memory is mirrored 64 times. */
- SRAM : ORIGIN = 0x04000000, LENGTH = 0x00100000
- /* 64MB of DRAM. */
- SDRAM : ORIGIN = 0x08000000, LENGTH = 0x04000000
-}
-
-SECTIONS {
- ROMK_SECTIONS(ROM, SRAM)
-}
+++ /dev/null
-/* Linker script for the Midas labs Anna V850E2 evaluation board
- (CONFIG_V850E2_ANNA). */
-
-MEMORY {
- /* 256KB of internal memory (followed by one mirror). */
- iMEM0 : ORIGIN = 0, LENGTH = 0x00040000
- /* 256KB of internal memory (followed by one mirror). */
- iMEM1 : ORIGIN = 0x00040000, LENGTH = 0x00040000
-
- /* 1MB of static RAM. This memory is mirrored 64 times. */
- SRAM : ORIGIN = 0x04000000, LENGTH = 0x00100000
- /* 64MB of DRAM. */
- SDRAM : ORIGIN = 0x08000000, LENGTH = 0x04000000
-}
-
-SECTIONS {
- .intv : { INTV_CONTENTS } > iMEM0
- .sram : { RAMK_KRAM_CONTENTS } > SRAM
- .root : { ROOT_FS_CONTENTS } > SDRAM
-}
+++ /dev/null
-/* Linker script for the NEC AS85EP1 V850E evaluation board
- (CONFIG_V850E_AS85EP1), with kernel in ROM (CONFIG_ROM_KERNEL). */
-
-MEMORY {
- /* 4MB of flash ROM. */
- ROM : ORIGIN = 0, LENGTH = 0x00400000
-
- /* 1MB of static RAM. */
- SRAM : ORIGIN = 0x00400000, LENGTH = 0x00100000
-
- /* About 58MB of DRAM. This can actually be at one of two
- positions, determined by jumper JP3; we have to use the first
- position because the second is partially out of processor
- instruction addressing range (though in the second position
- there's actually 64MB available). */
- SDRAM : ORIGIN = 0x00600000, LENGTH = 0x039F8000
-}
-
-SECTIONS {
- ROMK_SECTIONS(ROM, SRAM)
-}
+++ /dev/null
-/* Linker script for the NEC AS85EP1 V850E evaluation board
- (CONFIG_V850E_AS85EP1). */
-
-MEMORY {
- /* 1MB of internal memory (\e$BFbB"L?Na\e(BRAM). */
- iMEM0 : ORIGIN = 0, LENGTH = 0x00100000
-
- /* 1MB of static RAM. */
- SRAM : ORIGIN = 0x00400000, LENGTH = 0x00100000
-
- /* About 58MB of DRAM. This can actually be at one of two
- positions, determined by jump JP3; we have to use the first
- position because the second is partially out of processor
- instruction addressing range (though in the second position
- there's actually 64MB available). */
- SDRAM : ORIGIN = 0x00600000, LENGTH = 0x039F8000
-}
-
-SECTIONS {
- .resetv : {
- __intv_start = . ;
- *(.intv.reset) /* Reset vector */
- } > iMEM0
-
- .sram : {
- RAMK_KRAM_CONTENTS
-
- /* We stick most of the interrupt vectors here; they'll be
- copied into the proper location by the early init code (we
- can't put them directly in the right place because of
- hardware bugs). The vectors shouldn't need to be
- relocated, so we don't have to use `> ... AT> ...' to
- split the load/vm addresses (and we can't because of
- problems with the loader). */
- . = ALIGN (0x10) ;
- __intv_copy_src_start = . ;
- *(.intv.common) /* Vectors common to all v850e proc. */
- *(.intv.mach) /* Machine-specific int. vectors. */
- . = ALIGN (0x10) ;
- __intv_copy_src_end = . ;
- } > SRAM
-
- /* Where we end up putting the vectors. */
- __intv_copy_dst_start = 0x10 ;
- __intv_copy_dst_end = __intv_copy_dst_start + (__intv_copy_src_end - __intv_copy_src_start) ;
- __intv_end = __intv_copy_dst_end ;
-
- .root : { ROOT_FS_CONTENTS } > SDRAM
-}
+++ /dev/null
-/* Linker script for the FPGA implementation of the V850E2 NA85E2C cpu core
- (CONFIG_V850E2_FPGA85E2C). */
-
-MEMORY {
- /* Reset vector. */
- RESET : ORIGIN = 0, LENGTH = 0x10
- /* Interrupt vectors. */
- INTV : ORIGIN = 0x10, LENGTH = 0x470
- /* The `window' in RAM were we're allowed to load stuff. */
- RAM_LOW : ORIGIN = 0x480, LENGTH = 0x0005FB80
- /* Some more ram above the window were we can put bss &c. */
- RAM_HIGH : ORIGIN = 0x00060000, LENGTH = 0x000A0000
- /* This is the area visible from the outside world (we can use
- this only for uninitialized data). */
- VISIBLE : ORIGIN = 0x00200000, LENGTH = 0x00060000
-}
-
-SECTIONS {
- .reset : {
- __kram_start = . ;
- __intv_start = . ;
- *(.intv.reset) /* Reset vector */
- } > RESET
-
- .ram_low : {
- __r0_ram = . ; /* Must be near address 0. */
- . = . + 32 ;
-
- TEXT_CONTENTS
- DATA_CONTENTS
- ROOT_FS_CONTENTS
- RAMK_INIT_CONTENTS_NO_END
- INITRAMFS_CONTENTS
- } > RAM_LOW
-
- /* Where the interrupt vectors are initially loaded. */
- __intv_load_start = . ;
-
- .intv : {
- *(.intv.common) /* Vectors common to all v850e proc. */
- *(.intv.mach) /* Machine-specific int. vectors. */
- __intv_end = . ;
- } > INTV AT> RAM_LOW
-
- .ram_high : {
- /* This is here so that when we free init memory the
- load-time copy of the interrupt vectors and any empty
- space at the end of the `RAM_LOW' area is freed too. */
- . = ALIGN (4096);
- __init_end = . ;
-
- BSS_CONTENTS
- __kram_end = . ;
- BOOTMAP_CONTENTS
- } > RAM_HIGH
-
- .visible : {
- _memcons_output = . ;
- . = . + 0x8000 ;
- _memcons_output_end = . ;
- } > VISIBLE
-}
--- /dev/null
+/* Linker script for the Midas labs Anna V850E2 evaluation board
+ (CONFIG_V850E2_ANNA), with kernel in ROM (CONFIG_ROM_KERNEL). */
+
+MEMORY {
+ /* 8MB of flash ROM. */
+ ROM : ORIGIN = 0, LENGTH = 0x00800000
+
+ /* 1MB of static RAM. This memory is mirrored 64 times. */
+ SRAM : ORIGIN = SRAM_ADDR, LENGTH = SRAM_SIZE
+ /* 64MB of DRAM. */
+ SDRAM : ORIGIN = SDRAM_ADDR, LENGTH = SDRAM_SIZE
+}
+
+SECTIONS {
+ ROMK_SECTIONS(ROM, SRAM)
+}
--- /dev/null
+/* Linker script for the Midas labs Anna V850E2 evaluation board
+ (CONFIG_V850E2_ANNA). */
+
+MEMORY {
+ /* 256KB of internal memory (followed by one mirror). */
+ iMEM0 : ORIGIN = 0, LENGTH = 0x00040000
+ /* 256KB of internal memory (followed by one mirror). */
+ iMEM1 : ORIGIN = 0x00040000, LENGTH = 0x00040000
+
+ /* 1MB of static RAM. This memory is mirrored 64 times. */
+ SRAM : ORIGIN = SRAM_ADDR, LENGTH = SRAM_SIZE
+ /* 64MB of DRAM. */
+ SDRAM : ORIGIN = SDRAM_ADDR, LENGTH = SDRAM_SIZE
+}
+
+SECTIONS {
+ .intv : { INTV_CONTENTS } > iMEM0
+ .sram : { RAMK_KRAM_CONTENTS } > SRAM
+ .root : { ROOT_FS_CONTENTS } > SDRAM
+}
--- /dev/null
+/* Linker script for the NEC AS85EP1 V850E evaluation board
+ (CONFIG_V850E_AS85EP1), with kernel in ROM (CONFIG_ROM_KERNEL). */
+
+MEMORY {
+ /* 4MB of flash ROM. */
+ ROM : ORIGIN = 0, LENGTH = 0x00400000
+
+ /* 1MB of static RAM. */
+ SRAM : ORIGIN = SRAM_ADDR, LENGTH = SRAM_SIZE
+
+ /* About 58MB of DRAM. This can actually be at one of two
+ positions, determined by jumper JP3; we have to use the first
+ position because the second is partially out of processor
+ instruction addressing range (though in the second position
+ there's actually 64MB available). */
+ SDRAM : ORIGIN = SDRAM_ADDR, LENGTH = SDRAM_SIZE
+}
+
+SECTIONS {
+ ROMK_SECTIONS(ROM, SRAM)
+}
--- /dev/null
+/* Linker script for the NEC AS85EP1 V850E evaluation board
+ (CONFIG_V850E_AS85EP1). */
+
+MEMORY {
+ /* 1MB of internal memory (Æâ¢̿ÎáRAM). */
+ iMEM0 : ORIGIN = 0, LENGTH = 0x00100000
+
+ /* 1MB of static RAM. */
+ SRAM : ORIGIN = SRAM_ADDR, LENGTH = SRAM_SIZE
+
+ /* About 58MB of DRAM. This can actually be at one of two
+ positions, determined by jump JP3; we have to use the first
+ position because the second is partially out of processor
+ instruction addressing range (though in the second position
+ there's actually 64MB available). */
+ SDRAM : ORIGIN = SDRAM_ADDR, LENGTH = SDRAM_SIZE
+}
+
+SECTIONS {
+ .resetv : {
+ __intv_start = . ;
+ *(.intv.reset) /* Reset vector */
+ } > iMEM0
+
+ .sram : {
+ RAMK_KRAM_CONTENTS
+
+ /* We stick most of the interrupt vectors here; they'll be
+ copied into the proper location by the early init code (we
+ can't put them directly in the right place because of
+ hardware bugs). The vectors shouldn't need to be
+ relocated, so we don't have to use `> ... AT> ...' to
+ split the load/vm addresses (and we can't because of
+ problems with the loader). */
+ . = ALIGN (0x10) ;
+ __intv_copy_src_start = . ;
+ *(.intv.common) /* Vectors common to all v850e proc. */
+ *(.intv.mach) /* Machine-specific int. vectors. */
+ . = ALIGN (0x10) ;
+ __intv_copy_src_end = . ;
+ } > SRAM
+
+ /* Where we end up putting the vectors. */
+ __intv_copy_dst_start = 0x10 ;
+ __intv_copy_dst_end = __intv_copy_dst_start + (__intv_copy_src_end - __intv_copy_src_start) ;
+ __intv_end = __intv_copy_dst_end ;
+
+ .root : { ROOT_FS_CONTENTS } > SDRAM
+}
--- /dev/null
+/* Linker script for the FPGA implementation of the V850E2 NA85E2C cpu core
+ (CONFIG_V850E2_FPGA85E2C). */
+
+MEMORY {
+ /* Reset vector. */
+ RESET : ORIGIN = 0, LENGTH = 0x10
+ /* Interrupt vectors. */
+ INTV : ORIGIN = 0x10, LENGTH = 0x470
+ /* The `window' in RAM were we're allowed to load stuff. */
+ RAM_LOW : ORIGIN = 0x480, LENGTH = 0x0005FB80
+ /* Some more ram above the window were we can put bss &c. */
+ RAM_HIGH : ORIGIN = 0x00060000, LENGTH = 0x000A0000
+ /* This is the area visible from the outside world (we can use
+ this only for uninitialized data). */
+ VISIBLE : ORIGIN = 0x00200000, LENGTH = 0x00060000
+}
+
+SECTIONS {
+ .reset : {
+ __kram_start = . ;
+ __intv_start = . ;
+ *(.intv.reset) /* Reset vector */
+ } > RESET
+
+ .ram_low : {
+ __r0_ram = . ; /* Must be near address 0. */
+ . = . + 32 ;
+
+ TEXT_CONTENTS
+ DATA_CONTENTS
+ ROOT_FS_CONTENTS
+ RAMK_INIT_CONTENTS_NO_END
+ INITRAMFS_CONTENTS
+ } > RAM_LOW
+
+ /* Where the interrupt vectors are initially loaded. */
+ __intv_load_start = . ;
+
+ .intv : {
+ *(.intv.common) /* Vectors common to all v850e proc. */
+ *(.intv.mach) /* Machine-specific int. vectors. */
+ __intv_end = . ;
+ } > INTV AT> RAM_LOW
+
+ .ram_high : {
+ /* This is here so that when we free init memory the
+ load-time copy of the interrupt vectors and any empty
+ space at the end of the `RAM_LOW' area is freed too. */
+ . = ALIGN (4096);
+ __init_end = . ;
+
+ BSS_CONTENTS
+ __kram_end = . ;
+ BOOTMAP_CONTENTS
+ } > RAM_HIGH
+
+ .visible : {
+ _memcons_output = . ;
+ . = . + 0x8000 ;
+ _memcons_output_end = . ;
+ } > VISIBLE
+}
--- /dev/null
+/* Linker script for the Midas labs RTE-V850E/MA1-CB evaluation board
+ (CONFIG_RTE_CB_MA1), with kernel in ROM. */
+
+MEMORY {
+ ROM : ORIGIN = 0x00000000, LENGTH = 0x00100000
+ /* 1MB of SRAM. This memory is mirrored 4 times. */
+ SRAM : ORIGIN = SRAM_ADDR, LENGTH = SRAM_SIZE
+ /* 32MB of SDRAM. */
+ SDRAM : ORIGIN = SDRAM_ADDR, LENGTH = SDRAM_SIZE
+}
+
+SECTIONS {
+ ROMK_SECTIONS(ROM, SRAM)
+}
--- /dev/null
+/* Linker script for the Midas labs RTE-V850E/MA1-CB evaluation board
+ (CONFIG_RTE_CB_MA1), with kernel in SDRAM, under Multi debugger. */
+
+MEMORY {
+ /* 1MB of SRAM; we can't use the last 32KB, because it's used by
+ the monitor scratch-RAM. This memory is mirrored 4 times. */
+ SRAM : ORIGIN = SRAM_ADDR, LENGTH = (SRAM_SIZE - MON_SCRATCH_SIZE)
+ /* Monitor scratch RAM; only the interrupt vectors should go here. */
+ MRAM : ORIGIN = MON_SCRATCH_ADDR, LENGTH = MON_SCRATCH_SIZE
+ /* 32MB of SDRAM. */
+ SDRAM : ORIGIN = SDRAM_ADDR, LENGTH = SDRAM_SIZE
+}
+
+#ifdef CONFIG_RTE_CB_MA1_KSRAM
+# define KRAM SRAM
+#else
+# define KRAM SDRAM
+#endif
+
+SECTIONS {
+ /* We can't use RAMK_KRAM_CONTENTS because that puts the whole
+ kernel in a single ELF segment, and the Multi debugger (which
+ we use to load the kernel) appears to have bizarre problems
+ dealing with it. */
+
+ .text : {
+ __kram_start = . ;
+ TEXT_CONTENTS
+ } > KRAM
+
+ .data : {
+ DATA_CONTENTS
+ BSS_CONTENTS
+ RAMK_INIT_CONTENTS
+ __kram_end = . ;
+ BOOTMAP_CONTENTS
+
+ /* The address at which the interrupt vectors are initially
+ loaded by the loader. We can't load the interrupt vectors
+ directly into their target location, because the monitor
+ ROM for the GHS Multi debugger barfs if we try.
+ Unfortunately, Multi also doesn't deal correctly with ELF
+ sections where the LMA and VMA differ (it just ignores the
+ LMA), so we can't use that feature to work around the
+ problem! What we do instead is just put the interrupt
+ vectors into a normal section, and have the
+ `mach_early_init' function for Midas boards do the
+ necessary copying and relocation at runtime (this section
+ basically only contains `jr' instructions, so it's not
+ that hard). */
+ . = ALIGN (0x10) ;
+ __intv_load_start = . ;
+ INTV_CONTENTS
+ } > KRAM
+
+ .root ALIGN (4096) : { ROOT_FS_CONTENTS } > SDRAM
+}
--- /dev/null
+/* Linker script for the Midas labs RTE-V850E/ME2-CB evaluation board
+ (CONFIG_RTE_CB_ME2), with kernel in SDRAM. */
+
+MEMORY {
+ /* 128Kbyte of IRAM */
+ IRAM : ORIGIN = 0x00000000, LENGTH = 0x00020000
+
+ /* 32MB of SDRAM. */
+ SDRAM : ORIGIN = SDRAM_ADDR, LENGTH = SDRAM_SIZE
+}
+
+#define KRAM SDRAM
+
+SECTIONS {
+ .text : {
+ __kram_start = . ;
+ TEXT_CONTENTS
+ INTV_CONTENTS /* copy to iRAM (0x0-0x620) */
+ } > KRAM
+
+ .data : {
+ DATA_CONTENTS
+ BSS_CONTENTS
+ RAMK_INIT_CONTENTS
+ __kram_end = . ;
+ BOOTMAP_CONTENTS
+ } > KRAM
+
+ .root ALIGN (4096) : { ROOT_FS_CONTENTS } > SDRAM
+}
--- /dev/null
+/* Linker script for the Midas labs RTE-NB85E-CB evaluation board
+ (CONFIG_RTE_CB_NB85E), with the Multi debugger ROM monitor . */
+
+MEMORY {
+ /* 1MB of SRAM; we can't use the last 96KB, because it's used by
+ the monitor scratch-RAM. This memory is mirrored 4 times. */
+ SRAM : ORIGIN = SRAM_ADDR, LENGTH = (SRAM_SIZE - MON_SCRATCH_SIZE)
+ /* Monitor scratch RAM; only the interrupt vectors should go here. */
+ MRAM : ORIGIN = MON_SCRATCH_ADDR, LENGTH = MON_SCRATCH_SIZE
+ /* 16MB of SDRAM. */
+ SDRAM : ORIGIN = SDRAM_ADDR, LENGTH = SDRAM_SIZE
+}
+
+#ifdef CONFIG_RTE_CB_NB85E_KSRAM
+# define KRAM SRAM
+#else
+# define KRAM SDRAM
+#endif
+
+SECTIONS {
+ /* We can't use RAMK_KRAM_CONTENTS because that puts the whole
+ kernel in a single ELF segment, and the Multi debugger (which
+ we use to load the kernel) appears to have bizarre problems
+ dealing with it. */
+
+ .text : {
+ __kram_start = . ;
+ TEXT_CONTENTS
+ } > KRAM
+
+ .data : {
+ DATA_CONTENTS
+ BSS_CONTENTS
+ RAMK_INIT_CONTENTS
+ __kram_end = . ;
+ BOOTMAP_CONTENTS
+
+ /* The address at which the interrupt vectors are initially
+ loaded by the loader. We can't load the interrupt vectors
+ directly into their target location, because the monitor
+ ROM for the GHS Multi debugger barfs if we try.
+ Unfortunately, Multi also doesn't deal correctly with ELF
+ sections where the LMA and VMA differ (it just ignores the
+ LMA), so we can't use that feature to work around the
+ problem! What we do instead is just put the interrupt
+ vectors into a normal section, and have the
+ `mach_early_init' function for Midas boards do the
+ necessary copying and relocation at runtime (this section
+ basically only contains `jr' instructions, so it's not
+ that hard). */
+ . = ALIGN (0x10) ;
+ __intv_load_start = . ;
+ INTV_CONTENTS
+ } > KRAM
+
+ .root ALIGN (4096) : { ROOT_FS_CONTENTS } > SDRAM
+}
--- /dev/null
+/* Linker script for the Midas labs RTE-NB85E-CB evaluation board
+ (CONFIG_RTE_CB_NB85E). */
+
+MEMORY {
+ LOW : ORIGIN = 0x0, LENGTH = 0x00100000
+ /* 1MB of SRAM This memory is mirrored 4 times. */
+ SRAM : ORIGIN = SRAM_ADDR, LENGTH = SRAM_SIZE
+ /* 16MB of SDRAM. */
+ SDRAM : ORIGIN = SDRAM_ADDR, LENGTH = SDRAM_SIZE
+}
+
+#ifdef CONFIG_RTE_CB_NB85E_KSRAM
+# define KRAM SRAM
+#else
+# define KRAM SDRAM
+#endif
+
+SECTIONS {
+ .intv : { INTV_CONTENTS } > LOW
+ .sram : { RAMK_KRAM_CONTENTS } > KRAM
+ .root : { ROOT_FS_CONTENTS } > SDRAM
+}
--- /dev/null
+/* Linker script for the gdb v850e simulator (CONFIG_V850E_SIM). */
+
+MEMORY {
+ /* Interrupt vectors. */
+ INTV : ORIGIN = 0x0, LENGTH = 0xe0
+ /* Main RAM. */
+ RAM : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
+}
+
+SECTIONS {
+ .intv : { INTV_CONTENTS } > INTV
+ .ram : { RAMK_KRAM_CONTENTS } > RAM
+}
--- /dev/null
+/* Linker script for the sim85e2c simulator, which is a verilog simulation of
+ the V850E2 NA85E2C cpu core (CONFIG_V850E2_SIM85E2C). */
+
+MEMORY {
+ /* 1MB of `instruction RAM', starting at 0.
+ Instruction fetches are much faster from IRAM than from DRAM. */
+ IRAM : ORIGIN = IRAM_ADDR, LENGTH = IRAM_SIZE
+
+ /* 1MB of `data RAM', below and contiguous with the I/O space.
+ Data fetches are much faster from DRAM than from IRAM. */
+ DRAM : ORIGIN = DRAM_ADDR, LENGTH = DRAM_SIZE
+
+ /* `external ram' (CS1 area), comes after IRAM. */
+ ERAM : ORIGIN = ERAM_ADDR, LENGTH = ERAM_SIZE
+
+ /* Dynamic RAM; uses memory controller. */
+ SDRAM : ORIGIN = SDRAM_ADDR, LENGTH = SDRAM_SIZE
+}
+
+SECTIONS {
+ .iram : {
+ INTV_CONTENTS
+ *arch/v850/kernel/head.o
+ *(.early.text)
+ } > IRAM
+ .dram : {
+ _memcons_output = . ;
+ . = . + 0x8000 ;
+ _memcons_output_end = . ;
+ } > DRAM
+ .sdram : {
+ /* We stick console output into a buffer here. */
+ RAMK_KRAM_CONTENTS
+ ROOT_FS_CONTENTS
+ } > SDRAM
+}
#include <linux/config.h>
#include <asm-generic/vmlinux.lds.h>
+/* For most platforms, this will define useful things like RAM addr/size. */
+#include <asm/machdep.h>
+
/* The following macros contain the usual definitions for various data areas.
The prefix `RAMK_' is used to indicate macros suitable for kernels loaded
+++ /dev/null
-/* Linker script for the Midas labs RTE-V850E/MA1-CB evaluation board
- (CONFIG_RTE_CB_MA1), with kernel in ROM. */
-
-MEMORY {
- ROM : ORIGIN = 0x00000000, LENGTH = 0x00100000
- /* 1MB of SRAM. This memory is mirrored 4 times. */
- SRAM : ORIGIN = 0x00400000, LENGTH = 0x00100000
- /* 32MB of SDRAM. */
- SDRAM : ORIGIN = 0x00800000, LENGTH = 0x02000000
-}
-
-SECTIONS {
- ROMK_SECTIONS(ROM, SRAM)
-}
+++ /dev/null
-/* Linker script for the Midas labs RTE-V850E/MA1-CB evaluation board
- (CONFIG_RTE_CB_MA1), with kernel in SDRAM, under Multi debugger. */
-
-MEMORY {
- /* 1MB of SRAM; we can't use the last 32KB, because it's used by
- the monitor scratch-RAM. This memory is mirrored 4 times. */
- SRAM : ORIGIN = 0x00400000, LENGTH = 0x000F8000
- /* Monitor scratch RAM; only the interrupt vectors should go here. */
- MRAM : ORIGIN = 0x004F8000, LENGTH = 0x00008000
- /* 32MB of SDRAM. */
- SDRAM : ORIGIN = 0x00800000, LENGTH = 0x02000000
-}
-
-#ifdef CONFIG_RTE_CB_MA1_KSRAM
-# define KRAM SRAM
-#else
-# define KRAM SDRAM
-#endif
-
-SECTIONS {
- /* We can't use RAMK_KRAM_CONTENTS because that puts the whole
- kernel in a single ELF segment, and the Multi debugger (which
- we use to load the kernel) appears to have bizarre problems
- dealing with it. */
-
- .text : {
- __kram_start = . ;
- TEXT_CONTENTS
- } > KRAM
-
- .data : {
- DATA_CONTENTS
- BSS_CONTENTS
- RAMK_INIT_CONTENTS
- __kram_end = . ;
- BOOTMAP_CONTENTS
-
- /* The address at which the interrupt vectors are initially
- loaded by the loader. We can't load the interrupt vectors
- directly into their target location, because the monitor
- ROM for the GHS Multi debugger barfs if we try.
- Unfortunately, Multi also doesn't deal correctly with ELF
- sections where the LMA and VMA differ (it just ignores the
- LMA), so we can't use that feature to work around the
- problem! What we do instead is just put the interrupt
- vectors into a normal section, and have the
- `mach_early_init' function for Midas boards do the
- necessary copying and relocation at runtime (this section
- basically only contains `jr' instructions, so it's not
- that hard). */
- . = ALIGN (0x10) ;
- __intv_load_start = . ;
- INTV_CONTENTS
- } > KRAM
-
- .root ALIGN (4096) : { ROOT_FS_CONTENTS } > SDRAM
-}
+++ /dev/null
-/* Linker script for the Midas labs RTE-V850E/ME2-CB evaluation board
- (CONFIG_RTE_CB_ME2), with kernel in SDRAM. */
-
-MEMORY {
- /* 128Kbyte of IRAM */
- IRAM : ORIGIN = 0x00000000, LENGTH = 0x00020000
-
- /* 32MB of SDRAM. */
- SDRAM : ORIGIN = 0x00800000, LENGTH = 0x02000000
-}
-
-#define KRAM SDRAM
-
-SECTIONS {
- .text : {
- __kram_start = . ;
- TEXT_CONTENTS
- INTV_CONTENTS /* copy to iRAM (0x0-0x620) */
- } > KRAM
-
- .data : {
- DATA_CONTENTS
- BSS_CONTENTS
- RAMK_INIT_CONTENTS
- __kram_end = . ;
- BOOTMAP_CONTENTS
- } > KRAM
-
- .root ALIGN (4096) : { ROOT_FS_CONTENTS } > SDRAM
-}
+++ /dev/null
-/* Linker script for the Midas labs RTE-NB85E-CB evaluation board
- (CONFIG_RTE_CB_NB85E), with the Multi debugger ROM monitor . */
-
-MEMORY {
- /* 1MB of SRAM; we can't use the last 96KB, because it's used by
- the monitor scratch-RAM. This memory is mirrored 4 times. */
- SRAM : ORIGIN = 0x03C00000, LENGTH = 0x000E8000
- /* Monitor scratch RAM; only the interrupt vectors should go here. */
- MRAM : ORIGIN = 0x03CE8000, LENGTH = 0x00018000
- /* 16MB of SDRAM. */
- SDRAM : ORIGIN = 0x01000000, LENGTH = 0x01000000
-}
-
-#ifdef CONFIG_RTE_CB_NB85E_KSRAM
-# define KRAM SRAM
-#else
-# define KRAM SDRAM
-#endif
-
-SECTIONS {
- /* We can't use RAMK_KRAM_CONTENTS because that puts the whole
- kernel in a single ELF segment, and the Multi debugger (which
- we use to load the kernel) appears to have bizarre problems
- dealing with it. */
-
- .text : {
- __kram_start = . ;
- TEXT_CONTENTS
- } > KRAM
-
- .data : {
- DATA_CONTENTS
- BSS_CONTENTS
- RAMK_INIT_CONTENTS
- __kram_end = . ;
- BOOTMAP_CONTENTS
-
- /* The address at which the interrupt vectors are initially
- loaded by the loader. We can't load the interrupt vectors
- directly into their target location, because the monitor
- ROM for the GHS Multi debugger barfs if we try.
- Unfortunately, Multi also doesn't deal correctly with ELF
- sections where the LMA and VMA differ (it just ignores the
- LMA), so we can't use that feature to work around the
- problem! What we do instead is just put the interrupt
- vectors into a normal section, and have the
- `mach_early_init' function for Midas boards do the
- necessary copying and relocation at runtime (this section
- basically only contains `jr' instructions, so it's not
- that hard). */
- . = ALIGN (0x10) ;
- __intv_load_start = . ;
- INTV_CONTENTS
- } > KRAM
-
- .root ALIGN (4096) : { ROOT_FS_CONTENTS } > SDRAM
-}
+++ /dev/null
-/* Linker script for the Midas labs RTE-NB85E-CB evaluation board
- (CONFIG_RTE_CB_NB85E). */
-
-MEMORY {
- LOW : ORIGIN = 0x0, LENGTH = 0x00100000
- /* 1MB of SRAM; we can't use the last 96KB, because it's used by
- the monitor scratch-RAM. This memory is mirrored 4 times. */
- SRAM : ORIGIN = 0x03C00000, LENGTH = 0x000E8000
- /* Monitor scratch RAM; only the interrupt vectors should go here. */
- MRAM : ORIGIN = 0x03CE8000, LENGTH = 0x00018000
- /* 16MB of SDRAM. */
- SDRAM : ORIGIN = 0x01000000, LENGTH = 0x01000000
-}
-
-#ifdef CONFIG_RTE_CB_NB85E_KSRAM
-# define KRAM SRAM
-#else
-# define KRAM SDRAM
-#endif
-
-SECTIONS {
- .intv : { INTV_CONTENTS } > LOW
- .sram : { RAMK_KRAM_CONTENTS } > KRAM
- .root : { ROOT_FS_CONTENTS } > SDRAM
-}
+++ /dev/null
-/* Linker script for the gdb v850e simulator (CONFIG_V850E_SIM). */
-
-MEMORY {
- /* Interrupt vectors. */
- INTV : ORIGIN = 0x0, LENGTH = 0xe0
- /* 16MB of RAM.
- This must match RAM_ADDR and RAM_SIZE in include/asm-v850/sim.h */
- RAM : ORIGIN = 0x8F000000, LENGTH = 0x01000000
-}
-
-SECTIONS {
- .intv : { INTV_CONTENTS } > INTV
- .ram : { RAMK_KRAM_CONTENTS } > RAM
-}
+++ /dev/null
-/* Linker script for the sim85e2c simulator, which is a verilog simulation of
- the V850E2 NA85E2C cpu core (CONFIG_V850E2_SIM85E2C). */
-
-MEMORY {
- /* 1MB of `instruction RAM', starting at 0.
- Instruction fetches are much faster from IRAM than from DRAM.
- This should match IRAM_ADDR in "include/asm-v580/sim85e2c.h". */
- IRAM : ORIGIN = 0x00000000, LENGTH = 0x00100000
-
- /* 1MB of `data RAM', below and contiguous with the I/O space.
- Data fetches are much faster from DRAM than from IRAM.
- This should match DRAM_ADDR in "include/asm-v580/sim85e2c.h". */
- DRAM : ORIGIN = 0xfff00000, LENGTH = 0x000ff000
- /* We have to load DRAM at a mirror-address of 0x1ff00000,
- because the simulator's preprocessing script isn't smart
- enough to deal with the above LMA. */
- DRAM_LOAD : ORIGIN = 0x1ff00000, LENGTH = 0x000ff000
-
- /* `external ram' (CS1 area), comes after IRAM.
- This should match ERAM_ADDR in "include/asm-v580/sim85e2c.h". */
- ERAM : ORIGIN = 0x00100000, LENGTH = 0x07f00000
-
- /* Dynamic RAM; uses memory controller. */
- /* SDRAM : ORIGIN = 0x10000000, LENGTH = 0x01000000 */
- SDRAM : ORIGIN = 0x10000000, LENGTH = 0x00200000/*use 2MB*/
-}
-
-SECTIONS {
- .iram : {
- INTV_CONTENTS
- *arch/v850/kernel/head.o
- *(.early.text)
- } > IRAM
- .dram : {
- _memcons_output = . ;
- . = . + 0x8000 ;
- _memcons_output_end = . ;
- } > DRAM
- .sdram : {
- /* We stick console output into a buffer here. */
- RAMK_KRAM_CONTENTS
- ROOT_FS_CONTENTS
- } > SDRAM
-}
projects / linux / commitdiff