[PATCH] ppc32: Workaround new MPC745x CPU erratas

The latest versions of Motorola erratas for the MPC745x CPUs (and 744x)
adds a couple of nasty ones for which we really want workarounds in the
kernel. One is to disable the BTIC branch target cache on some revs
(too bad for performances...) and the other one is to force cacheable
memory pages to always be marked as SMP coherent even on UP systems (I
didn't measure significant perfs impact with this one).

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

diff --git a/arch/ppc/kernel/cpu_setup_6xx.S b/arch/ppc/kernel/cpu_setup_6xx.S
index 9e4e48ffb641bee3803bfb74873e680fea48113a..ee0705c6e3abc45b08e247f517f977bcb26ba99c 100644 (file)
--- a/arch/ppc/kernel/cpu_setup_6xx.S
+++ b/arch/ppc/kernel/cpu_setup_6xx.S
@@ -218,7 +218,10 @@ setup_745x_specifics:
 
        /* All of the bits we have to set.....
         */
-       ori     r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE | HID0_BTIC | HID0_LRSTK
+       ori     r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE | HID0_LRSTK
+BEGIN_FTR_SECTION
+       ori     r11,r11,HID0_BTIC
+END_FTR_SECTION_IFCLR(CPU_FTR_NO_BTIC)
 BEGIN_FTR_SECTION
        oris    r11,r11,HID0_DPM@h      /* enable dynamic power mgmt */
 END_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM)

diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c
index 675d9230d221b6f4d1bdf55742052901d1269d06..b60fa998bbced8f6b935ba9e2cb8394530440dce 100644 (file)
--- a/arch/ppc/kernel/cputable.c
+++ b/arch/ppc/kernel/cputable.c
@@ -55,7 +55,8 @@ extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spe
 #endif
 
 /* We need to mark all pages as being coherent if we're SMP or we
- * have a 754x and an MPC107 host bridge. */
+ * have a 754x and an MPC107 host bridge.
+ */
 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
 #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
 #else
@@ -263,7 +264,7 @@ struct cpu_spec     cpu_specs[] = {
        CPU_FTR_COMMON |
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
-       CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450,
+       CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_745x
@@ -274,7 +275,7 @@ struct cpu_spec     cpu_specs[] = {
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
        CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
-       CPU_FTR_L3_DISABLE_NAP,
+       CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_745x
@@ -284,7 +285,8 @@ struct cpu_spec     cpu_specs[] = {
        CPU_FTR_COMMON |
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
-       CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR,
+       CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
+       CPU_FTR_NEED_COHERENT,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_745x
@@ -294,7 +296,8 @@ struct cpu_spec     cpu_specs[] = {
        CPU_FTR_COMMON |
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
-       CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS,
+       CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS |
+       CPU_FTR_NEED_COHERENT,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_745x
@@ -305,7 +308,7 @@ struct cpu_spec     cpu_specs[] = {
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
        CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
-       CPU_FTR_L3_DISABLE_NAP | CPU_FTR_HAS_HIGH_BATS,
+       CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_745x
@@ -316,18 +319,40 @@ struct cpu_spec   cpu_specs[] = {
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
        CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
-       CPU_FTR_HAS_HIGH_BATS,
+       CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
+       COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+       32, 32,
+       __setup_cpu_745x
+    },
+    {  /* 7447/7457 Rev 1.0 */
+       0xffffffff, 0x80020100, "7447/7457",
+       CPU_FTR_COMMON |
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+       CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+       CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
+       CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
+       COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+       32, 32,
+       __setup_cpu_745x
+    },
+    {  /* 7447/7457 Rev 1.1 */
+       0xffffffff, 0x80020101, "7447/7457",
+       CPU_FTR_COMMON |
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+       CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+       CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
+       CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_745x
     },
-    {  /* 7457 */
-       0xffff0000, 0x80020000, "7457",
+    {  /* 7447/7457 Rev 1.2 and later */
+       0xffff0000, 0x80020000, "7447/7457",
        CPU_FTR_COMMON |
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
        CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
-       CPU_FTR_HAS_HIGH_BATS,
+       CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_745x
@@ -338,7 +363,7 @@ struct cpu_spec     cpu_specs[] = {
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
        CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
-       CPU_FTR_HAS_HIGH_BATS,
+       CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_745x

diff --git a/include/asm-ppc/cputable.h b/include/asm-ppc/cputable.h
index 4c07a0cac979c55da618bda9d13f9dbcb69f08f5..fcdb87db389bcd0856331b5158058cf73050b854 100644 (file)
--- a/include/asm-ppc/cputable.h
+++ b/include/asm-ppc/cputable.h
@@ -76,6 +76,7 @@ extern struct cpu_spec                *cur_cpu_spec[];
 #define CPU_FTR_NO_DPM                 0x00008000
 #define CPU_FTR_HAS_HIGH_BATS          0x00010000
 #define CPU_FTR_NEED_COHERENT           0x00020000
+#define CPU_FTR_NO_BTIC                        0x00040000
 
 #ifdef __ASSEMBLY__