[PATCH] M68k update (part 9)

M68k cache handling updates
  - Add missing definition of L1_CACHE_SHIFT
  - Define L1_CACHE_BYTES in terms of L1_CACHE_SHIFT
  - Add missing include
  - Fix address types and casts

diff --git a/include/asm-m68k/cache.h b/include/asm-m68k/cache.h
index 52262e891ed8c07b1c6aea95c9e2f68896c3f767..fed3fd30de7e468797a85ff5945119c436f92fce 100644 (file)
--- a/include/asm-m68k/cache.h
+++ b/include/asm-m68k/cache.h
@@ -5,6 +5,7 @@
 #define __ARCH_M68K_CACHE_H
 
 /* bytes per L1 cache line */
-#define        L1_CACHE_BYTES  16
+#define        L1_CACHE_SHIFT  4
+#define        L1_CACHE_BYTES  (1<< L1_CACHE_SHIFT)
 
 #endif

diff --git a/include/asm-m68k/cacheflush.h b/include/asm-m68k/cacheflush.h
index 089a570d552a338394ed6511bc0819e2a610c6c8..078523b767ba3a3d92d2f6490355496dc445183b 100644 (file)
--- a/include/asm-m68k/cacheflush.h
+++ b/include/asm-m68k/cacheflush.h
@@ -1,6 +1,8 @@
 #ifndef _M68K_CACHEFLUSH_H
 #define _M68K_CACHEFLUSH_H
 
+#include <linux/mm.h>
+
 /*
  * Cache handling functions
  */
@@ -104,15 +106,15 @@ extern inline void flush_cache_page(struct vm_area_struct *vma,
 
 /* Push the page at kernel virtual address and clear the icache */
 /* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
-#define flush_page_to_ram(page) __flush_page_to_ram((unsigned long) page_address(page))
-extern inline void __flush_page_to_ram(unsigned long address)
+#define flush_page_to_ram(page) __flush_page_to_ram(page_address(page))
+extern inline void __flush_page_to_ram(void *vaddr)
 {
        if (CPU_IS_040_OR_060) {
                __asm__ __volatile__("nop\n\t"
                                     ".chip 68040\n\t"
                                     "cpushp %%bc,(%0)\n\t"
                                     ".chip 68k"
-                                    : : "a" (__pa((void *)address)));
+                                    : : "a" (__pa(vaddr)));
        } else {
                unsigned long _tmp;
                __asm__ __volatile__("movec %%cacr,%0\n\t"