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4 months agopinctrl: qcom: eliza: Merge QUP1_SE4 lanes in groups
Abel Vesa [Fri, 15 May 2026 11:21:52 +0000 (14:21 +0300)]
pinctrl: qcom: eliza: Merge QUP1_SE4 lanes in groups

QUP1_SE4 uses GPIO36 and GPIO37 for two selectable lane pairs. The
current driver exposes lanes 0, 1, 2 and 3 as independent functions.
However, since these are usually configured in pairs in devicetree,
it makes more sense to merge them into groups.

So merge the per-lane functions into qup1_se4_01 and qup1_se4_23, and list
both GPIO36 and GPIO37 in each function group.

Fixes: 4f5b1f4e770b ("pinctrl: qcom: eliza: Split QUP1_SE4 lanes")
Suggested-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agodt-bindings: pinctrl: qcom,eliza-tlmm: Merge QUP1_SE4 lane functions
Abel Vesa [Fri, 15 May 2026 11:21:51 +0000 (14:21 +0300)]
dt-bindings: pinctrl: qcom,eliza-tlmm: Merge QUP1_SE4 lane functions

QUP1_SE4 uses GPIO36 and GPIO37 for two selectable lane pairs. The
previous split added one function name per lane. Since these are usually
configured in pairs in devicetree, it makes more sense to have them
grouped.

So replace the per-lane qup1_se4_l[0-3] names with names for the two
selectable pairs, qup1_se4_01 and qup1_se4_23.

Fixes: 1bd5c56253c5 ("dt-bindings: pinctrl: qcom,eliza-tlmm: Split QUP1_SE4 lanes")
Suggested-by: Bjorn Andersson <andersson@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: Add OF dependency for PINCTRL_GENERIC_MUX
Frank Li [Wed, 8 Apr 2026 05:07:01 +0000 (01:07 -0400)]
pinctrl: Add OF dependency for PINCTRL_GENERIC_MUX

Add an explicit OF dependency for PINCTRL_GENERIC_MUX to ensure the
generic mux support is only enabled when device tree is available.

Also fix the stub implementation of pinctrl_generic_to_map() by correcting
its last argument to match the non-stub prototype.

Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202604072013.aI84l57L-lkp@intel.com/
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: qcom: spmi-gpio: Add PM8010 GPIO support
Fenglin Wu [Fri, 8 May 2026 05:34:08 +0000 (22:34 -0700)]
pinctrl: qcom: spmi-gpio: Add PM8010 GPIO support

Add PM8010 GPIO support with its compatible string and match data.

Signed-off-by: Fenglin Wu <fenglin.wu@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agodt-bindings: pinctrl: qcom,pmic-gpio: Document PM8010 GPIO support
Fenglin Wu [Fri, 8 May 2026 05:34:07 +0000 (22:34 -0700)]
dt-bindings: pinctrl: qcom,pmic-gpio: Document PM8010 GPIO support

Update the binding documentation to include the compatible string for
PM8010 PMIC which has 2 GPIO modules.

Signed-off-by: Fenglin Wu <fenglin.wu@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: qcom: Add Shikra pinctrl driver
Komal Bajaj [Tue, 12 May 2026 13:25:44 +0000 (18:55 +0530)]
pinctrl: qcom: Add Shikra pinctrl driver

Add pinctrl driver for TLMM block found in Shikra SoC.

Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agodt-bindings: pinctrl: qcom: Document Shikra Top Level Mode Multiplexer
Komal Bajaj [Tue, 12 May 2026 13:25:43 +0000 (18:55 +0530)]
dt-bindings: pinctrl: qcom: Document Shikra Top Level Mode Multiplexer

Add a DeviceTree binding to describe the TLMM block on Qualcomm's
Shikra SoC.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agoMerge tag 'renesas-pinctrl-for-v7.2-tag1' of git://git.kernel.org/pub/scm/linux/kerne...
Linus Walleij [Sat, 23 May 2026 08:46:52 +0000 (10:46 +0200)]
Merge tag 'renesas-pinctrl-for-v7.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v7.2

  - Save/restore more registers during suspend/resume on the RZ/G2L and
    RZ/V2H SoC families,
  - Add support for the RZ/G3L (R9A08G046) SoC,
  - Add support for pinconf-groups in debugfs on EMMA Mobile,
    SH/R-Mobile, R-Car, RZ/G1, and RZ/G2 SoCs,
  - Miscellaneous fixes and improvements.

Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: renesas: sh-pfc: Implement .pin_config_group_get() callback
Geert Uytterhoeven [Thu, 30 Apr 2026 15:24:42 +0000 (17:24 +0200)]
pinctrl: renesas: sh-pfc: Implement .pin_config_group_get() callback

When reading /sys/kernel/debug/pinctrl/*.pinctrl-sh-pfc/pinconf-groups
while CONFIG_DEBUG_PINCTRL is enabled, the user is confronted with a
seemlingly endless stream of identical messages on the console:

    sh-pfc e6060000.pinctrl: cannot get configuration for pin group, missing group config get function in driver

Fix this by implementing the sh_pfc_pinconf_ops.pin_config_group_get()
callback.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/130ce567f23fd6eef8f5fa7273480a0e3ff2d1d9.1777562482.git.geert+renesas@glider.be
4 months agoMerge branch 'ib-mux-pinctrl' into devel
Linus Walleij [Mon, 11 May 2026 20:33:30 +0000 (22:33 +0200)]
Merge branch 'ib-mux-pinctrl' into devel

4 months agomux: describe np parameter in __devm_mux_state_get()
Frank Li [Thu, 7 May 2026 15:21:14 +0000 (11:21 -0400)]
mux: describe np parameter in __devm_mux_state_get()

Add a description for the 'np' parameter of __devm_mux_state_get() to fix
build warning.

Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202605061502.ullLjmtN-lkp@intel.com/
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agodt-bindings: pinctrl: mediatek,mt65xx: Add MT6392 pinctrl
Luca Leonardo Scorcia [Mon, 20 Apr 2026 21:30:03 +0000 (22:30 +0100)]
dt-bindings: pinctrl: mediatek,mt65xx: Add MT6392 pinctrl

Add a compatible for the pinctrl device of the MT6392 PMIC, a variant of
the already supported MT6397.

Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agodt-bindings: pinctrl: mediatek: mt8188: allow gpio hogs
Icenowy Zheng [Mon, 4 May 2026 07:27:47 +0000 (15:27 +0800)]
dt-bindings: pinctrl: mediatek: mt8188: allow gpio hogs

Add gpio hogs subnode rules to the MT8188 pinctrl binding.

Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: realtek: Fix typo
Thomas Weber [Tue, 5 May 2026 12:24:43 +0000 (14:24 +0200)]
pinctrl: realtek: Fix typo

STRENGH -> STRENGTH

Signed-off-by: Thomas Weber <thomas.weber@corscience.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: qcom: Fix typo
Thomas Weber [Tue, 5 May 2026 12:24:12 +0000 (14:24 +0200)]
pinctrl: qcom: Fix typo

STRENGH -> STRENGTH

Signed-off-by: Thomas Weber <thomas.weber@corscience.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: aspeed: Add AST2700 SoC0 support
Billy Tsai [Wed, 6 May 2026 08:06:20 +0000 (16:06 +0800)]
pinctrl: aspeed: Add AST2700 SoC0 support

Add pinctrl support for the SoC0 instance of the ASPEED AST2700.

AST2700 consists of two interconnected SoC instances, each with its own
pinctrl register block.

The SoC0 pinctrl hardware closely follows the design found in previous
ASPEED BMC generations, allowing the driver to build upon the common
ASPEED pinctrl infrastructure.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agodt-bindings: pinctrl: Add aspeed,ast2700-soc0-pinctrl
Billy Tsai [Wed, 6 May 2026 08:06:18 +0000 (16:06 +0800)]
dt-bindings: pinctrl: Add aspeed,ast2700-soc0-pinctrl

Add a device tree binding for the pin controller found in the
ASPEED AST2700 SoC0.

The controller manages various peripheral functions such as eMMC, USB,
VGA DDC, JTAG, and PCIe root complex signals.

Describe the AST2700 SoC0 pin controller using standard pin multiplexing
and configuration properties.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: mediatek: common-v1: bypass pinctrl GPIO layer in set GPIO direction
Chen-Yu Tsai [Tue, 5 May 2026 10:40:55 +0000 (18:40 +0800)]
pinctrl: mediatek: common-v1: bypass pinctrl GPIO layer in set GPIO direction

pinctrl_gpio_direction_input() / pinctrl_gpio_direction_output() take
the pinctrl mutex. This causes a gpiochip operations to need to sleep.
Worse yet, the .can_sleep field in the gpiochip is not set. This causes
the shared GPIO proxy to trip over, as it uses gpiod_cansleep() to check
whether it can use a spinlock or needs a mutex. In this case, it ends
up taking a spinlock, then calls pinctrl_gpio_direction_output(), which
takes a mutex. This causes a huge warning.

Since the Mediatek hardware has separate clear/set registers, there is
no risk of clobbering other bits like with a read-modify-write pattern.
Also, once the GPIO function is selected / muxed in, further GPIO
operations do not involve pinctrl operations or state. The GPIO direction
and level values do not require toggling the pinmux or any other pin config
options.

Switch to directly calling mtk_pmx_gpio_set_direction() in the GPIO set
direction callbacks to avoid taking the pinctrl mutex. Drop the
.gpio_set_direction field in mtk_pmx_ops to signal we are no longer using
the pinctrl GPIO layer for setting the direction.

Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: mediatek: paris: bypass pinctrl GPIO layer in set GPIO direction
Chen-Yu Tsai [Tue, 5 May 2026 10:39:57 +0000 (18:39 +0800)]
pinctrl: mediatek: paris: bypass pinctrl GPIO layer in set GPIO direction

pinctrl_gpio_direction_input() / pinctrl_gpio_direction_output() take
the pinctrl mutex. This causes a gpiochip operations to need to sleep.
Worse yet, the .can_sleep field in the gpiochip is not set. This causes
the shared GPIO proxy to trip over, as it uses gpiod_cansleep() to check
whether it can use a spinlock or needs a mutex. In this case, it ends
up taking a spinlock, then calls pinctrl_gpio_direction_output(), which
takes a mutex. This causes a huge warning.

While this class of Mediatek hardware does not have separate clear/set
registers, the pinctrl context has a spinlock that is taken whenever
a register read-modify-write is done. Also, once the GPIO function is
selected / muxed in, further GPIO operations do not involve pinctrl
operations or state. The GPIO direction and level values do not require
toggling the pinmux or any other pin config options.

Switch to directly calling mtk_pinmux_gpio_set_direction() in the GPIO
set direction callbacks to avoid taking the pinctrl mutex. Drop the
.gpio_set_direction field in mtk_pmxops to signal we are no longer using
the pinctrl GPIO layer for setting the direction.

Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: renesas: rzv2m: Fix type in .pin_config_group_get() callback
Geert Uytterhoeven [Thu, 30 Apr 2026 15:33:17 +0000 (17:33 +0200)]
pinctrl: renesas: rzv2m: Fix type in .pin_config_group_get() callback

On 64-bit platforms, "unsigned long" is 64-bit.  Hence checking if all
"unsigned long" configuration values are equal should be done using an
"unsigned long" temporary.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/4bcb78b40d685b0aab8c3150d379240ffb765b37.1777562725.git.geert+renesas@glider.be
4 months agopinctrl: renesas: rzg2l: Fix type in .pin_config_group_get() callback
Geert Uytterhoeven [Thu, 30 Apr 2026 15:33:16 +0000 (17:33 +0200)]
pinctrl: renesas: rzg2l: Fix type in .pin_config_group_get() callback

On 64-bit platforms, "unsigned long" is 64-bit.  Hence checking if all
"unsigned long" configuration values are equal should be done using an
"unsigned long" temporary.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://patch.msgid.link/6befae30f129daffd94f7a9507d874443e444a21.1777562725.git.geert+renesas@glider.be
4 months agopinctrl: renesas: rzg2l: Add support for clone channel control
Biju Das [Thu, 30 Apr 2026 09:34:12 +0000 (10:34 +0100)]
pinctrl: renesas: rzg2l: Add support for clone channel control

The RZ/G3L SoC has some IP such as I2C ch{2,3},SCIF ch{3,4,5},
RSPI ch{1,2} and RSCI ch{1,2,3} need to control the clone channel for
proper operation. As per the RZ/G3L hardware manual, the clone channel
setting is to be done before the mux setting.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260430093422.74812-8-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 months agopinctrl: renesas: rzg2l: Simplify rzg2l_pinctrl_set_mux()
Biju Das [Thu, 30 Apr 2026 09:34:11 +0000 (10:34 +0100)]
pinctrl: renesas: rzg2l: Simplify rzg2l_pinctrl_set_mux()

The port and function selectors are evaluated multiple times
in rzg2l_pinctrl_set_mux(). Simplify the function by dropping
dupicate evaluation storing them in local variables.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260430093422.74812-7-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 months agopinctrl: renesas: rzg2l: Add support for RZ/G3L SoC
Biju Das [Thu, 30 Apr 2026 09:34:10 +0000 (10:34 +0100)]
pinctrl: renesas: rzg2l: Add support for RZ/G3L SoC

Add pinctrl driver support for RZ/G3L SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260430093422.74812-6-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 months agopinctrl: renesas: rzg2l: Update OEN pin validation to use exact match
Biju Das [Thu, 30 Apr 2026 09:34:09 +0000 (10:34 +0100)]
pinctrl: renesas: rzg2l: Update OEN pin validation to use exact match

The RZ/G2L SoC uses pin 0 from a port for OEN while RZ/G3L uses pin 1. The
existing greater-than comparison against oen_max_pin in
rzg2l_pin_to_oen_bit() would incorrectly accept any pin below that value
rather than enforcing the single valid OEN pin for each SoC. Replace the
range check with an exact equality test so that only the designated OEN
pin is accepted.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260430093422.74812-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 months agopinctrl: renesas: rzg2l: Add support for selecting power source for {WDT,AWO,ISO}
Biju Das [Thu, 30 Apr 2026 09:34:08 +0000 (10:34 +0100)]
pinctrl: renesas: rzg2l: Add support for selecting power source for {WDT,AWO,ISO}

The RZ/G3L SoC has support for setting power source that are not
controlled by the following voltage control registers:
  - SD_CH{0,1,2}_POC, XSPI_POC, ETH{0,1}_POC, I3C_SET.POC

Add support for selecting voltages using OTHER_POC register for
setting I/O domain voltage for WDT, ISO and AWO by extending
rzg2l_caps_to_pwr_reg() with a mask output parameter so that callers
callers can identify which bit(s) within OTHER_POC correspond to the
requested domain. Update rzg2l_get_power_source() to extract the
relevant bit field via field_get() when reading OTHER_POC, and update
rzg2l_set_power_source() to perform a read-modify-write under the
spinlock when writing to OTHER_POC, since multiple domains share the
same register.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260430093422.74812-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 months agopinctrl: renesas: rzg2l: Make QSPI register handling conditional
Biju Das [Thu, 30 Apr 2026 09:34:07 +0000 (10:34 +0100)]
pinctrl: renesas: rzg2l: Make QSPI register handling conditional

The QSPI register at offset 0x3008 is not present on all SoCs supported by
the RZ/G2L pinctrl driver. Unconditionally reading and writing this
register during suspend/resume on hardware that lacks it can cause
undefined behaviour.

Add a qspi field to rzg2l_register_offsets to allow per-SoC declaration of
the QSPI register offset, and guard the suspend/resume accesses with a
check on that field. Populate the offset only for the RZ/{G2L,G2LC,G2UL,
Five} hardware configuration, which is where the register is known to
exist.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260430093422.74812-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 months agoMerge tag 'renesas-r9a08g046-dt-binding-defs-tag2' into renesas-pinctrl-for-v7.2
Geert Uytterhoeven [Mon, 11 May 2026 09:06:50 +0000 (11:06 +0200)]
Merge tag 'renesas-r9a08g046-dt-binding-defs-tag2' into renesas-pinctrl-for-v7.2

Renesas RZ/G3L DT Pin Control Binding Definitions

Pin Control DT bindings and binding definitions for the Renesas RZ/G3L
(R9A08G046) SoC, shared by driver and DT source files.

4 months agodt-bindings: pinctrl: renesas: Document RZ/G3L SoC
Biju Das [Thu, 30 Apr 2026 09:34:06 +0000 (10:34 +0100)]
dt-bindings: pinctrl: renesas: Document RZ/G3L SoC

Add documentation for the pin controller found on the Renesas RZ/G3L
(R9A08G046) SoC. The RZ/G3L PFC is similar to the RZ/G3S SoC but has
more pins.

Also add header file similar to RZ/G3E and RZ/V2H as it has alpha
numeric ports.

Document renesas,clonech property for controlling clone channel
control register located on SYSC IP block on RZ/G3L SoC.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260430093422.74812-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 months agodt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document reset-names
Biju Das [Tue, 17 Mar 2026 10:16:14 +0000 (10:16 +0000)]
dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document reset-names

All SoCs have multiple resets.  Document the reset-names property.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260317101627.174491-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 months agopinctrl: qcom: nord: remove duplicated pin function
Bartosz Golaszewski [Wed, 6 May 2026 09:00:06 +0000 (11:00 +0200)]
pinctrl: qcom: nord: remove duplicated pin function

The qdss_cti function is initialized twice in the nord_functions array.
Remove the duplicate entry.

Fixes: c24dd0826f06 ("pinctrl: qcom: add the TLMM driver for the Nord platforms")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202605061633.BJLI5voT-lkp@intel.com/
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agoMerge branch 'ib-qcom-configs' into devel
Linus Walleij [Wed, 6 May 2026 19:10:24 +0000 (21:10 +0200)]
Merge branch 'ib-qcom-configs' into devel

4 months agopinctrl: qcom: Make important drivers default (1)
Krzysztof Kozlowski [Tue, 28 Apr 2026 16:35:49 +0000 (18:35 +0200)]
pinctrl: qcom: Make important drivers default (1)

The main SoC TLMM (Top-Level Multiplexer) pin controller drivers are
essential for booting up SoCs and are not really optional for a given
platform.  Kernel should not ask users choice of drivers when that
choice is obvious and known to the developers that answer should be
'yes' or 'module'.

Switch all Qualcomm TLMM pin controller drivers to a default 'yes' for
ARCH_QCOM.  This has impact:

1. arm64 defconfig: enable PINCTRL_SM7150, PINCTRL_IPQ9650 and
   PINCTRL_HAWI, which were not selected before but should be, because
   these platforms need them for proper boot.

2. arm qcom_defconfig: no changes.

3. arm multi_v7 defconfig: enable drivers necessary to boot ARM 32-bit
   platforms, which are already enabled on qcom_defconfig.

4. COMPILE_TEST builds: enable by default all drivers for arm or arm64
   builds, whenever ARCH_QCOM is selected.  This has impact on build
   time and feels logical, because if one selects ARCH_QCOM then
   probably by default wants to build test it entirely.  Kernels with
   COMPILE_TEST are not supposed to be used for booting.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
[linusw@kernel.org: Split off the defconfig changes to a separate patch]
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: qcom: Make important drivers default (2)
Krzysztof Kozlowski [Tue, 28 Apr 2026 16:35:49 +0000 (18:35 +0200)]
pinctrl: qcom: Make important drivers default (2)

The main SoC TLMM (Top-Level Multiplexer) pin controller drivers are
essential for booting up SoCs and are not really optional for a given
platform.  Kernel should not ask users choice of drivers when that
choice is obvious and known to the developers that answer should be
'yes' or 'module'.

Switch all Qualcomm TLMM pin controller drivers to a default 'yes' for
ARCH_QCOM.  This has impact:

1. arm64 defconfig: enable PINCTRL_SM7150, PINCTRL_IPQ9650 and
   PINCTRL_HAWI, which were not selected before but should be, because
   these platforms need them for proper boot.

2. arm qcom_defconfig: no changes.

3. arm multi_v7 defconfig: enable drivers necessary to boot ARM 32-bit
   platforms, which are already enabled on qcom_defconfig.

4. COMPILE_TEST builds: enable by default all drivers for arm or arm64
   builds, whenever ARCH_QCOM is selected.  This has impact on build
   time and feels logical, because if one selects ARCH_QCOM then
   probably by default wants to build test it entirely.  Kernels with
   COMPILE_TEST are not supposed to be used for booting.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
[linusw@kernel.org: split off defconfig changes to its own patch]
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: rockchip: Move MODULE_DEVICE_TABLE next to the table itself
Krzysztof Kozlowski [Tue, 5 May 2026 09:43:18 +0000 (11:43 +0200)]
pinctrl: rockchip: Move MODULE_DEVICE_TABLE next to the table itself

By convention MODULE_DEVICE_TABLE() immediately follows the ID table it
exports, because this is easier to read and verify.  It also makes more
sense since #ifdef for ACPI or OF could hide both of them.

Most of the pin controller drivers already have this correctly placed,
so adjust the other drivers.  No functional impact.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: bcm: Move MODULE_DEVICE_TABLE next to the table itself
Krzysztof Kozlowski [Tue, 5 May 2026 09:43:17 +0000 (11:43 +0200)]
pinctrl: bcm: Move MODULE_DEVICE_TABLE next to the table itself

By convention MODULE_DEVICE_TABLE() immediately follows the ID table it
exports, because this is easier to read and verify.  It also makes more
sense since #ifdef for ACPI or OF could hide both of them.

Most of the pin controller drivers already have this correctly placed,
so adjust the other drivers.  No functional impact.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: qcom: Move MODULE_DEVICE_TABLE next to the table itself
Krzysztof Kozlowski [Tue, 5 May 2026 09:34:45 +0000 (11:34 +0200)]
pinctrl: qcom: Move MODULE_DEVICE_TABLE next to the table itself

By convention MODULE_DEVICE_TABLE() immediately follows the ID table it
exports, because this is easier to read and verify.  It also makes more
sense since #ifdef for ACPI or OF could hide both of them.

Some Qualcomm pin controller drivers already have this correctly placed,
so adjust the other drivers.  No functional impact.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agodt-bindings: pinctrl: qcom: move gpio-hog schema to tlmm-common
Swati Agarwal [Mon, 4 May 2026 06:49:36 +0000 (12:19 +0530)]
dt-bindings: pinctrl: qcom: move gpio-hog schema to tlmm-common

Qualcomm TLMM-based pin controllers share the same gpio-hog binding
semantics across multiple SoCs. The gpio-hog pattern currently defined in
qcom,ipq4019-pinctrl.yaml and qcom,sdm845-pinctrl.yaml are not SOC specific
and applies to all TLMM controllers.

Move the gpio-hog patternProperties definition to qcom,tlmm-common.yaml so
that it can be reused by other Qualcomm TLMM pinctrl bindings and avoid
schema duplication.

Signed-off-by: Swati Agarwal <swati.agarwal@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: sophgo: allocate power_cfg with priv
Rosen Penev [Thu, 30 Apr 2026 22:04:09 +0000 (15:04 -0700)]
pinctrl: sophgo: allocate power_cfg with priv

Use a flexible array member to combine allocations and simplify code
slightly.

Signed-off-by: Rosen Penev <rosenp@gmail.com>
[linusw@kernel.org: add a counter and __counted_by() annotation]
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: single: Fix type in .pin_config_group_get() callback
Geert Uytterhoeven [Thu, 30 Apr 2026 15:33:18 +0000 (17:33 +0200)]
pinctrl: single: Fix type in .pin_config_group_get() callback

On 64-bit platforms, "unsigned long" is 64-bit.  Hence checking if all
"unsigned long" configuration values are equal should be done using an
"unsigned long" temporary.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: mediatek: moore: Fix type in .pin_config_group_get() callback
Geert Uytterhoeven [Thu, 30 Apr 2026 15:33:15 +0000 (17:33 +0200)]
pinctrl: mediatek: moore: Fix type in .pin_config_group_get() callback

On 64-bit platforms, "unsigned long" is 64-bit.  Hence checking if all
"unsigned long" configuration values are equal should be done using an
"unsigned long" temporary.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: ingenic: Fix type in .pin_config_group_get() callback
Geert Uytterhoeven [Thu, 30 Apr 2026 15:33:14 +0000 (17:33 +0200)]
pinctrl: ingenic: Fix type in .pin_config_group_get() callback

On 64-bit platforms, "unsigned long" is 64-bit.  Hence checking if all
"unsigned long" configuration values are equal should be done using an
"unsigned long" temporary.

While Ingenic is a 32-bit platform, it is still better to use the
correct type, to serve as an example.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: equilibrium: Fix type in .pin_config_group_get() callback
Geert Uytterhoeven [Thu, 30 Apr 2026 15:33:13 +0000 (17:33 +0200)]
pinctrl: equilibrium: Fix type in .pin_config_group_get() callback

On 64-bit platforms, "unsigned long" is 64-bit.  Hence checking if all
"unsigned long" configuration values are equal should be done using an
"unsigned long" temporary.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: airoha: Fix type in .pin_config_group_get() callback
Geert Uytterhoeven [Thu, 30 Apr 2026 15:33:12 +0000 (17:33 +0200)]
pinctrl: airoha: Fix type in .pin_config_group_get() callback

On 64-bit platforms, "unsigned long" is 64-bit.  Hence checking if all
"unsigned long" configuration values are equal should be done using an
"unsigned long" temporary.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: qcom: Add SM6350 LPASS LPI TLMM
Luca Weiss [Thu, 30 Apr 2026 07:10:43 +0000 (09:10 +0200)]
pinctrl: qcom: Add SM6350 LPASS LPI TLMM

Add support for the pin controller block on SM6350 Low Power Island.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
[linusw@kernel.org: fixed up Kconfig entry]
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: qcom: lpass-lpi: Add ability to use SPARE_1 for slew control
Luca Weiss [Thu, 30 Apr 2026 07:10:42 +0000 (09:10 +0200)]
pinctrl: qcom: lpass-lpi: Add ability to use SPARE_1 for slew control

On some platforms like SM6350 (Bitra), some pins have their slew
controlled with the SPARE_1 register. Add support for that.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agodt-bindings: pinctrl: qcom: Add SM6350 LPI pinctrl
Luca Weiss [Thu, 30 Apr 2026 07:10:41 +0000 (09:10 +0200)]
dt-bindings: pinctrl: qcom: Add SM6350 LPI pinctrl

Add bindings for pin controller in Low Power Audio SubSystem (LPASS).

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: qcom: Remove unused macro definitions
Maulik Shah [Wed, 29 Apr 2026 06:15:45 +0000 (11:45 +0530)]
pinctrl: qcom: Remove unused macro definitions

Remove SDC_QDSD_PINGROUP, QUP_I3C and UFS_RESET macros as on some
platforms they are unused.

No functional impact.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: add generic board-level pinctrl driver using mux framework
Frank Li [Mon, 4 May 2026 23:54:39 +0000 (19:54 -0400)]
pinctrl: add generic board-level pinctrl driver using mux framework

Many boards use on-board mux chips (often controlled by GPIOs from an I2C
expander) to switch shared signals between peripherals.

Add a generic pinctrl driver built on top of the mux framework to
centralize mux handling and avoid probe ordering issues. Keep board-level
routing out of individual drivers and supports boot-time only mux
selection.

Ensure correct probe ordering, especially when the GPIO expander is probed
later.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: add optional .release_mux() callback
Frank Li [Mon, 4 May 2026 23:54:38 +0000 (19:54 -0400)]
pinctrl: add optional .release_mux() callback

Add an optional .release_mux() callback to struct pinmux_ops.

Some drivers acquire additional resources in .set_mux(), such as software
locks. These resources may need to be released when the mux function is no
longer active. Introducing a dedicated .release_mux() callback allows
drivers to clean up such resources.

The callback is optional and does not affect existing drivers.

Commit 2243a87d90b42 ("pinctrl: avoid duplicated calling
enable_pinmux_setting for a pin") removed the .disable() callback
to resolve two issues:

  1. desc->mux_usecount increasing monotonically
  2. Hardware glitches caused by repeated .disable()/.enable() calls

Adding .release_mux() does not reintroduce those problems. The callback is
intended only for releasing driver-side resources (e.g. locks) and must not
modify hardware registers.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: extract pinctrl_generic_to_map() from pinctrl_generic_pins_function_dt_node_...
Frank Li [Mon, 4 May 2026 23:54:37 +0000 (19:54 -0400)]
pinctrl: extract pinctrl_generic_to_map() from pinctrl_generic_pins_function_dt_node_to_map()

Refactor pinctrl_generic_pins_function_dt_subnode_to_map() by separating DT
parsing logic from map creation. Introduce a new helper
pinctrl_generic_to_map() to handle mapping to kernel data structures, while
keeping DT property parsing in the subnode function.

Improve code structure and enables easier reuse for platforms using
different DT properties (e.g. pinmux) without modifying the
dt_node_to_map-style callback API. Avoid unnecessary coupling to
pinctrl_generic_pins_function_dt_node_to_map(), which provides
functionality not needed when the phandle target is unambiguous.

Maximize code reuse and provide a cleaner extension point for future
pinctrl drivers.

Suggested-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agodt-bindings: pinctrl: Add generic pinctrl for board-level mux chips
Frank Li [Mon, 4 May 2026 23:54:36 +0000 (19:54 -0400)]
dt-bindings: pinctrl: Add generic pinctrl for board-level mux chips

Add a generic pinctrl binding for board-level pinmux chips that are
controlled through the multiplexer subsystem.

On some boards, especially development boards, external mux chips are used
to switch SoC signals between different peripherals (e.g. MMC and UART).
The mux select lines are often driven by a GPIO expander over I2C,
as illustrated below:

┌──────┐      ┌─────┐
│ SOC  │      │     │    ┌───────┐
│      │      │     │───►│ MMC   │
│      │      │ MUX │    └───────┘
│      ├─────►│     │    ┌───────┐
│      │      │     │───►│ UART  │
│      │      └─────┘    └───────┘
│      │         ▲
│      │    ┌────┴──────────────┐
│ I2C  ├───►│ GPIO Expander     │
└──────┘    └───────────────────┘

Traditionally, gpio-hog is used to configure the onboard mux at boot.
However, the GPIO expander may probe later than consumer devices such as
MMC. As a result, the MUX might not be configured when the peripheral
driver probes, leading to initialization failures or data transfer errors.

Introduce a generic pinctrl binding that models the board-level MUX as a
pin control provider and builds proper device links between the MUX, its
GPIO controller, and peripheral devices. This ensures correct probe
ordering and reliable mux configuration.

The implementation leverages the standard multiplexer subsystem, which
provides broad support for onboard mux controllers and avoids the need for
per-driver custom MUX handling.

Allow pinctrl-* pattern as node name because this pinctrl device have not
reg property.

Reviewed-by: Linus Walleij <linusw@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agomux: add devm_mux_state_get_from_np() to get mux from child node
Frank Li [Mon, 4 May 2026 23:54:35 +0000 (19:54 -0400)]
mux: add devm_mux_state_get_from_np() to get mux from child node

Add new API devm_mux_state_get_from_np() to retrieve a mux control from
a specified child device node.

Make devm_mux_state_get() call devm_mux_state_get_from_np() with a NULL
node parameter, which defaults to using the device's own of_node.

Support the following DT schema:

pinctrl@0 {
    uart-func {
            mux-state = <&mux_chip 0>;
    };

    spi-func {
            mux-state = <&mux_chip 1>;
    };
};

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: qcom: add the TLMM driver for the Nord platforms
Bartosz Golaszewski [Mon, 4 May 2026 10:07:26 +0000 (12:07 +0200)]
pinctrl: qcom: add the TLMM driver for the Nord platforms

Add support for the TLMM controller on the Qualcomm Nord platform.

Co-developed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Maulik Shah <maulik.shah@oss.qualcomm.com>
Reviewed-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agodt-bindings: pinctrl: describe the Qualcomm nord-tlmm
Bartosz Golaszewski [Mon, 4 May 2026 10:07:25 +0000 (12:07 +0200)]
dt-bindings: pinctrl: describe the Qualcomm nord-tlmm

Add a DT binding document describing the TLMM pin controller available
on the Nord platforms from Qualcomm.

Co-developed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: sunxi: fix regulator leak in sunxi_pmx_request() error path
Felix Gu [Mon, 4 May 2026 14:53:26 +0000 (22:53 +0800)]
pinctrl: sunxi: fix regulator leak in sunxi_pmx_request() error path

In the error path of sunxi_pmx_request(), the code calls
regulator_put(s_reg->regulator) to release the regulator. However,
s_reg->regulator is only assigned after a successful regulator_enable().
This causes a memory leak: the regulator obtained via regulator_get()
is never properly released when regulator_enable() fails.

Fixes: dc1445584177 ("pinctrl: sunxi: Fix and simplify pin bank regulator handling")
Signed-off-by: Felix Gu <ustc.gu@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: mediatek: eint: Drop base from mtk_eint_chip_write_mask()
Chen-Yu Tsai [Mon, 27 Apr 2026 02:11:46 +0000 (10:11 +0800)]
pinctrl: mediatek: eint: Drop base from mtk_eint_chip_write_mask()

When support for multiple EINT base addresses was added in commit
3ef9f710efcb ("pinctrl: mediatek: Add EINT support for multiple
addresses"), mtk_eint_chip_write_mask() was changed to write interrupt
masks for all base addresses in one call. However the "base" parameter
was left around and now causes sparse warnings:

    mtk-eint.c:428:44: warning: incorrect type in argument 2 (different address spaces)
    mtk-eint.c:428:44:    expected void [noderef] __iomem *base
    mtk-eint.c:428:44:    got void [noderef] __iomem **base
    mtk-eint.c:436:44: warning: incorrect type in argument 2 (different address spaces)
    mtk-eint.c:436:44:    expected void [noderef] __iomem *base
    mtk-eint.c:436:44:    got void [noderef] __iomem **base

Since the "base" parameter is no longer needed, just drop it.

Fixes: 3ef9f710efcb ("pinctrl: mediatek: Add EINT support for multiple addresses")
Cc: Hao Chang <ot_chhao.chang@mediatek.com>
Cc: Qingliang Li <qingliang.li@mediatek.com>
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: starfive: jh7110: use struct_size
Rosen Penev [Sat, 25 Apr 2026 01:40:29 +0000 (18:40 -0700)]
pinctrl: starfive: jh7110: use struct_size

Instead of an extra kcalloc, Use a flexible array member to combine
allocations. Saves a pointer in the struct.

Signed-off-by: Rosen Penev <rosenp@gmail.com>
Acked-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: qcom: Unify user-visible "Qualcomm" name
Krzysztof Kozlowski [Wed, 22 Apr 2026 08:33:46 +0000 (10:33 +0200)]
pinctrl: qcom: Unify user-visible "Qualcomm" name

Various names for Qualcomm as a company are used in user-visible config
options: QCOM, Qualcomm and Qualcomm Technologies.  Switch to unified
"Qualcomm" so it will be easier for users to identify the options when
for example running menuconfig.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
[linusw@kernel.org: Also fix the new IPQ9650]
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: pinconf-generic: fix properties bitmap leak in parse_fw_cfg()
Felix Gu [Mon, 20 Apr 2026 10:55:55 +0000 (18:55 +0800)]
pinctrl: pinconf-generic: fix properties bitmap leak in parse_fw_cfg()

In parse_fw_cfg(), if fwnode_property_match_property_string() fails with
-ENOENT, the code returns directly and leaks the bitmap.

Use __free(bitmap) for automatic cleanup to fix the leak.

Fixes: 9c105255108b ("pinctrl: pinconf-generic: perform basic checks on pincfg properties")
Signed-off-by: Felix Gu <ustc.gu@gmail.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: qcom: eliza: Split QUP1_SE4 lanes
Alexander Koskovich [Thu, 23 Apr 2026 04:43:46 +0000 (04:43 +0000)]
pinctrl: qcom: eliza: Split QUP1_SE4 lanes

QUP1_SE4 shares GPIO_36 & GPIO_37 for both L0/L1 and L3/L2 so the
function name cannot be the same or the alternate function cannot
be selected.

Split them up into individual lane functions so boards can specify.

Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: qcom: eliza: Split QUP lane mirror alternates
Alexander Koskovich [Thu, 23 Apr 2026 04:43:37 +0000 (04:43 +0000)]
pinctrl: qcom: eliza: Split QUP lane mirror alternates

Several QUP lanes have MIRA/MIRB mirror routings which are collapsed
under a single function name (e.g. qup1_se6).

This is an issue because it means there are multiple functions defined
for a given pin that share the same name:

[42] = PINGROUP(42, qup1_se6, qup1_se2, qup1_se6...

So when you select pin 42 and request function qup1_se6, it will select
the first instance of it in this group, which just happens to be
QUP1_SE6_L2, making the second instance (QUP1_SE6_L1_MIRA) effectively
unreachable.

Split each of these lanes that has an alternative GPIO into their own
function so they can actually be selected, following the pattern seen
in pinctrl-sm8550.c.

Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agodt-bindings: pinctrl: qcom,eliza-tlmm: Split QUP1_SE4 lanes
Alexander Koskovich [Thu, 23 Apr 2026 04:43:27 +0000 (04:43 +0000)]
dt-bindings: pinctrl: qcom,eliza-tlmm: Split QUP1_SE4 lanes

QUP1_SE4 shares GPIO_36 & GPIO_37 for both L0/L1 and L3/L2 so the
function name cannot be the same or the alternate function cannot
be selected.

Split them up into individual lane functions so boards can specify.

Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agodt-bindings: pinctrl: qcom,eliza-tlmm: Split QUP lane mirror alternates
Alexander Koskovich [Thu, 23 Apr 2026 04:43:19 +0000 (04:43 +0000)]
dt-bindings: pinctrl: qcom,eliza-tlmm: Split QUP lane mirror alternates

Several QUP lanes have MIRA/MIRB mirror routings that let the same lane
be muxed out on alternative GPIOs. On Eliza these were all collapsed
under the base function name (e.g. qup1_se6), which prevented boards
from selecting the mirror variants.

Add explicit function names for each mirror lane, matching the pattern
already established by qcom,sm8550-tlmm and related bindings.

Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: pinconf-generic: Use kmemdup_array() over kmemdup()
Yash Suthar [Sat, 18 Apr 2026 19:11:24 +0000 (00:41 +0530)]
pinctrl: pinconf-generic: Use kmemdup_array() over kmemdup()

using kmemdup_array instead of kmemdup ,as it is more
readable and matches the intent of the api.
tested with w=1, no new warnings introduced.

Signed-off-by: Yash Suthar <yashsuthar983@gmail.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: qcom: Introduce IPQ9650 TLMM driver
Kathiravan Thirumoorthy [Wed, 15 Apr 2026 11:29:25 +0000 (16:59 +0530)]
pinctrl: qcom: Introduce IPQ9650 TLMM driver

Qualcomm's IPQ9650 comes with a TLMM block, like all other platforms,
so add a driver for it.

Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agodt-bindings: pinctrl: qcom: add IPQ9650 pinctrl
Kathiravan Thirumoorthy [Wed, 15 Apr 2026 11:29:24 +0000 (16:59 +0530)]
dt-bindings: pinctrl: qcom: add IPQ9650 pinctrl

Add device tree bindings for IPQ9650 TLMM block.

Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agodt-bindings: pinctrl: nvidia,tegra234: Correctly use additionalProperties
Krzysztof Kozlowski [Fri, 10 Apr 2026 11:10:49 +0000 (13:10 +0200)]
dt-bindings: pinctrl: nvidia,tegra234: Correctly use additionalProperties

The binding does not reference any other schema, thus should use
"additionalProperties: false" to disallow any undocumented properties.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agodt-bindings: pinctrl: nvidia,tegra234: Add missing required block
Krzysztof Kozlowski [Fri, 10 Apr 2026 11:10:48 +0000 (13:10 +0200)]
dt-bindings: pinctrl: nvidia,tegra234: Add missing required block

Binding should require 'reg' property, because address space cannot be
missing in the hardware and is already needed by the Linux drivers.
Require also 'compatible' by convention, although it is not strictly
necessary.

Fixes: 857982138b79 ("dt-bindings: pinctrl: Document Tegra234 pin controllers")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: vt8500: Enable compile testing
Krzysztof Kozlowski [Fri, 10 Apr 2026 13:04:58 +0000 (15:04 +0200)]
pinctrl: vt8500: Enable compile testing

Enable compile testing for Realtek pin controller drivers for increased
build and static checkers coverage.  PINCTRL_WMT uses
gpiochip_get_data(), thus needs GPIOLIB.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: aspeed: Enable compile testing outside of ARCH_ASPEED
Krzysztof Kozlowski [Fri, 10 Apr 2026 13:04:57 +0000 (15:04 +0200)]
pinctrl: aspeed: Enable compile testing outside of ARCH_ASPEED

Since inception in commit 4d3d0e4272d8 ("pinctrl: Add core support for
Aspeed SoCs"), the Aspeed pin controller drivers cannot be compile
tested, unless ARCH_ASPEED is selected.  .  That partially defeats the
purpose of compile testing, since ARCH_ASPEED is pulled when building
platform kernels.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: realtek: Enable compile testing
Krzysztof Kozlowski [Fri, 10 Apr 2026 13:04:56 +0000 (15:04 +0200)]
pinctrl: realtek: Enable compile testing

Enable compile testing for Realtek pin controller drivers for increased
build and static checkers coverage.  PINCTRL_RTD uses
pinconf_generic_dt_node_to_map(), thus needs OF.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Yu-Chun Lin <eleanor.lin@realtek.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: tegra: Enable easier compile testing
Krzysztof Kozlowski [Fri, 10 Apr 2026 10:30:06 +0000 (12:30 +0200)]
pinctrl: tegra: Enable easier compile testing

Currently NVIDIA Tegra pin controller drivers cannot be compile tested,
unless ARCH_TEGRA is selected.  That partially defeats the purpose of
compile testing, since ARCH_TEGRA is pulled when building platform
kernels.  Solve it and allow compile testing independently of ARCH_TEGRA
choice which requires few less usual changes:

1. Descent in Makefile in to drivers/pinctrl/tegra/ unconditionally,
   because there is no menu option.

2. Depend on COMMON_CLK for PINCTRL_TEGRA20, because it uses
   clk_register_mux().

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
4 months agopinctrl: renesas: rzg2l: Handle PUPD for RZ/V2H(P) dedicated pins in PM
Lad Prabhakar [Mon, 13 Apr 2026 18:24:55 +0000 (19:24 +0100)]
pinctrl: renesas: rzg2l: Handle PUPD for RZ/V2H(P) dedicated pins in PM

On RZ/V2H(P), dedicated pins support pull-up/pull-down configuration
via PIN_CFG_PUPD. Add PUPD handling for dedicated pins in the PM
save/restore path.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260413182456.811543-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 months agopinctrl: renesas: rzg2l: Add NOD register cache for PM suspend/resume
Lad Prabhakar [Mon, 13 Apr 2026 18:24:54 +0000 (19:24 +0100)]
pinctrl: renesas: rzg2l: Add NOD register cache for PM suspend/resume

Include the NOD (N-ch Open Drain) register in the PM suspend/resume
register cache.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260413182456.811543-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 months agopinctrl: renesas: rzg2l: Handle RZ/V2H(P) IOLH configuration in PM cache
Lad Prabhakar [Mon, 13 Apr 2026 18:24:53 +0000 (19:24 +0100)]
pinctrl: renesas: rzg2l: Handle RZ/V2H(P) IOLH configuration in PM cache

Include PIN_CFG_IOLH_RZV2H in the IOLH capability checks when saving
and restoring pin configuration registers.

On RZ/V2H(P), RZ/V2N, and RZ/G3E, the IOLH configuration is defined by
the PIN_CFG_IOLH_RZV2H capability.  The previous implementation did not
account for this, causing the IOLH registers to be skipped during PM
save/restore.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260413182456.811543-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 months agopinctrl: renesas: rzg2l: Add SR register cache for PM suspend/resume
Lad Prabhakar [Mon, 13 Apr 2026 18:24:52 +0000 (19:24 +0100)]
pinctrl: renesas: rzg2l: Add SR register cache for PM suspend/resume

Include the SR (Slew Rate) register in the PM suspend/resume register
cache.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260413182456.811543-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 months agopinctrl: renesas: rzg2l: Fix SMT register cache handling
Lad Prabhakar [Mon, 13 Apr 2026 18:24:51 +0000 (19:24 +0100)]
pinctrl: renesas: rzg2l: Fix SMT register cache handling

Store SMT register cache per bank instead of using a single array.

On RZ/V2H(P), RZ/V2N, and RZ/G3E, the SMT register is split across two
32-bit registers: bits 0/8/16/24 control pins 0-3, while pins 4-7 are
controlled by the corresponding bits in the next register.  The previous
implementation cached only a single SMT register, leading to incomplete
save/restore of SMT state.

Convert cache->smt to a per-bank array and allocate storage for both
halves.  Update suspend/resume handling to save and restore both SMT
registers when present.

Fixes: 837afa592c623 ("pinctrl: renesas: rzg2l: Add suspend/resume support for Schmitt control registers")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260413182456.811543-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 months agopinctrl: renesas: rzg2l: Fix incorrect PUPD register offset for high pins during...
Biju Das [Sat, 28 Mar 2026 09:05:45 +0000 (09:05 +0000)]
pinctrl: renesas: rzg2l: Fix incorrect PUPD register offset for high pins during suspend/resume

When saving/restoring pull-up/down register state during suspend/resume,
the second PUPD register access was incorrectly using the same base offset
as the first, effectively reading/writing the same register twice instead
of the adjacent one.

Add the correct + 4 byte offset to the second RZG2L_PCTRL_REG_ACCESS32
call so that pupd[1][port] is properly saved and restored from the next
32-bit register in the PUPD register pair, covering pins 4–7 of ports
with 4 or more pins.

Fixes: b2bd65fbb617 ("pinctrl: renesas: rzg2l: Add suspend/resume support for pull up/down")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260328090548.84124-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 months agoLinux 7.1-rc1
Linus Torvalds [Sun, 26 Apr 2026 21:19:00 +0000 (14:19 -0700)]
Linux 7.1-rc1

4 months agoMerge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Linus Torvalds [Sun, 26 Apr 2026 21:03:20 +0000 (14:03 -0700)]
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fix from Stephen Boyd:
 "One more fix for the merge window to avoid a boot hang on
  Raspberry Pi 3B by marking the VEC clk critical so that it
  doesn't get turned off and hang the bus"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: bcm: rpi: Mark VEC clock as CLK_IGNORE_UNUSED

4 months agoMerge tag 'tsm-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/devsec/tsm
Linus Torvalds [Sun, 26 Apr 2026 16:51:29 +0000 (09:51 -0700)]
Merge tag 'tsm-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/devsec/tsm

Pull PCIe TSP update from Dan Williams:
 "A small update for the TSM core. It is arguably a fix and coming in
  late as I have been offline the past few weeks:

   - Drop class_create() for the 'tsm' class"

* tag 'tsm-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/devsec/tsm:
  virt: coco: change tsm_class to a const struct

4 months agoMerge tag 'kbuild-fixes-7.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kbuil...
Linus Torvalds [Sun, 26 Apr 2026 00:04:15 +0000 (17:04 -0700)]
Merge tag 'kbuild-fixes-7.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kbuild/linux

Pull Kbuild fixes from Nicolas Schier:

 - builddeb - avoid recompiles for non-cross-compiles

   Avoid triggering complete rebuilds for non-cross-compile Debian
   package builds by only triggering the rebuild of host tools for
   actual cross-compile builds

 - Never respect CONFIG_WERROR / W=e to fixdep

   Avoid spurious rebuilds of fixdep w/ and w/o -Werror during a single
   kbuild invocation by never respecting CONFIG_WERROR for fixdep

* tag 'kbuild-fixes-7.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kbuild/linux:
  kbuild: Never respect CONFIG_WERROR / W=e to fixdep
  kbuild: builddeb - avoid recompiles for non-cross-compiles

4 months agoMerge tag 'power-utilities-2026.04.25' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Sat, 25 Apr 2026 23:58:34 +0000 (16:58 -0700)]
Merge tag 'power-utilities-2026.04.25' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux

Pull power utility updates from Len Brown:
 "x86_energy_perf_policy:
   - Initial SoC Slider support

 turbostat:
   - Display HT siblings in cpu# order
   - Add Module-ID column
   - Print Core-ID and APIC-ID in hex
   - Fix misc bugs"

* tag 'power-utilities-2026.04.25' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux:
  tools/power x86_energy_perf_policy: Version 2026.04.25
  tools/power x86_energy_perf_policy.8: Document SoC Slider Options
  tools/power x86_energy_perf_policy: Enhances SoC Slider related checks
  tools/power turbostat: v2026.04.21
  tools/power turbostat: Process HT siblings in CPU order
  tools/power turbostat: Show module_id column
  tools/power turbostat: Print core_id and apic_id in hex
  tools/power turbostat: Cleanup print helper functions
  tools/power turbostat: Fix --cpu-set 1 regression on HT systems
  tools/power turbostat: Fix --cpu-set 0 regression on HT systems
  tools/power turbostat: Fix unrecognized option '-P'
  tools/power turbostat: Fix AMD RAPL regression on big systems
  tools/power/x86: Add SOC slider and platform profile support

4 months agoMerge tag 'rtc-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
Linus Torvalds [Sat, 25 Apr 2026 23:39:03 +0000 (16:39 -0700)]
Merge tag 'rtc-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux

Pull RTC updates from Alexandre Belloni:
 "Subsystem:
   - add data_race() in rtc_dev_poll()

  Drivers:
   - remove i2c_match_id usage
   - abx80x: Disable alarm feature if no interrupt attached
   - ti-k3: support resuming from IO DDR low power mode"

* tag 'rtc-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux:
  rtc: abx80x: Disable alarm feature if no interrupt attached
  rtc: ntxec: fix OF node reference imbalance
  rtc: pic32: allow driver to be compiled with COMPILE_TEST
  rtc: ti-k3: Add support to resume from IO DDR low power mode
  rtc: cmos: Use platform_get_irq_optional() in cmos_platform_probe()
  dt-bindings: rtc: add olpc,xo1-rtc to trivial-rtc
  dt-bindings: rtc: sc2731: Add compatible for SC2730
  rtc: add data_race() in rtc_dev_poll()
  rtc: armada38x: zalloc + calloc to single allocation
  dt-bindings: rtc: isl12026: convert to YAML schema
  dt-bindings: rtc: microcrystal,rv3028: Allow to specify vdd-supply
  rtc: max77686: convert to i2c_new_ancillary_device
  dt-bindings: rtc: mpfs-rtc: permit resets
  rtc: rx8025: Remove use of i2c_match_id()
  rtc: rv8803: Remove use of i2c_match_id()
  rtc: rs5c372: Remove use of i2c_match_id()
  rtc: pcf2127: Remove use of i2c_match_id()
  rtc: m41t80: Remove use of i2c_match_id()
  rtc: abx80x: Remove use of i2c_match_id()

4 months agoMerge tag 'for-next-tpm-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git...
Linus Torvalds [Sat, 25 Apr 2026 23:20:52 +0000 (16:20 -0700)]
Merge tag 'for-next-tpm-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-tpmdd

Pull tpm updates from Jarkko Sakkinen:
 "Here are the accumulated fixes for 7.1-rc1 and a single structural
  change worth mentioning separately: Rafael's commit converting tpm_crb
  from ACPI driver to a platform driver"

* tag 'for-next-tpm-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-tpmdd:
  tpm: tpm_tis: stop transmit if retries are exhausted
  tpm: tpm_tis: add error logging for data transfer
  tpm: avoid -Wunused-but-set-variable
  tpm: Use kfree_sensitive() to free auth session in tpm_dev_release()
  tpm2-sessions: Fix missing tpm_buf_destroy() in tpm2_read_public()
  tpm: Fix auth session leak in tpm2_get_random() error path
  tpm: i2c: atmel: fix block comment formatting
  tpm_crb: Convert ACPI driver to a platform one
  tpm: Make tcpci_pm_ops variable static const

4 months agoMerge branches 'turbostat' and 'x86_energy_perf_policy' into power-utilities
Len Brown [Sat, 25 Apr 2026 18:26:32 +0000 (14:26 -0400)]
Merge branches 'turbostat' and 'x86_energy_perf_policy' into power-utilities

4 months agotools/power x86_energy_perf_policy: Version 2026.04.25
Len Brown [Sat, 25 Apr 2026 17:26:16 +0000 (13:26 -0400)]
tools/power x86_energy_perf_policy: Version 2026.04.25

Since v2025.11.22:
Initial SoC Slider support
SoC Slider is an SoC-wide power/performance policy setting.
On SoC Slider systems, EPP plays a diminished role.

Whitespace cleanup via: indent -npro -kr -i8 -ts8 -sob -l160 -ss -ncs -cp1

No functional changes

Signed-off-by: Len Brown <len.brown@intel.com>
4 months agotools/power x86_energy_perf_policy.8: Document SoC Slider Options
Len Brown [Sat, 25 Apr 2026 16:10:54 +0000 (12:10 -0400)]
tools/power x86_energy_perf_policy.8: Document SoC Slider Options

x86_energy_perf_policy accesses the SoC Slider via standard
user/kernel APIs to the processor_thermal_soc_slider driver.

Machines that support SoC Slider largely use it instead of EPP,
which may continue to exist in a diminished role, or vanish entirely.

Signed-off-by: Len Brown <len.brown@intel.com>
4 months agotools/power x86_energy_perf_policy: Enhances SoC Slider related checks
Len Brown [Wed, 15 Apr 2026 19:12:29 +0000 (15:12 -0400)]
tools/power x86_energy_perf_policy: Enhances SoC Slider related checks

When processor_thermal_soc_slider is loaded, its slider
and offset modparams are visible.  Check that the driver
actually registered the profile named "SoC Slider" before
reading or writing these modparams.

n.b. This utility allows writing the Slider and Offset modparams
even if the driver policy is not "balanced".  Currently the
processor_thermal_soc_slider consults those modparams
only in "balanced" mode.

Signed-off-by: Len Brown <len.brown@intel.com>
4 months agoclk: bcm: rpi: Mark VEC clock as CLK_IGNORE_UNUSED
Maíra Canal [Fri, 24 Apr 2026 15:34:52 +0000 (16:34 +0100)]
clk: bcm: rpi: Mark VEC clock as CLK_IGNORE_UNUSED

On Raspberry Pi 3B, the VEC clock is used by the VideoCore firmware
display driver, which remains active until the vc4 driver loads and
sends NOTIFY_DISPLAY_DONE. If this clock is disabled during boot, a bus
lockup happens and the firmware becomes unresponsive, causing a complete
system lockup.

Mark the VEC clock with CLK_IGNORE_UNUSED so it survives the unused
clock disablement and remains available until the vc4 driver takes over
display management.

Fixes: 672299736af6 ("clk: bcm: rpi: Manage clock rate in prepare/unprepare callbacks")
Reported-by: Mark Brown <broonie@kernel.org>
Closes: https://lore.kernel.org/r/5f0bec08-f458-4fba-8bf3-06817a100c4c@sirena.org.uk
Signed-off-by: Maíra Canal <mcanal@igalia.com>
Link: https://patch.msgid.link/20260401111416.562279-2-mcanal@igalia.com
Tested-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Brian Masney <bmasney@redhat.com> # Active contributor to clk
Reviewed-by: Stefan Wahren <wahrenst@gmx.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
4 months agoMerge tag 'fbdev-for-7.1-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git...
Linus Torvalds [Sat, 25 Apr 2026 14:48:33 +0000 (07:48 -0700)]
Merge tag 'fbdev-for-7.1-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/linux-fbdev

Pull fbdev fixes from Helge Deller:

 - request memory region before use (cobalt_lcdfb, clps711x-fb, hgafb)

 - reference cleanups in failure path (offb, savage)

 - a spelling fix (atyfb)

* tag 'fbdev-for-7.1-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/linux-fbdev:
  fbdev: hgafb: Request memory region before ioremap
  fbdev: clps711x-fb: Request memory region for MMIO
  fbdev: cobalt_lcdfb: Request memory region
  fbdev: atyfb: Fix spelling mistake "enfore" -> "enforce"
  fbdev: savage: fix probe-path EDID cleanup leaks
  fbdev: offb: fix PCI device reference leak on probe failure

4 months agoMerge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rmk/linux
Linus Torvalds [Sat, 25 Apr 2026 14:44:26 +0000 (07:44 -0700)]
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rmk/linux

Pull ARM updates from Russell King:

 - fix a race condition handling PG_dcache_clean

 - further cleanups for the fault handling, allowing RT to be enabled

 - fixing nzones validation in adfs filesystem driver

 - fix for module unwinding

* tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rmk/linux:
  ARM: 9463/1: Allow to enable RT
  ARM: 9472/1: fix race condition on PG_dcache_clean in __sync_icache_dcache()
  ARM: 9471/1: module: fix unwind section relocation out of range error
  fs/adfs: validate nzones in adfs_validate_bblk()
  ARM: provide individual is_translation_fault() and is_permission_fault()
  ARM: move FSR fault status definitions before fsr_fs()
  ARM: use BIT() and GENMASK() for fault status register fields
  ARM: move is_permission_fault() and is_translation_fault() to fault.h
  ARM: move vmalloc() lazy-page table population
  ARM: ensure interrupts are enabled in __do_user_fault()

4 months agoMerge tag 'trace-ring-buffer-v7.1-3' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Fri, 24 Apr 2026 22:17:23 +0000 (15:17 -0700)]
Merge tag 'trace-ring-buffer-v7.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace

Pull ring-buffer fix from Steven Rostedt:

 - Fix accounting of persistent ring buffer rewind

   On boot up, the head page is moved back to the earliest point of the
   saved ring buffer. This is because the ring buffer being read by user
   space on a crash may not save the part it read. Rewinding the head
   page back to the earliest saved position helps keep those events from
   being lost.

   The number of events is also read during boot up and displayed in the
   stats file in the tracefs directory. It's also used for other
   accounting as well. On boot up, the "reader page" is accounted for
   but a rewind may put it back into the buffer and then the reader page
   may be accounted for again.

   Save off the original reader page and skip accounting it when
   scanning the pages in the ring buffer.

* tag 'trace-ring-buffer-v7.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace:
  ring-buffer: Do not double count the reader_page

4 months agoMerge tag 'block-7.1-20260424' of git://git.kernel.org/pub/scm/linux/kernel/git/axboe...
Linus Torvalds [Fri, 24 Apr 2026 22:06:55 +0000 (15:06 -0700)]
Merge tag 'block-7.1-20260424' of git://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux

Pull block fixes from Jens Axboe:

 - Series for zloop, fixing a variety of issues

 - t10-pi code cleanup

 - Fix for a merge window regression with the bio memory allocation mask

 - Fix for a merge window regression in ublk, caused by an issue with
   the maple tree iteration code at teardown

 - ublk self tests additions

 - Zoned device pgmap fixes

 - Various little cleanups and fixes

* tag 'block-7.1-20260424' of git://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux: (21 commits)
  Revert "floppy: fix reference leak on platform_device_register() failure"
  ublk: avoid unpinning pages under maple tree spinlock
  ublk: refactor common helper ublk_shmem_remove_ranges()
  ublk: fix maple tree lockdep warning in ublk_buf_cleanup
  selftests: ublk: add ublk auto integrity test
  selftests: ublk: enable test_integrity_02.sh on fio 3.42
  selftests: ublk: remove unused argument to _cleanup
  block: only restrict bio allocation gfp mask asked to block
  block/blk-throttle: Add WQ_PERCPU to alloc_workqueue users
  block: Add WQ_PERCPU to alloc_workqueue users
  block: relax pgmap check in bio_add_page for compatible zone device pages
  block: add pgmap check to biovec_phys_mergeable
  floppy: fix reference leak on platform_device_register() failure
  ublk: use unchecked copy helpers for bio page data
  t10-pi: reduce ref tag code duplication
  zloop: remove irq-safe locking
  zloop: factor out zloop_mark_{full,empty} helpers
  zloop: set RQF_QUIET when completing requests on deleted devices
  zloop: improve the unaligned write pointer warning
  zloop: use vfs_truncate
  ...

4 months agoMerge tag 'io_uring-7.1-20260424' of git://git.kernel.org/pub/scm/linux/kernel/git...
Linus Torvalds [Fri, 24 Apr 2026 22:00:54 +0000 (15:00 -0700)]
Merge tag 'io_uring-7.1-20260424' of git://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux

Pull io_uring fixes from Jens Axboe:

 - Fix for a NOMMU bug with io_uring, where NOMMU doesn't grab page refs
   at mmap time. NOMMU also has entirely broken FOLL_PIN support, yet
   here we are

 - A few fixes covering minor issues introduced in this merge window

 - data race annotation to shut up KCSAN for when io-wq limits are
   applied

 - A nospec addition for direct descriptor file updating. Rest of the
   direct descriptor path already had this, but for some reason the
   update did not. Now they are all the same

 - Various minor defensive changes that claude identified and suggested
   terrible fixes for, turned into actually useful cleanups:

       - Use kvfree() for the imu cache. These can come from kmalloc or
         vmalloc depending on size, but the in-cache ones are capped
         where it's always kmalloc based. Change to kvfree() in the
         cleanup path, making future changes unlikely to mess that up

       - Negative kbuf consumption lengths. Can't happen right now, but
         cqe->res is used directly, which if other codes changes could
         then be an error value

 - Fix for an issue with the futex code, where partial wakes on a
   vectored fuxes would potentially wake the same futex twice, rather
   than move on to the next one. This could confuse an application as it
   would've expected the next futex to have been woken

 - Fix for a bug with ring resizing, where SQEs or CQEs might not have
   been copied correctly if large SQEs or CQEs are used in the ring.
   Application side issue, where SQEs or CQEs might have been lost
   during resize

 - Fix for a bug where EPOLL_URING_WAKE might have been lost, causing a
   multishot poll to not be terminated when it's nested, like it should
   have been

 - Fix for an issue with signed comparison of poll references for the
   slow path

 - Fix for a user struct UAF in the zcrx code

 - Two minor zcrx cleanups

* tag 'io_uring-7.1-20260424' of git://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux:
  io_uring: take page references for NOMMU pbuf_ring mmaps
  io_uring/poll: ensure EPOLL_ONESHOT is propagated for EPOLL_URING_WAKE
  io_uring/zcrx: warn on freelist violations
  io_uring/zcrx: clear RQ headers on init
  io_uring/zcrx: fix user_struct uaf
  io_uring/register: fix ring resizing with mixed/large SQEs/CQEs
  io_uring/futex: ensure partial wakes are appropriately dequeued
  io_uring/rw: add defensive hardening for negative kbuf lengths
  io_uring/rsrc: use kvfree() for the imu cache
  io_uring/rsrc: unify nospec indexing for direct descriptors
  io_uring: fix spurious fput in registered ring path
  io_uring: fix iowq_limits data race in tctx node addition
  io_uring/tctx: mark io_wq as exiting before error path teardown
  io_uring/tctx: check for setup tctx->io_wq before teardown
  io_uring/poll: fix signed comparison in io_poll_get_ownership()

4 months agoMerge tag 'nfs-for-7.1-1' of git://git.linux-nfs.org/projects/trondmy/linux-nfs
Linus Torvalds [Fri, 24 Apr 2026 21:20:03 +0000 (14:20 -0700)]
Merge tag 'nfs-for-7.1-1' of git://git.linux-nfs.org/projects/trondmy/linux-nfs

Pull NFS client updates from Trond Myklebust:
 "Bugfixes:

   - Fix handling of ENOSPC so that if we have to resend writes, they
     are written synchronously

   - SUNRPC RDMA transport fixes from Chuck

   - Several fixes for delegated timestamps in NFSv4.2

   - Failure to obtain a directory delegation should not cause stat() to
     fail with NFSv4

   - Rename was failing to update timestamps when a directory delegation
     is held on NFSv4

   - Ensure we check rsize/wsize after crossing a NFSv4 filesystem
     boundary

   - NFSv4/pnfs:

      - If the server is down, retry the layout returns on reboot

      - Fallback to MDS could result in a short write being incorrectly
        logged

  Cleanups:

   - Use memcpy_and_pad in decode_fh"

* tag 'nfs-for-7.1-1' of git://git.linux-nfs.org/projects/trondmy/linux-nfs: (21 commits)
  NFS: Fix RCU dereference of cl_xprt in nfs_compare_super_address
  NFS: remove redundant __private attribute from nfs_page_class
  NFSv4.2: fix CLONE/COPY attrs in presence of delegated attributes
  NFS: fix writeback in presence of errors
  nfs: use memcpy_and_pad in decode_fh
  NFSv4.1: Apply session size limits on clone path
  NFSv4: retry GETATTR if GET_DIR_DELEGATION failed
  NFS: fix RENAME attr in presence of directory delegations
  pnfs/flexfiles: validate ds_versions_cnt is non-zero
  NFS/blocklayout: print each device used for SCSI layouts
  xprtrdma: Post receive buffers after RPC completion
  xprtrdma: Scale receive batch size with credit window
  xprtrdma: Replace rpcrdma_mr_seg with xdr_buf cursor
  xprtrdma: Decouple frwr_wp_create from frwr_map
  xprtrdma: Close lost-wakeup race in xprt_rdma_alloc_slot
  xprtrdma: Avoid 250 ms delay on backlog wakeup
  xprtrdma: Close sendctx get/put race that can block a transport
  nfs: update inode ctime after removexattr operation
  nfs: fix utimensat() for atime with delegated timestamps
  NFS: improve "Server wrote zero bytes" error
  ...

4 months agoMerge tag 'ceph-for-7.1-rc1' of https://github.com/ceph/ceph-client
Linus Torvalds [Fri, 24 Apr 2026 20:47:19 +0000 (13:47 -0700)]
Merge tag 'ceph-for-7.1-rc1' of https://github.com/ceph/ceph-client

Pull ceph updates from Ilya Dryomov:
 "We have a series from Alex which extends CephFS client metrics with
  support for per-subvolume data I/O performance and latency tracking
  (metadata operations aren't included) and a good variety of fixes and
  cleanups across RBD and CephFS"

* tag 'ceph-for-7.1-rc1' of https://github.com/ceph/ceph-client:
  ceph: add subvolume metrics collection and reporting
  ceph: parse subvolume_id from InodeStat v9 and store in inode
  ceph: handle InodeStat v8 versioned field in reply parsing
  libceph: Fix slab-out-of-bounds access in auth message processing
  rbd: fix null-ptr-deref when device_add_disk() fails
  crush: cleanup in crush_do_rule() method
  ceph: clear s_cap_reconnect when ceph_pagelist_encode_32() fails
  ceph: only d_add() negative dentries when they are unhashed
  libceph: update outdated comment in ceph_sock_write_space()
  libceph: Remove obsolete session key alignment logic
  ceph: fix num_ops off-by-one when crypto allocation fails
  libceph: Prevent potential null-ptr-deref in ceph_handle_auth_reply()

4 months agoMerge tag 'ntfs-for-7.1-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git...
Linus Torvalds [Fri, 24 Apr 2026 20:40:25 +0000 (13:40 -0700)]
Merge tag 'ntfs-for-7.1-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/linkinjeon/ntfs

Pull ntfs updates from Namjae Jeon:

 - Fix potential data leakage by zeroing the portion of the straddle
   block beyond initialized_size when reading non-resident attributes

 - Remove unnecessary zeroing in ntfs_punch_hole() for ranges beyond
   initialized_size, as they are already returned as zeros on read

 - Fix writable check in ntfs_file_mmap_prepare() to correctly handle
   shared mappings using VMA_SHARED_BIT | VMA_MAYWRITE_BIT

 - Use page allocation instead of kmemdup() for IOMAP_INLINE data to
   ensure page-aligned address and avoid BUG trap in
   iomap_inline_data_valid() caused by the page boundary check

 - Add a size check before memory allocation in ntfs_attr_readall() and
   reject overly large attributes

 - Remove unneeded noop_direct_IO from ntfs_aops as it is no longer
   required following the FMODE_CAN_ODIRECT flag

 - Fix seven static analysis warnings reported by Smatch

* tag 'ntfs-for-7.1-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/linkinjeon/ntfs:
  ntfs: use page allocation for resident attribute inline data
  ntfs: fix mmap_prepare writable check for shared mappings
  ntfs: fix potential 32-bit truncation in ntfs_write_cb()
  ntfs: fix uninitialized variable in ntfs_map_runlist_nolock
  ntfs: delete dead code
  ntfs: add missing error code in ntfs_mft_record_alloc()
  ntfs: fix uninitialized variables in ntfs_ea_set_wsl_inode()
  ntfs: fix uninitialized pointer in ntfs_write_mft_block
  ntfs: fix uninitialized variable in ntfs_write_simple_iomap_begin_non_resident
  ntfs: remove noop_direct_IO from address_space_operations
  ntfs: limit memory allocation in ntfs_attr_readall
  ntfs: not zero out range beyond init in punch_hole
  ntfs: zero out stale data in straddle block beyond initialized_size

4 months agoMerge tag '9p-for-7.1-rc1' of https://github.com/martinetd/linux
Linus Torvalds [Fri, 24 Apr 2026 20:37:26 +0000 (13:37 -0700)]
Merge tag '9p-for-7.1-rc1' of https://github.com/martinetd/linux

Pull 9p updates from Dominique Martinet:

 - 9p access flag fix (cannot change access flag since new mount API implem)

 - some minor cleanup

* tag '9p-for-7.1-rc1' of https://github.com/martinetd/linux:
  9p/trans_xen: replace simple_strto* with kstrtouint
  9p/trans_xen: make cleanup idempotent after dataring alloc errors
  9p: document missing enum values in kernel-doc comments
  9p: fix access mode flags being ORed instead of replaced
  9p: fix memory leak in v9fs_init_fs_context error path