Arnd Bergmann [Thu, 11 Jun 2026 13:01:19 +0000 (15:01 +0200)]
drm/amd/display: avoid large stack allocation in commit_planes_do_stream_update_sequence
The function has two arrays on the stack to hold temporary dsc_optc_config
and dsc_config objects. The combination blows through common stack frame
warning limits in combination with the other local variables:
Since neither array is initialized or used outside of the
add_link_update_dsc_config_sequence() function, there is no actual
need to keep each element around.
Replace the arrays with a single instance each to reduce the stack usage
to less than half.
Fixes: 9f49d3cd7e71 ("drm/amd/display: Implement block sequencing infrastructure for modular hardware operations.") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Acked-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Hung [Mon, 15 Jun 2026 18:10:58 +0000 (12:10 -0600)]
drm/amd/display: Remove redundant IPS mode case for DCN 4.2
[WHAT]
Remove the redundant IP_VERSION(4, 2, 0) case from
dm_get_default_ips_mode() since it only reassigns the same
DMUB_IPS_ENABLE value already set at initialization.
Also remove the corresponding KUnit test.
Reviewed-by: Chenyu Chen <chen-yu.chen@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Taimur Hassan [Sat, 13 Jun 2026 08:02:41 +0000 (03:02 -0500)]
drm/amd/display: Promote DC to 3.2.387
DC Automatic Code Cutoff
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Acked-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Taimur Hassan [Fri, 12 Jun 2026 22:44:35 +0000 (18:44 -0400)]
drm/amd/display: [FW Promotion] Release 0.1.64.0
Added panel polarity feature
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Acked-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Austin Zheng [Tue, 9 Jun 2026 23:01:13 +0000 (19:01 -0400)]
drm/amd/display: Add Debug Option To Enable Per-DPM De-rate Usage
[Why]
DML has been updated to use per-DPM derates when provided but per-DPM de-rates have not been finalized.
Need to validate to see what values should be stored in the bounding box.
[How]
Add debug options to set custom derates per DPM (starting at DPM0) and their values
Each entry in the custom derate expects the derates to be stored in the following format:
bits 0-7: dram_derate_percent_pixel
bits 8-15: fclk_derate_percent
bits 16-23: dcfclk_derate_percent
bits 24-31 are unused.
e.g. Using the value 0x414020 will set the following derates for DPM0
DPM0: 0x20, 0x40, 0x41 for dram, fclk, and dcfclk respectively
Note that global derate value will be used if the per-DPM derate is 0.
Reviewed-by: Jun Lei <jun.lei@amd.com> Signed-off-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Chen [Tue, 9 Jun 2026 22:38:23 +0000 (18:38 -0400)]
drm/amd/display: Update ONO PG Workaround for DCN42
[Why & How]
There is an updated workaround for PG Repeater issue in DCN42. This PR is
addressing the dynamic power gating use cases (Driver PG) to align with
the new sequence.
Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Leo Chen <leo.chen@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Wed, 6 May 2026 00:45:10 +0000 (20:45 -0400)]
drm/amd/display: Update LSDMA commands to explicitly handle DCC fields
[Description]
- Previously linear copy commands for LSDMA assumed no DCC
- Update so that there is explicit assignment for DCC related fields
- Caller can 0 out the fields if DCC is not used
- For linear copy command don't subtract 1 from the count - this will
be done at a lower layer
Reviewed-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
George Shen [Wed, 22 Apr 2026 00:27:42 +0000 (20:27 -0400)]
drm/amd/display: Add flag to disable dynamic expansion for 12bpc
[Why]
Dynamic expansion is not needed when outputting 12bpc test patterns.
[How]
Add a debug flag to control disabling dynamic expansion in the case
of 12bpc test patterns.
Reviewed-by: Michael Strauss <michael.strauss@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chandana G B [Mon, 1 Jun 2026 05:39:55 +0000 (11:09 +0530)]
drm/amd/display: Fix intermittently CRC open failure during active rendering
[Why]
Opening the CRC data file during active rendering can fail with -EINVAL.
Closing the CRC data file with ctrl+C (which will send SIGINT to the kernel
and if the wait thread in sleep, kernel will send the -ERESTARTSYS to the
wait_for_completion_interruptible_timeout)
resulting in intermittently getting -ERESTARTSYS. which will just do the
clean up without releasing the vblank reference causing -EINVAL while opening
the crc data file in the next iteration
[How]
Ignoring the ERESTARTSYS as this is a return value for the
wait_for_completion_interruptible_timeout()
Reviewed-by: Chen-Yu Chen <chen-yu.chen@amd.com> Signed-off-by: Chandana G B <Chandana.GB@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Austin Zheng [Wed, 10 Jun 2026 13:22:47 +0000 (09:22 -0400)]
drm/amd/display: Allow Per-DPM De-rates Instead Of A Single Global Value
[Why]
Currently only a singular de-rate is used for all DPM levels.
The intent was to limit the bandwidth utilization at high DPMs
so the display requirements are not competing with other engines for bandwidth.
At lower DPMs, the de-rates could be more lenient so more bandwidth can be
utilized without the need to increase the DPM level and result in potential power savings.
i.e. DPM0 could be achieved on certain display configs instead of DPM1
if de-rates were a couple percentage points higher
The system average de-rates can be adjusted as needed as only urgent de-rates are defined for the SOC.
[How]
Update QOS parameters to have a table of derates with a per-DPM granularity
If the per-DPM value is provided, that will value be used.
Otherwise use the global value if there is no DPM specific value.
Reviewed-by: Jun Lei <jun.lei@amd.com> Signed-off-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Karen Chen [Wed, 10 Jun 2026 17:40:13 +0000 (13:40 -0400)]
drm/amd/display: Disable DPPCLK RCG to fix cursor disappearing
[Why & How]
DPP clock is gated when programming the cursor. This change
disables DPPCLK RCG in dccg42_init before accessing DPP,
ensuring cursor programming latches correctly.
Assisted-by: Cursor Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Karen Chen <Karen.Chen@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Harry Wentland [Wed, 10 Jun 2026 16:49:58 +0000 (12:49 -0400)]
drm/amd/display: split TF/LUT colorop state lookups into separate upfront phases
In __set_dm_plane_colorop_shaper and __set_dm_plane_colorop_blend the
single colorop_state variable was reused sequentially: first to capture
the TF state, then (after mutating the colorop pointer) to capture the
LUT state.
Split into separate tf_state / lut_state pointers and introduce a
dedicated lut_colorop local. Resolve both pointers upfront before any
computation begins. This separates the concern of "find the states" from
"use the states" and makes the code easier to follow.
No functional change.
Assisted-by: Copilot:claude-opus-4.8 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Harry Wentland [Wed, 10 Jun 2026 16:49:01 +0000 (12:49 -0400)]
drm/amd/display: drop redundant colorop type and TF checks
DRM core builds the curve_1d_type enum property with only the supported
TF values, so any curve_1d_type that reaches atomic_commit is already
guaranteed to be in the supported set. The per-colorop type field is
immutable — it cannot change between the loop that finds colorop_state
and the if block that uses it, so re-checking colorop->type there is
dead code.
Remove the redundant checks:
- colorop->type == DRM_COLOROP_1D_CURVE in the shaper TF if block
- colorop->type == DRM_COLOROP_1D_LUT in the shaper LUT if block
- colorop->type == DRM_COLOROP_1D_CURVE in the blend TF if block
- colorop->type == DRM_COLOROP_1D_LUT in the blend LUT if block
- BIT(colorop_state->curve_1d_type) & supported_blnd_tfs in the blend
TF if block (already guaranteed by the loop filter)
- BIT(colorop_state->curve_1d_type) & supported_blnd_tfs in the blend
LUT if block (nonsensical: a 1D_LUT colorop has no curve_1d_type)
No functional change.
Assisted-by: Copilot:claude-opus-4.8 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Matthew Stewart [Fri, 5 Jun 2026 19:05:46 +0000 (15:05 -0400)]
drm/amd/display: Remove DCCG registers not needed in DCN42
[why]
Some resources that exist in the DCN block are not needed and shouldn't
be used.
[how]
Remove defines from register lists.
Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
William Palacek [Mon, 25 May 2026 16:09:36 +0000 (12:09 -0400)]
drm/amdkfd: use scnprintf/vscnprintf in kfd_smi_event_add
snprintf() and vsnprintf() return the number of bytes that would have
been written if the buffer were large enough, not the actual bytes
written. If truncation occurs, the accumulated length can exceed the
buffer size, causing kfifo_in() to read past the fifo_in[] stack buffer.
Switch to scnprintf() and vscnprintf() which return the actual number
of bytes written, excluding the null terminator. This prevents the
potential buffer over-read when calculating the offset for subsequent
writes.
Signed-off-by: William Palacek <William.Palacek@amd.com> Reviewed-by: Alysa Liu <Alysa.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Matthew Stewart [Mon, 8 Jun 2026 15:22:02 +0000 (11:22 -0400)]
drm/amd/display: Rewrite dccg42_init
[why]
DCN42 reuses dccg42_init, which causes problems due to undefined masks.
[how]
- Read res_pool to determine the quantities of the respective resources
- Remove the physymclk root_clock_optimization check, as it seems like
it shouldn't do anything (defaults to disabled already).
Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The register lists used on DCN42 variants are different. Some reused
codepaths are trying to access registers not used.
[how]
Add DISPCLK_FREQ_CHANGECNTL, HUBPREQ_DEBUG, and HDMISTREAMCLK_CNTL to
the register lists.
Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ivan Lipski [Thu, 11 Jun 2026 14:18:24 +0000 (10:18 -0400)]
drm/amd/display: Reintroduce "Force validation link training on all ASICs"
[Why & How]
'skip_frl_pretraining' was introduced and enabled along w/ HDMI 2.1
initial upstream, but is causing HDMI validation link training to be s
kipped on short hotplugs and compliance issues.
Remove this behaviour to force link training on all hotplugs for all
ASICs.
Reviewed-by: Relja (Reggie) Vojvodic <relja.vojvodic@amd.com> Reviewed-by: Sun peng (Leo) Li <sunpeng.li@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Michael Strauss [Thu, 19 Feb 2026 16:15:24 +0000 (11:15 -0500)]
drm/amd/display: Add 12bpc Color Ramp Support
[WHY]
12bpc color ramp pattern was never implemented.
[HOW]
Add correct DPG_RAMP_CONTROL programming to match DP color ramp spec.
Reviewed-by: George Shen <george.shen@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lohita Mudimela [Mon, 25 May 2026 08:54:06 +0000 (14:24 +0530)]
drm/amd/display: Integrate power_helpers.c functionality into power.c.
[Why]
Reduces file fragmentation in the power module by consolidating
power_helpers.c . The helper file contained minimal
functionality (single utility function and shared includes) that
didn't warrant a separate compilation unit, leading to increased
build complexity and maintenance overhead.
[How]
Consolidated power_helpers.c content into the internal module
implementation. Moved macro outside
platform-specific conditional block for wider availability.
Reviewed-by: Josip Pavic <josip.pavic@amd.com> Signed-off-by: Lohita Mudimela <lohita.mudimela@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Piotr Maziarz [Fri, 22 May 2026 14:27:11 +0000 (16:27 +0200)]
drm/amd/display: Fix 4018 warning
[Why]
It is required by Security Guidance for All Software Components.
[How]
Change variable type to unsigned in dc\dml\dcn314\display_mode_vba_31.c
and dc\dml\dcn31\display_mode_vba_314.c.
Explicit cast to unsigned in dc\link\protocols\link_hdmi_frl.c.
Move warning from UNSOLVED set to SOLVED set.
Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Gabe Teeger [Fri, 5 Jun 2026 20:21:29 +0000 (16:21 -0400)]
drm/amd/display: Enable PSR and Replay on DCN4 variant and fix AUX instance
[Why]
Enable PSR and Panel Replay on a DCN4 variant for display power
savings. On links without native I2C (no DDC pin), the AUX channel
must use aux_hw_inst to avoid NULL pointer access during PSR and
Replay setup.
[How]
Enable PSR and Replay in the DCN4 variant panel config defaults.
Add no_ddc_pin check in dp_setup_panel_replay(),
edp_setup_freesync_replay(), and fsft_send_msg_to_fw() to use
link->aux_hw_inst when dp_connector_no_native_i2c and no_ddc_pin
are set.
Reviewed-by: Matthew Stewart <matthew.stewart2@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Matthew Stewart [Wed, 27 May 2026 18:39:47 +0000 (14:39 -0400)]
drm/amd/display: Add dcn42b_soc_and_ip_translator
[why]
DCN42B was not using its own max_ip_caps table. Need to create a
separate soc_and_ip_translator in order to not reuse the DCN42 one.
[how]
Separate DCN42B into its own soc_and_ip_translator.c file to handle this.
Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jesse Zhang [Sat, 20 Jun 2026 15:06:35 +0000 (23:06 +0800)]
drm/amdgpu: defer KCQ remap until after MES resume in reset flow
Split amdgpu_gfx_mes_reset_queue_start() into reset+unmap now and queue
reinit later, and do the remap only after amdgpu_mes_resume(). Avoids
re-adding legacy queues while MES gangs are still suspended.
Suggested-by: Shaoyun Liu <shaoyun.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jesse Zhang [Tue, 9 Jun 2026 02:00:48 +0000 (10:00 +0800)]
drm/amdgpu/gfx11: handle error interrupts for userqs
Call the new userq reset helper, and dispatch KQs first by ring_id
before falling back to the user-queue lookup.
v2: squash in fixes
Co-developed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse Zhang <jesse.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jesse Zhang [Mon, 22 Jun 2026 02:40:11 +0000 (10:40 +0800)]
drm/amdgpu/userq: add reset helper and identify guilty user queue
If we get an interrupt for a bad user queue (bad opcode, etc.), add
a helper to handle the reset for user queues.
v2: squash in fixes
v3:
- schedule the reset via amdgpu_userq_start_hang_detect_work() instead
of open-coding mod_delayed_work()
- drop the per-queue guilty flag; always reset the queue the hang
detect work belongs to, matching the non-compute reset path
Co-developed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse Zhang <jesse.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jesse Zhang [Sat, 20 Jun 2026 15:06:34 +0000 (23:06 +0800)]
drm/amdgpu/mes12: drop queue state on RESET_QUEUES unmap
Set remove_queue_after_reset=1 (MES >= 0x5a) so MES drops its internal
state instead of re-unmapping an already MMIO-reset queue, which can
timeout into a GPU reset.
Suggested-by: Shaoyun Liu <shaoyun.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Mon, 25 May 2026 15:34:27 +0000 (11:34 -0400)]
drm/amdgpu/vce: fix integer overflow in image size
Fix a security vulnerability where malicious VCE command streams
with oversized dimensions (e.g. 65536×65536) cause 32-bit integer
overflow, wrapping the calculated buffer size to 0. This bypasses
validation and allows GPU firmware to perform out-of-bound memory
access.
The fix uses 64-bit arithmetic to detect overflow and rejects
invalid dimensions before they reach the hardware.
V2: remove redundant check
V3: modify max height value
V4: remove size64
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Tue, 12 May 2026 14:29:36 +0000 (10:29 -0400)]
drm/amdgpu: fix division by zero with invalid uvd dimensions
When width or height is less than 16, width_in_mb or height_in_mb
becomes 0, leading to fs_in_mb being 0. This causes a division by
zero when calculating num_dpb_buffer in H264 and H264 Perf decode
paths.
Add validation to reject frames with width < 16 or height < 16
before performing any calculations that depend on these values.
V2: Format change - move up all vaiable definitions.
V3: Use warn_once to avoid spam.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Matthew Jacob [Fri, 19 Jun 2026 18:45:46 +0000 (11:45 -0700)]
drm/amdgpu: Support some Barco AMD based graphics adapters
These adapters typically are only supported by Barco on the
Windows platform. However, with these changes in the linux
driver, multiple monitor support should work correctly.
Signed-off-by: Matthew Jacob <mjacob@feralsw.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Huang [Fri, 19 Jun 2026 16:37:01 +0000 (12:37 -0400)]
drm/amdkfd: avoid PTL confused warning message
PTL is a special feature for gfxv9.4.4, but the warning is
always appearing on other ASICs when rocprof is running, it
causes confusion, so move hw_supported check earlier to
avoid it.
Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yongqiang Sun [Fri, 12 Jun 2026 17:03:35 +0000 (13:03 -0400)]
drm/amdkfd: drop struct kfd_signal_page wrapper
struct kfd_signal_page now only wraps a single uint64_t *kernel_address
pointer. Drop the wrapper struct (and the page_slots() helper) and store
the signal page pointer directly in kfd_process::signal_page.
Since the signal page is the GTT BO mapping provided by user mode and is
not owned by the events code, no separate allocation/free is needed for
it, so shutdown_signal_page() goes away as well.
No functional change intended.
Signed-off-by: Yongqiang Sun <Yongqiang.Sun@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lijo Lazar [Tue, 16 Jun 2026 04:44:58 +0000 (10:14 +0530)]
drm/amdgpu: bounds check ATOM IIO table parsing
atom_index_iio() parsed the IIO bytecode without bounds checks, allowing
out-of-bounds reads on a malformed VBIOS. Pass the BIOS size into
amdgpu_atom_parse() and bound the parse loops by it.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Assisted-by: Claude Code Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leorize [Tue, 19 May 2026 03:06:19 +0000 (20:06 -0700)]
drm/amd/display: set MSA MISC1 bit 6 when using VSC SDP for DCE 11.x
When BT.2020 colorimetry is selected, the driver sends information using
VSC SDP but does not set "ignore MSA colorimetry" bit on older GPUs with
DCE-based IPs. This causes certain sinks to prefer colorimetry
information in DP MSA, resulting in terrible color rendering ("dull"
colors) when HDR is enabled.
This commit wires up the MISC1 bit 6 for GPUs with DCE 11.x based IPs to
correctly configure sinks to ignore colorimetry information in MSA,
resolving the color rendering issue.
Timur Kristóf [Wed, 17 Jun 2026 19:14:28 +0000 (21:14 +0200)]
drm/amdgpu/gfx8: Enable IP block soft reset as a GPU recovery method
Enable IP block soft reset as a GPU recovery method for GFX8
graphics and compute rings.
Tested with the "hard_reset_cp_wait" test case from the
Hang Test Suite created by Natalie Vock and Konstantin Seurer.
This Vulkan testcase waits for an event that never occurs,
effectively a WAIT_REG_MEM packet that intentionally hangs.
IP block soft reset can resolve that hang and allow
the rest of the system to move on and keep functioning
without needing a full ASIC reset.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Timur Kristóf [Wed, 17 Jun 2026 19:14:27 +0000 (21:14 +0200)]
drm/amdgpu/gfx8: Fixup IP block soft reset
Always reset everything in the GFX block at once as opposed
to trying to figure out which blocks need to be reset based
on their busy flags. This makes the reset more robust and
predictable.
Increase delays when waiting for the GRBM and SRBM soft reset
to complete.
Call IP block suspend/resume to ensure correct operation now
that we no longer have pre/post_soft_reset().
Call clock/powergating functions, otherwise power consumption
will increase after the GFX IP block is soft reset.
Return correct error code to signal failure in case not all
rings are functional after the IP block is soft reset.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Timur Kristóf [Wed, 17 Jun 2026 19:14:26 +0000 (21:14 +0200)]
drm/amdgpu/gfx8: Adjust EDC GPR workaround
When the compute queue is unavailable to run the IB,
return -EBUSY instead of silently failing.
Make sure the IB is always executed during reset:
Set preempt condition (may be cleared during reset),
and flush HDP cache so the GPU sees the updated value.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Timur Kristóf [Wed, 17 Jun 2026 19:14:25 +0000 (21:14 +0200)]
drm/amdgpu/gfx8: Support COND_EXEC on compute rings
It is useful to minimize collateral damage during an IP block
soft reset. We can clear the COND_EXEC condition so that
only the currently executing submission is at risk.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Timur Kristóf [Wed, 17 Jun 2026 19:14:24 +0000 (21:14 +0200)]
drm/amdgpu/gfx8: Return error when testing all rings
The gfx_v8_0_cp_test_all_rings() function should return success
only when all ring tests were successful.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Timur Kristóf [Wed, 17 Jun 2026 19:14:23 +0000 (21:14 +0200)]
drm/amdgpu/gfx8: Stop CP and RLC during reset
The only case when they may not go idle is when we are dealing
with a GPU hang, in which case we should just forcibly disable
these even when they aren't idle.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Timur Kristóf [Wed, 17 Jun 2026 19:14:22 +0000 (21:14 +0200)]
drm/amdgpu: Add IP block soft reset as a GPU recovery method
Implement IP block soft reset as a recovery method that fits into
the current GPU recovery code as opposed to being hacked into the
full GPU reset code path.
This can gracefully handle GPU hangs when other reset methods
are not available or have failed. It makes sure to minimize
collateral damage (ie. affected non-guilty jobs) and does a
backup and restore on all affected queues.
Note that some of the new helpers may be useful for other
reset types as well, which we can explore later.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Timur Kristóf [Wed, 17 Jun 2026 19:14:17 +0000 (21:14 +0200)]
drm/amdgpu: Delete pre/post_soft_reset() from amd_ip_funcs
These functions were largely redundant with the respective
suspend() and resume() functions, the main difference being
that they were less used and therefore less likely to be
tested and correct.
Move anything relevant from pre/post_soft_reset()
that is not already done by suspend()/resume()
into the soft_reset() functions.
Note that future uses of soft_reset() will need to call
the suspend() / resume() functions and the necessary clock
and power gating functions.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yang Wang [Thu, 18 Jun 2026 04:54:14 +0000 (12:54 +0800)]
drm/amd/pm: fix amdgpu_pm_info power display units
amdgpu_pm_info displayed power sensor readings with the wrong fractional unit.
It treated the low byte of the raw sensor value as the decimal part of watts,
while that field represents milliwatts in the decoded value. As a result,
debugfs could report misleading SoC power when the remainder was not already
a two-digit centiwatt value.
Example with query = 0x00000354:
raw field value
---------------------
query >> 8 3 W
query & 0xff 84 mW
decoded power 3084 mW
output value
---------------------
before 3.84 W
after 3.08 W
Fixes: f0b8f65b4825 ("drm/amd/amdgpu: fix the GPU power print error in pm info") Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sunil Khatri [Fri, 19 Jun 2026 09:25:18 +0000 (14:55 +0530)]
drm/amdgpu: do not release the root bo after vm validate
Make sure to not release the vm root bo after vm validation
and to make that happen we moved the restore function within
amdgpu_userq_vm_validate function.
Also update the function name to reflect the intent.
Suggested-by: Christian König <christian.koenig@amd.com> Signed-off-by: Zhu Lingshan <lingshan.zhu@amd.com> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 6 May 2026 12:29:01 +0000 (14:29 +0200)]
drm/amdgpu: move suballoc defines into own header
Just some code cleanup, while at it remove outdated comment.
No functional change.
Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Timur Kristóf [Wed, 17 Jun 2026 19:14:16 +0000 (21:14 +0200)]
drm/amdgpu: Delete check_soft_reset() from amd_ip_funcs
This function is not called from anywhere anymore and
every implementation was bogus.
Some implementations checked busy flags of the IP blocks,
which are not really indicative of whether the block is
hung and needs to be reset. For example the blocks
could be busy just normally executing submissions,
and not need to be reset.
Other implementations checked IB tests, which is actually
more useful, but could still just indicate that an IP block
is executing submissions normally.
It is also unnecessary because the GPU recovery code path
already knows which ring is hung so we know exactly what
we need to reset.
Just delete check_soft_reset() entirely.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Timur Kristóf [Wed, 17 Jun 2026 19:14:15 +0000 (21:14 +0200)]
drm/amdgpu: Delete soft reset code from legacy display driver
This was basically dead code, not used or called from anywhere.
Now that DC is the default display driver for all ASICs,
it is unlikely that anyone wants to develop this further.
Display hang related work should be focused on DC.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Timur Kristóf [Wed, 17 Jun 2026 19:14:14 +0000 (21:14 +0200)]
drm/amdgpu: Delete GMC 8 soft reset
We should only reset the memory controller during ASIC reset
and only when it's absolutely necessary. Otherwise, resetting
the memory controller typically just breaks everything and
on dGPUs may also clear the contents of VRAM (it's unclear if
it really does, but it's likely).
Specifically for GMC 8, the memory controller is reset as part
of the ASIC reset and otherwise should be left alone.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Timur Kristóf [Wed, 17 Jun 2026 19:14:13 +0000 (21:14 +0200)]
drm/amdgpu: Clean up defunct soft reset from ASIC reset code path
Soft reset means resetting IP blocks individually using
a hardware interconnect (SRBM or GRBM) without assistance
from firmware.
Soft reset is a useful tool for implementing GPU recovery,
eg. it is already successfully used for SDMA queue resets.
It should be used by a GPU recovery method instead of
being called directly from the ASIC reset code path.
Currently, this is only used on Carrizo and Stoney,
but doesn't work well and fails on those chips.
A subsequent commit will add a working GFX8 recovery
implementation after the cleanups.
Note that this commit only cleans up the ASIC reset path,
which also unblocks more opportunities for cleanup for
the various IP blocks. Those will be done in subsequent commits.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Timur Kristóf [Wed, 17 Jun 2026 19:14:12 +0000 (21:14 +0200)]
drm/amdgpu: Clarify name of soft recovery to avoid confusion
Soft recovery is not the same as soft reset:
* Soft recovery attempts to resolve a GPU hang by sending a
command to terminate shaders.
* Soft reset completely re-initializes an entire device IP block,
which may affect multiple rings and jobs at the same time.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jakob Linke [Wed, 17 Jun 2026 06:24:15 +0000 (08:24 +0200)]
drm/amdgpu/soc24: reset dGPU if suspend got aborted
For SOC24 ASICs (RDNA4 / Navi 4x dGPUs) re-enabling PM features fails if an
S3 suspend got aborted, the same issue already handled for SOC21 and SOC15:
commit df3c7dc5c58b ("drm/amdgpu: Reset dGPU if suspend got aborted")
commit 38e8ca3e4b6d ("amdgpu/soc15: enable asic reset for dGPU in case of suspend abort")
The aborted resume fails with:
amdgpu: SMU: No response msg_reg: 6 resp_reg: 0
amdgpu: Failed to enable requested dpm features!
amdgpu: resume of IP block <smu> failed -62
Apply the same workaround for soc24: detect the aborted-suspend state at
resume via the sign-of-life register and reset the device before re-init.
This is a workaround till a proper solution is finalized.
Fixes: 98b912c50e44 ("drm/amdgpu: Add soc24 common ip block (v2)") Signed-off-by: Jakob Linke <jakob@linke.cx> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lijo Lazar [Mon, 18 May 2026 12:13:44 +0000 (17:43 +0530)]
drm/amdgpu: Validate ATPX buffer length before use
Add amdgpu_atpx_buffer_validate() to check that the returned ACPI
buffer is of type ACPI_TYPE_BUFFER, is large enough to hold the u16
size field, and that the BIOS-reported size does not exceed the actual
allocation length or fall below the minimum required by the caller.
Use it in VERIFY_INTERFACE and GET_PX_PARAMETERS callers.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Assisted-by: Claude Sonnet (Cursor AI) Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lijo Lazar [Mon, 18 May 2026 12:13:32 +0000 (17:43 +0530)]
drm/amdgpu: Validate ATIF buffer length before use
Add a min_size parameter to amdgpu_atif_call() to validate that the
returned ACPI buffer is of type ACPI_TYPE_BUFFER, holds at least a u16
size field, does not claim more data than was actually returned, and
meets the minimum size required by the calling function. Each caller
passes its required minimum via sizeof() or offsetof() of the expected
output struct and drops its own size check.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Assisted-by: Claude Sonnet (Cursor AI) Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Asad Kamal [Tue, 16 Jun 2026 14:25:08 +0000 (22:25 +0800)]
drm/amdgpu: guard zero divisors in soc_v1_0 partition code
Abort driver load when num_mem_partitions is zero since operation is
unreliable without valid memory partition info. Skip absent resources
in soc_v1_0_get_xcp_res_info() to avoid divide-by-zero on firmware-
reported zero instance counts.
v2: Remove redundant checks (Lijo)
v3: Return error instead when num_mem_partitions is zero (Lijo)
Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tvrtko Ursulin [Fri, 29 May 2026 09:34:36 +0000 (10:34 +0100)]
drm/amdgpu: Remove output parameter in bo list handling
Removing the output parameter from a few functions should result in more
readable code and also enables us to save some lines.
v2: fix build (Alex)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tvrtko Ursulin [Fri, 29 May 2026 09:34:35 +0000 (10:34 +0100)]
drm/amdgpu: Replace idr with xarray in amdgpu_bo_list
IDR is deprecated so let's replace it with xarray.
Conversion is mostly 1:1 apart from AMDGPU_BO_LIST_OP_UPDATE which was
implemented with idr_replace, and has now been replaced with a sequence of
xa_load and xa_cmpxchg. Should userspace attempt multi-threaded update
operations on the same handle it could theoretically hit a new -ENOENT
path. But I believe this is purely theoretical and still safe.
Also, since we have removed the RCU protection around the handle lookup we
also removed the RCU freeing of the list.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tvrtko Ursulin [Fri, 29 May 2026 09:34:34 +0000 (10:34 +0100)]
drm/amdgpu: Remove the bo list mutex
The bo list is immutable during command submission since the drm_exec
conversion so we can remove the mutex.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tvrtko Ursulin [Fri, 29 May 2026 09:34:33 +0000 (10:34 +0100)]
drm/amdgpu: Drop support for variable struct drm_amdgpu_bo_list_entry size
Userspace always uses struct drm_amdgpu_bo_list_in->bo_info_size equal to
sizeof(struct drm_amdgpu_bo_list_entry) and there are no plans to extend
it. Even if the structure is extended at some point, older kernels will
note that they do not support the additional fields by rejecting the new
structure size.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Suggested-by: Christian König <christian.koenig@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiang Liu [Wed, 17 Jun 2026 08:51:18 +0000 (16:51 +0800)]
drm/amdgpu: dump RAS EEPROM table via debugfs
When the RAS core manages the EEPROM, the eeprom_control is never
initialized (amdgpu_ras_init_badpage_info() returns early), so reading
ras/ras_eeprom_table in debugfs printed only a zeroed header and no
records, even though bad-page records exist in the RAS core EEPROM.
Source the table header and records from the RAS core EEPROM
(ras_core->ras_eeprom) in that case, reusing the existing output layout
so the debugfs node keeps the same format. Skip the dump when the
firmware manages the EEPROM, since the records are not stored in the
I2C-backed table then.
Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Prike Liang [Wed, 20 May 2026 03:22:12 +0000 (11:22 +0800)]
drm/amdgpu: add userq create and destroy tracepoints
Add ftrace events around user queue creation and destruction to profile
queue setup and teardown latency.
Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
projects / linux / log